115-T-7121TPA

Page 1 of 12 Digital Satellite Network Interface Module 115-T-7121TPA APPLICATIONS - Set-Top Box applications for DVB-S and DSS Digital Satellite MODEM FEATURES - 950 ~ 2150 MHz tuning range 1 ~ 45M symbol rate supported, thus suitable for SCPC and MCPC application Internal AGC monitor out I2C-bus control for tuner PLL and for LINK IC Loop through output Both parallel and serial output transport stream interface 22KHz tone output for LNB and DiSEqC Viterbi BER monitoring Regulated transport interface, DATA_CLK polarity selection supported System clock generation PLL with low frequency external clock H istory Initial Release Release 1.0 Release 1.1 Release 1.2 Nov. 15 1999 Nov. 5. 2000, port switching @ 1500Mhz Feb. 2. 2001, pin#10(PORT2) to GND HYNIX Semiconductor Co. LTD. System IC Division TEL: 82-2-3459-3168 Digital Satellite NIM Specification 1.2 Feb. 2001 Page 2 of 12 Contents 1. General Specification of RF Tuner........................................................................................................................3 2. Electrical Specification of RF Tuner.....................................................................................................................4 3. Tuner Synthesizer PLL Information......................................................................................................................4 4. General Specification of LINK IC.........................................................................................................................6 5. Electrical Specification of LINK IC ......................................................................................................................8 6. NIM Configuration...................................................................................................................................................8 Contents of Table Fig. 1 RF Tuner Block Diagram(ZIF version).......................................................................................................10 Fig. 2 LINK IC(HDM8513A) block diagram ........................................................................................................11 Fig. 3 Output Timing Diagram for DVB ................................................................................................................12 Fig. 4 Output Timing Diagram for DSS..................................................................................................................12 Digital Satellite NIM Specification 1.2 Feb. 2001 Page 3 of 12 1. General Specification of RF Tuner 1 1.1 Power Supply ITEM 5V Supply Voltage 5V Supply Current Tuning Voltage Tuning Current LNB Voltage LNB Supply Current MIN 4.75 TYPICAL 5 230 MAX 5.25 260 33 2 UNIT V mA V mA 28 30 500 mA 1.2 Ambient Conditions ITEM Operating Temperature Storage Temperature Operating Humidity Storage Humidity MIN 0 -20 TYPICAL MAX 60 70 85 90 UNIT °C °C % % 1.3 Antenna Terminal - RF Input: f-type, 75Ω - RF Loop-through: f-type, 75Ω 1.4 Down Conversion - Broad band IQ down conversion, integrated in ZIF IC 1.5 I/Q Demodulator - Integrated in ZIF IC 1.6 AGC Voltage - 0 ~ 5V DC 1 See Fig. 1 for block diagram. Digital Satellite NIM Specification 1.2 Feb. 2001 Page 4 of 12 2. Electrical Specification of RF Tuner Test Condition Supply voltage B+(5V): 5V±0.1V VT(30V): 28V±0.1V Ambient temperature: 25°C±5°C Ambient humidity: 65% ±10% ITEM 2.1 Input Level 2.2 Input VSWR 2.3 Noise Figure 2.4 3’rd Order Inter mo du- MIN -65 TYPICAL MAX -25 UNIT dBm CONDITION 2 6 40 3 12 dB -25dBm level dB difference lation Rejection Ratio 2.5 Local Oscillation -65 -50 dBm Signal Leakage at RF Input Terminal 2.6 Gain Deviation 2.7 Phase Noise @10KHz @100KHz 2.8 I/Q Level Imbalance 2.9 I/Q Phase Error 2.10 I/Q Baseband Flatness 2.11 I/Q Output Level 2.12 I/Q Output Impedance 5 -75 -95 10 -70 dB dBc/Hz 950~2150MHz -90 ±1 ±3 ±3 dB DEG dB mVp-p Ω I relative 600 250 1KΩ , 15pF load 3 . Tuner Synthesizer PLL Information 3.1 IC adopted : SP5769 3.2 I2C address: 0xC2, fixed internally Digital Satellite NIM Specification 1.2 Feb. 2001 Page 5 of 12 3.3 Write Registers MSB Prog. divider Prog. divider Control data Control data Byte1 Byte2 Byte3 Byte4 0 N7 1 C1 N14 N6 T2 C0 N13 N5 T1 RE N12 N4 T0 RS N11 N3 R3 P3 N10 N2 R2 P2 N9 N1 R1 P1 LSB N8 N0 R0 P0 A A A A A: Acknowledge bit N14~N0: Programmable divider bits N = N14 ×214 + N13 ×213 + … +N1 ×21 +N0 R3,R2,R1,R0: Reference Division Ratio(See Table 1) C0,C1: Charge pump current(See Table 2) RE, RS: Not used, for normal operation RE=0 and RS=don’t care T2,T1,T0: Test mode control, for normal operation T2=0 and T1=T0=don’t care P3,P2,P1,P0: Port output states, for normal operation P3=P2=P0=don’t care, P1 is used for switcing local oscillator, i.e. if fLO < 1500MHz then P1=1, else P1=0 Table 1 Reference Division Ratio (4MHz external reference) R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Ratio 2 4 8 16 32 64 128 256 24 5 10 20 40 80 160 320 Comparison frequency 2MHz 1MHz 500KHz 250KHz 125KHz 62.5KHz 31.25KHz 15.62KHz 166.67KHz 800KHz 400KHz 200KHz 100KHz 50KHz 25KHz 12.5KHz * Recommended, 125KHz Digital Satellite NIM Specification 1.2 Feb. 2001 Page 6 of 12 Table 2 Charge Pump Current C1 byte 5, bit 1 0 0 1 1 0 1 0 1 C0 byte 5, bit 2 MIN CURRENT(uA) TYPICAL MAX ±98 ±210 ±450 ±975 ±130 ±280 ±600 ±1300 ±162 ±350 ±750 ±1625 * Recommended, C1=1, C0=0 Example for determining programmable divider Desired channel frequency = LO frequency(fLO) = 1200MHz if fREF=125KHz thus ratio = 32, R3=0, R2=1, R1=0, R0=0 then Programmable divider = fLO (1/fREF) = (1200.0E6/1)(1/125.0E3) = 9600 = 0x2580 3.4 Read Register MSB Status byte Byte1 POR FL 0 0 0 0 0 LSB 0 A A: Acknowledge bit POR: Power-On reset indicator FL: PLL lock flag(FL=1 if locked) * PLL lock-up time: TBD 4. General Specification of LINK IC 2 4.1 IC adopted: HDM8513A 3 2 See Fig. 2 for block diagram. Register information is not included in this specification, see HDM8513A Users Manual for detail 3 Digital Satellite NIM Specification 1.2 Feb. 2001 Page 7 of 12 4.2 I2C address: 0xe8, fixed internally 4.3 Power Supply MIN 3.3V Supply Voltage 3.3V Supply Current 3.0 TYPICAL 3.3 367 (@30Msps, 1/2 inner rate) MAX 3.6 420 UNIT V mA 4.4 Ambient Conditions ITEM Operating Temperature Storage Temperature MIN -10 -65 TYPICAL MAX 70 150 UNIT °C °C 4.5 LINK IC functionality ITEM ADC System Clock Generation DESCRIPTION 6 bit dual sigma-delta ADC Internal PLL with external reference clock Root-raised cosine filter with roll-off 0.35 Digital carrier recovery loop (autonomous sweep functionality) Digital symbol recovery loop Digital AGC (0~3V DC) NOTE 60MHz QPSK Demodulation Viterbi Decoding Deinterleaving ReedSolomon Decoding Descrambling Viterbi BER Indicator 1/2, 2/3, 3/4, 5/6, 7/8 with constraint length K=7 interleaving depth I=12 (204, 188, 8) Energy dispersal descrambling Number of errors among 220 data bits 6/7 for DSS description. Digital Satellite NIM Specification 1.2 Feb. 2001 Page 8 of 12 Maximum symbol rate consideration @60MHz CLK Viterbi rate 1/2 2/3 3/4 5/6 7/8 MAX RATE[Msps] 45 45 40 36 34.2 Notes due to antialiasing limitation ″ due to system clock limitation ″ ″ 5. Electrical Specification of LINK IC 5.1 BER vs Eb/No characteristics INNER RATE 1/2 2/3 3/4 5/6 7/8 Eb/No THRESHOLD