GL6962

GL6962/GL6962A GL6962/GL6962A Low Voltage Universal Speech Network Description The GL6962 and GL6962A are bipolar integrated circuits that perform all speech and line interface functions required in fully electronic telephone sets. They perform electronic switching between dialing and speech. The ICs operate at line voltage down to 1.6V DC (with reduced performance) to facilitate the use of more telephone sets connected in parallel. PIN Configuration (TOP View) LN TGA1 1 2 3 4 16 15 14 13 SLPE AGC REG VCC MUTE DTMF IR VEE Features Low DC line voltage: operates down to 1.6V (excluding polarity guard) Voltage regulator with adjustable static resistance Provides a supply for external circuits Symmetrical high-impedance inputs (64k¥ Ø for ) dynamic, magnetic or piezo-electric microphones Asymmetrical high-impedance inputs(32k¥ Ø ) for electric microphones DTMF signal input with confidence tone MUTE input for pulse or DTMF dialing (GL6962) MUTE input for pulse or DTMF dialing (GL6962A) Receiving amplifier for dynamic, magnetic or piezo-electric earpieces. Large gain setting ranges on microphone and earpiece amplifiers. Line loss compensation (line current dependent) for microphone and earpiece amplifiers Gain control curve adaptable to exchange supply DC line voltage adjustment facility Packaged in 16 DIP/SOP. TGA2 QR RGA MICMIC+ Iref GL6962 5 6 7 8 12 11 10 9 * Pin 12 is active LOW(MUTE) for GL6962A 1 GL6962/GL6962A Block Diagram VCC LN 13 RGC 1 5 RGA IR 10 - 4 QR + TGC MIC 7 MIC- 6 dB + _ + _ RM 2 TGA1 + DTMF 11 3 TGA2 (1) MUTE 12 SUPPLY & REFERENCE MUTE CONTROL RM RGC TGC CURRENT REFERENCE LOW VOLTAGE CIRCUIT CURRENT CONTROL Ó 9 VEE 8 Iref 15 AGC 14 REG 16 SLPE * Pin 12 is active LOW ( MUTE ) for GL6962A. 2 GL6962/GL6962A Pin Description PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL LN TGA1 TGA2 QR RGA MICMIC+ Iref VEE IR DTMF MUTE VCC REG AGC SLPE DESCRIPTION Positive line terminal Gain adjustment: transmitting amplifier Gain adjustment: transmitting amplifier Non-inverting output: receiving amplifier Gain adjustment: receiving amplifier Inverting microphone input Non-Inverting microphone input Current stabilizer Negative line terminal Receiving amplifier input Dual-tone multi-frequency input Mute input (1) Positive decoupling Voltage regulator decoupling Automatic gain control input Slope (DC resistance) adjustment. (1) Pin 12 is active LOW ( MUTE ) for GL6962A. 3 GL6962/GL6962A Absolute Maximum Ratings SYMBOL VLN Iline PARAMETER Positive continuous line voltage Line Current R9 = 20 ; Note1 GL6962 ; GL6962A Input voltage on all other pins Positive input voltage Negative input voltage Total power dissipation R9 = 20 ; Note2 GL6962 ; GL6962A Operating ambient temperature Storage temperature MIN MAX 12 UNIT V - 140 VCC+0.7 -0.7 mA V V Vi Ptot Tamb Tstg -25 -40 666 +75 +125 mW ¡É ¡É Maximum Ratings are those values beyond which damage to the device may occur. Functional Operation should be restricted to the limits in the Electrical Characteristics tables or pin Descriptions section Notes to the Absolute Maximum Ratings 1. 2. Mostly dependent on the maximum required Tamb and on the voltage between LN and SLPE. Calculated for the maximum ambient temperature specified Tamb = 75¡ É and maximum junction temperature of 125¡ É . 4 GL6962/GL6962A Electrical Characteristics Iline = 11 to 140 mA, VEE = 0V, f = 800Hz; Tamb = 25¡ É; unless otherwise specified SYMBOL PARAMETER Supplies LN and VCC (Pin 1 and 13) VLN Voltage drop over circuit Between LN and VEE CONDITION MIC inputs open circuit Iline = 1mA Iline = 4mA Iline = 15mA Iline = 100mA Iline = 140mA Iline = 15mA RVA(LN to REG)=68 k§ Ù RVA(REG to SLPE)=39k§ Ù VCC = 2.8V Iline = 15mA MIN TYP MAX UNIT 3.55 4.9 - 1.6 1.9 4.0 5.7 3.5 4.5 0.9 4.25 6.5 7.5 1.35 V V V V V V V mA VLN ICC VCC MUTE = HIGH IP = 1.2mA IP = 0mA GL6962A MUTE = LOW IP = 1.2mA IP = 0mA Microphone inputs MIC- and MIC+ (pin 6 and 7) | Zi | Input inpedance Between MIC- and MIC+ Differential MIC- or MIC+ to VEE Single-ended CMRR Common mode rejection ratio GV Voltage gain MIC+ or MIC- Iline = 15mA to LN R7 = 68k§ Ù ¥ Ä vf G Gain variation with f = 300 and 3400 Hz frequency referred to 800Hz Voltage drop over circuit between LN and VEE with external resistor RVA Supply current Supply voltage available for peripheral circuitry GL6962 2.2 2.2 - 2.7 3.4 2.7 3.4 - V V V V 50.5 - 64 34 82 52.0 ¡ ¾ .2 0 53.5 - k§ Ù k§ Ù dB dB dB 5 GL6962/GL6962A SYMBOL PARAMETER DTMF input (pin 11) | Zi | Input impedance GV Voltage gain from DTMF to LN CONDITION MIN 24.0 - TYP 22 25.5 ¡¾ 0.2 - MAX 27.0 - UNIT k§ Ù Iline = 15mA R7 = 68k§ Ù ¥ Ä vf G Gain variation with frequency referred to 800f = 300 and 3400 Hz Hz Gain adjustment input TGA1 and TGA2 (pin 2 and 3) ¥ Äv G Transmitting amplifier gain variation by adjustment of R7 between TGA1 and TGA2 Sending adjustment output LN (pin 1) VLN(RMS) Output voltage (RMS value) THD = 10% Iline = 4mA Iline = 15mA Vno(RMS) Noise output voltage Iline = 15mA (RMS value) R7 = 68 k§ Ù 200 § Ù between MICand MIC+; psophometrically weighted dB dB -8 0 dB 1.7 - 0.8 2.3 -69 - V V dBmp Receiving amplifier input IR (pin 10) | Zi | Input impedance Receiving amplifier output QR (pin 4) | Zo | Output impedance GV Voltage gain from IR to QR 29.5 22 4 31.0 32.5 k§ Ù ¥ Ä vf G Iline = 15mA RL =300 ¥ Ø (from pin 9 to pin4) Gain variation with frequency referred to f = 300 and 3400 800Hz Hz ¥Ø dB - ¡¾ 0.2 - dB 6 GL6962/GL6962A SYMBOL Vo(RMS) PARAMETER Output voltage(RMS value) CONDITION THD = 2 % sinewave drive ; R4 = 100k¥ Ø Iline = 15mA ; Ip = 0mA ; RL = 150 ¥ Ø RL= 150 ¥ Ø THD = 10% ; R4 = 100 k¥ Ø; RL = 150 ¥ Ø Iline = 4mA Iline = 15mA ; R4 =100 k¥ Ø; IR open-circuit psophometrically weighted RL =300 ¥ Ø MIN TYP MAX UNIT 0.22 0.3 - 0.33 0.48 15 - V V mV Vo(RMS) Output voltage(RMS value) Vno(RMS) Noise output voltage (RMS value) - 50 - •V Gain adjustment input RGA (pin 5) ¥ Äv G Receiving amplifier gain Variation by adjustment of R4 between RGA and QR HIGH level input voltage LOW level input voltage Input current Voltage gain from DTMF to QR GL6962 GL6962A R4 =100 k¥ Ø; RL = 300 ¥ Ø MUTE = HIGH MUTE = LOW R6 =100 K¥ ø (between AGC and VEE) Iline = 70mA -5.8 -11 0 dB MUTE input (pin 12) VIH VIL IMUTE Gv 1.5 8 VCC 0.3 15 V V µA Reduction of gain - -19 -19 - dB dB Automatic gain control input AGC (pin 15) ¥ Äv G Controlling the gain from IR to QR and the gain from MIC+, MIC- to LN Gain control range - dB 7 GL6962/GL6962A Test Circuit Iline R1 620¥ Ø 1 13 VCC 100•F + VO 10 IR 4 QR C4 100pF 5 RGA C7 1 nF MIC+ 7 LN 11 DTMF R4 100k¥ Ø RL 600¥ Ø GL6962A MUTE 12 C1 + 100•F 10 to 140mA Vi MIC6 SLPE 16 TGA1 2 TGA2 3 REG 14 AGC 15 Iref 8 VEE 9 + 10•F Vi C6 100pF R9 20¥ Ø R7 68k¥ Ø C8 1 nF C3 4.7•F + R6 R5 3. 6k ¥Ø For measuring gain from MIC+ and MIC-, the MUTE input should be LOW or open-circuit. For measuring the DTMF input, the MUTE input should be HIGH. Inputs not being tested should be open-circuit. Fig. 1 Test circuit for defining GL6962 voltage gain of MIC+, MIC- and DTMF inputs. (Voltage gain is defined as GV = 20log |Vo/Vi| 8 GL6962/GL6962A Iline R1 620¥ Ø 1 13 VCC 100•F + VO 10 IR 4 QR C4 100pF 5 RGA C7 1 nF MIC+ 7 LN 11 DTMF R4 100k¥ Ø RL 600¥ Ø GL6962A MUTE 12 C1 + 100•F 10 to 140mA Vi MIC6 SLPE 16 TGA1 2 TGA2 3 REG 14 AGC 15 Iref 8 VEE 9 + 10•F C6 100pF R9 20¥ Ø R7 68k¥ Ø C8 1 nF C3 4.7•F + R6 R5 3. 6k ¥Ø For measuring gain from MIC+ and MIC-, the MUTE input should be HIGH. For measuring the DTMF input, the MUTE input should be LOW or open-circuit. Inputs not being tested should be open-circuit. Fig. 2 Test circuit for defining GL6962A voltage gain of MIC+, MIC- and DTMF inputs. (Voltage gain is defined as GV = 20log |Vo/Vi| 9 GL6962/GL6962A line R1 + 620¥ Ø 1 V 10 10µ ZL 11 C2 DTMF 4 QR R4 100k¥ Ø C4 100pF 5 C7 1 nF 13 CC 100•F ¥Ø IR GL6962 MIC+ Vi 6 MICSLPE TGA1 2 3 REG AGC 15 ref EE 140mA + 8 C1 100• 100pF R9 ¥Ø R7 ¥Ø C8 1 nF C3 4.7•F + R5 3. 6k ¥Ø Fig. 3 Test circuit for defining GL696 (Voltage gain is defined as G = 20log | o/V | 10 GL6962/GL6962A Iline + 100•F 600¥ Ø VO + ZL 10 10µF 1 LN R1 620¥ Ø 13 VCC IR 11 C2 DTMF 4 QR 100k C4 100pF 5 RGA C7 10 to 140mA 7 Vi 6 MICSLPE 16 TGA1 2 TGA2 3 REG 14 AGC 15 Iref 8 VEE 9 C1 100•F MIC+ + GL6962A MUTE 12 C6 100pF R9 20¥ Ø R7 68k¥ Ø 1 nF 4.7•F + R6 R5 ¥Ø Fig. 4 Test circuit for defining GL6962A voltage gain of receiving amplifier. (Voltage gain is defined as GV = 20log |Vo/Vi| 11 GL6962/GL6962A Application Circuit R1 620¥ Ø R2 130K R 10 13µ 12V C2 C5 10 1 LN 13 VCC C1 100µF + IR 100nF 4 QR Telephone Line R4 R3 3.92k C4 100pF 5 RGA C7 1 nF 7 MIC+ 11 DTMF from dial and control circuit 12 (1) GL6962 MUTE 6 MICSLPE 16 TGA1 2 R7 TGA2 3 REG 14 AGC 15 Iref 8 VEE 9 R8 390 C6 RVA(R16-14) R6 Zbal R9 20¥ Ø C8 1 nF C3 4.7•F + R5 3. 6k ¥Ø (1) Pin 12 is active LOW ( MUTE ) for GL6962A. Fig. 5 Typical application of GL6962, shown there with piezo-electric earpiece and DTMF dialing. (The diode bridge, the zener diode and R10 limit current into, and the voltage across, the circuit during line transients. A different protection requirement is required for pulse dialing or register recall.) 12