GM0936TQ

GM0936TQ GM0936TQ Voice-Band Audio CODEC for CDMA Features • Single 3-V operation • Low power consumption – Operating mode .... 20mW Typ – Power-down mode ... 1mW Typ • Combined A/D, D/A, and Filters • Electret microphone bias reference voltage available • Compatible with all digital signal processors (DSPs) • Programmable volume control • 300 Hz - 3.6 kHz Passband with Specified Master clock 48 LQFP (TOP VIEW) MICBIAS EXTMIC EARGS EARB MICGS MICIN 41 40 ____ EARA PDN MICSEL NC 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 NC 48 NC 47 • Designed for standard 2.048MHz master clock for U.S. Analog, U.S. Digital, CT2, DECT, GSM, and PCS Standards for Hand-held Battery-Powered Telephones • On-chip voltage references • Package Type : 48 LQFP, 20 DIP, 20 SOP 20 DIP/SOP (TOP VIEW) 46 45 44 43 42 NC ____ PDN EARA EARB EARGS Vcc __________ MICMUTE NC DIN FSR __________ EARMUTE 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 MICBIAS MICGS MICIN VMID GND NC NC DOUT FSX CLK NC NC AVcc NC NC NC NC DVcc NC __________ MICMUTE NC 1 2 3 4 5 6 7 8 9 10 11 12 39 38 VMID NC AGND NC NC NC NC NC NC DGND NC NC DIN FSR __________ EARMUTE NC CLK FSX DOUT NC NC NC 1 NC NC GM0936TQ Description The GM0936TQ contains A/D and D/A conversion functions integrated on a single chip, and utilizes the sigma-delta modulation technique to achieve high resolution data conversion and low power consumption. The GM0936TQ is an ideal analog front end device for high performance voice-band communication systems. Cellular telephone systems are targeted in particular; however, these integrated circuits can function in other systems including digital audio, telecommunications, and data acquisition. The transmit section is designed to interface directly with an electret microphone element. One of two microphone input signals, MICIN and EXTMIC, is selected by MICSEL. If MICSEL is floated or Low, then MICIN is selected, and if MICSEL is high, then EXTMIC is selected. The microphone input signal (MICIN and EXTMIC) is buffered, first-order low-pass filtered, and amplified with provision for setting the amplifier gain to accommodate a range of signal input levels. The amplified signal is 1bitmodulated by second-order sigma-delta modulator. The modulated signal is then applied to the input of high-performance FIR-type digital decimation filters with frequency response equalization. The resulting data is then clocked out of DOUT as a serial data stream. The receive section takes a frame of sereal data on DIN and converts it to analog through highperformance FIR-type digital interpolation filter together with frequency response equalization, second-order digital sigma-delta modulator, and analog reconstruction filters. On-chip voltage reference ensures a highly integrated solution and all internal voltage references are generated. An internal reference voltage, VMID, is used to develop the midlevel virtual ground for all the amplifier circuits and the microphone bias circuit.Another reference voltage, MICBIAS, can supply bias current for the microphone. Serial DSP interfaces for transmit and receive paths support directly industry standard DSP processors. The GM0936TQ devices are characterized for operation from -20 to 70¡ É . 2 GM0936TQ Block Diagram AVCC EXTMIC MICIN MICGS __________ EARMUTE MICMUTE VMID MICBIAS EARGS EARA EARB AGND DVCC DGND _ __ PDN ANALOG Σ ∆-MODULATOR SINC 3FILTER FIRFILTER CLK FSR FSX DIN DOUT VOLTAGE REFERENCE POST FILTER 1-BIT DAC INTERFACE FIRDIGITAL Σ ∆- SINC 2MODULATOR FILTER FILTER MICSEL Analog 2nd orderΣ -∆ Modulator Block Diagram x 1/2 Integrator1 1/2 Integrator2 Quantizer Y Digital 2nd order Σ -∆ Modulator Block Diagram x Quantizer Y 2 Delay2 Delay1 3 GM0936TQ Pin Description ANALOG SIGNALS TERMINAL NAME AGND AVcc EARA EARB EARGS EARMUTE_ MICBIAS MICGS MICIN MICMUTE_ LQFP 34 4 44 45 46 17 42 41 40 11 SOP&DIP 16 5 2 3 4 10 20 19 18 6 I/O DESCRIPTION Analog Ground Analog Power (3V) O O I I O O I I Earphone output Side-tone output Side-tone input Earphone output mute control signal Microphone bias Output of the internal microphone amplifier Microphone input Microphone input mute Bias voltage reference. A pair of external, lowleakage, high-frequency capacitors (1 µF and 470 pF) should be connected between VMID and ground for filtering Hand-free MIC-IN MIC-IN selection input. When float or low, MICSEL selects MICIN. When high, MICSEL selects EXTMIC. VMID 36 17 O ETMIC 39 N/A I MICSEL 38 N/A I 4 GM0936TQ Pin Description DIGITAL SIGNALS TERMINAL NAME CLK DGND DIN DOUT DVcc FSR FSX PDN_ LQFP 19 27 15 21 9 16 20 43 1,2,3, 5,6,7, 8,10, 12,13, 14,18, 22,23, 24,25, 26,28, 29,30, 31,32, 33,35 SOP&DIP 11 16 8 13 5 9 12 1 I/O I DESCRIPTION Clock input (2.048 MHz) Digital ground I O Receive data input Transmit data output Digital power (3 V) I I I Frame-synchronization clock input for receive channel Frame-synchronization clock input for receive channel Power-down input, Active Low NC 7, 14, 15 No internal connection 5 GM0936TQ Electrical Characteristics Absolute Maximum Ratings over operating free-air temperature range PARAMETER Supply Voltage Range Digital Input Voltage Range Analog Input Voltage Range SYMBOL DVCC, AVCC Vind Vina MIN - 0.3 - 0.3 - 0.3 TYP MAX 3.6 3.6 3.6 UNIT V V V Recommended Operating Conditions PARAMETER Supply Voltage High-level Input Voltage Low-level Input Voltage Operating free-air Temperature SYMBOL DVCC, AVCC VIH VIL TA -20 MIN 2.7 2.2 0.8 70 TYP 3.0 MAX 3.3 UNIT V V V ¡É Power Supply Characteristics, fCLK = 2.048 MHz, outputs not loaded, Vcc=3V, TA=25¡ É PARAMETER Power Dissipation , Operating Power Dissipation , Power down MIN TYP 18 1 MAX UNIT mW mW Digital Characteristics (TA=25¡ É, DVCC = AVCC = 3V) PARAMETER Input Capacitance Input Leakage Current Low-level output Voltage (IOL = 3.2mA) High-level output Voltage (IOH = -3.2mA) 2.4 - 10 MIN TYP MAX 10 10 0.4 UNIT pF §Ë V V 6 GM0936TQ Microphone interface PARAMETER VIO Input offset voltage at MICIN IIB Input bias current at MICIN 1.5 10000 3 1 TEST CONDITIONS MIN TYP MAX UNIT V I= 0 to 3 V +5 mV +200 nA MHz V/V µA mA B1 Unity-gain bandwidth, open loop at MICIN Av Large-signal voltage amplification at MICGS Iomax Maximum output current VMID MICBIAS(source only) Speaker interface PARAMETER VO(PP) AC output voltage IOmax Maximum output current ro Output resistance at EARA, EARB Gain change EARMUTE low, max level when muted -60 RL = 600 Ω 1 TEST CONDITIONS MIN TYP MAX UNIT 3 +1 Vpp mA Ω dB 7 GM0936TQ Analog Characteristics (TA=25¡ É DVCC = AVCC = 3V, fs = 8 KHz) , A/D Converter PARAMETER Oversampling Ratio Resolution Dynamic Range S/(N+THD) Output Sample Rate Maximum output current for MICBIAS Maximum output voltage for Microphone Amplifier 1 0.85 0.95 50 MIN TYP 128 13 70 52 8 bit dB dB KHz mA Vpp MAX UNIT Transmit filter transfer over recommended ranges of supply voltage and free-air temperature, CLK=2.048 MHz, FSX=8 kHz PARAMETER TEST CONDITIONS fMICIN = 50 Hz fMICIN = 200 Hz fMICIN = 300 Hz Gain relative to input signal at 1.02 kHz Input amplifier set for unity gain, the output for 400mVpp signal at MICGS is 0dB fMICIN = 1 kHz fMICIN = 2 kHz fMICIN = 3 kHz fMICIN = 3.3 kHz fMICIN = 3.8 kHz MIN TYP MAX UNIT 0.76 0.73 0.67 0 -1.9 -4.5 -5.4 -8.9 dB 8 GM0936TQ Transmit idle channel noise and distortion, linear mode selected, over recommended ranges of supply voltage and free-air temperature (see Notes 1 and 2) PARAMETER Transmit noise TEST CONDITIONS MICIN connected to MICGS through a 22 kΩ resistor MICIN to DOUT at 0 dBm0 Gain relative to input signal at 1.02 kHz MICIN to DOUT at -3 dBm0 MICIN to DOUT at -6 dBm0 MICIN to DOUT at -9 dBm0 MICIN to DOUT at -12 dBm0 MIN TYP MAX UNIT 178 53 52.3 51.9 50.7 49.0 dB µVrms Notes: 1. The input amplifier is set for inverting unity gain. 2. Transmit noise, linear mode: 200 µVrms is equivalent to -75 dB (referenced to device 0 dB level). D/A Converter PARAMETER Oversampling Ratio Resolution Dynamic Range S/(N+THD) Maximum output current (RL =600§ Ù ) Output Voltage Range 0.81 48 MIN TYP 128 13 67 54 +1 0.91 bit dB dB mA Vpp MAX UNIT Receive distortion, linear mode selected, over recommended ranges of supply voltage and free-air temperature PARAMETER TEST CONDITIONS DIN to EARA at 0 dBm0 Receive signal-to -distortion ratio with sine-wave input DIN to EARA at -3 dBm0 DIN to EARA at -6 dBm0 DIN to EARA at -9 dBm0 DIN to EARA at -12 dBm0 MIN TYP MAX UNIT 60 59.7 59.6 56.1 55.3 dB 9 GM0936TQ Power supply rejection over recommended ranges of supply voltage and operating free-air temperature PARAMETER Supply voltage rejection, transmit channel Supply voltage rejection, receive channel TEST CONDITIONS Idle channel, supply signal = 100mVrms f = 1 kHz (measured at DOUT) Idle channel, supply signal = 100mVrms f = 1 kHz (measured at EARA) MIN TYP MAX UNIT -50 dB -50 dB 10 GM0936TQ Timing (TA=25¡ É DVCC = AVCC = 3V) , PARAMETER CLK Frequency Sampling Rate DOUT Delay from CLK DIN Delay from CLK MIN TYP 2.048 8 35 35 MAX UNIT MHz KHz ns ns Clock timing requirements MIN Duty cycle, CLK 45% NOM MAX UNIT 50% 55% Transmit timing requirements MIN tsu(FSX) th(FSX) Setup time, FSX high before CLK ¡ é Hold time, FSX high after CLK ¡ é 20 20 MAX 468 468 UNIT ns ns Receive timing requirements MIN tsu(FSR) th(FSR) tsu(DIN) th(DIN) Setup time, FSR high before CLK ¡ é Hold time, FSR high after CLK ¡ é Setup time, DIN high or low before CLK ¡ é Hold time, DIN high or low after CLK ¡ é 20 20 20 20 MAX 468 468 UNIT ns ns ns ns 11 GM0936TQ Timing Diagram Receive Time Slot 0 CLK FSR 20% 80% 1 th(FSR) 2 3 4 15 16 80% 17 ≈ See Note A See Note B 20% tsu(FSR) ≈ DIN 15 16 1 2 3 4 ≈≈ th(DIN) 15 16 tsu(DIN) 1 See Note C NOTES: A. This window is allowed for FSR high. B. This window is allowed for FSR low. C. Transitions are measured at 50%. Figure1. Receive Side Timing Diagram Transmit Time Slot 0 CLK FSX 20% 80% 1 th(FSX) 2 3 4 15 16 80% 20% 17 tsu(FSX) See Note A DOUT tpd1 1 2 3 ≈≈ See Note B tpd2 ≈ ≈ tpd3 4 15 16 See Note C NOTES: A. This window is allowed for FSX high. B. This window is allowed for FSX low. C. Transitions are measured at 50%. Figure2. Transmit Side Timing Diagram 12 GM0936TQ PRINCIPLES OF OPERATION power-down operation To minimize power consumption, a power-down mode is provided. For power down, an external low signal is applied to PDN. In the absence of a signal, PDN is internally pulled up to a high logic level and the device remains active. In the power-down mode, the average power consumption is reduced to 1mW. Timing FSX and FSR are inputs that set the sampling frequency. Data is transmitted on DOUT on the positive transitions of CLK following the rising edge of FSX. Data is received on DIN on the falling edges of CLK following FSR. Table 1. Power-On and Power-Down Procedures DEVICE STATUS PROCEDURE PDN =high, FSX = pulses, FSR = pulses PDN =low, FSX,FSR =X TYPICAL POWER CONSUMPTION 20 mW DIGITAL OUTPUT STATUS Power on Digital outputs active Power down X = dont care 1 mW DOUT in the high-impedance state 13 GM0936TQ PRINCIPLES OF OPERATION transmit operation microphone input The microphone input amplifier is designed specifically to interface to electret-type microphone elements, as shown in Figure 3. The VMID buffer circuit provides a voltage (MICBIAS) as a bias voltage to the electret microphone. The microphone amplifier output (MICGS) is used in conjunction with a feedback network and applied to the amplifier inverting input (MICIN) to set the amplifier gain. VMID appears at a terminal to provide a place to filter the VMID voltage. VMID 36 4.4 µ F 470 pF VMID Reference For Amplifiers MICBIAS 42 2.2 nF 2 kΩ Reference Voltage Generator MICGS 41 100nF 22 kΩ 22 kΩ Microphone Amplifier To 2nd-order Σ−∆ Modulator MICIN 40 Electret Microphone GM0936TQ NOTE A: Terminal numbers shown are for the 48 LQFP package. Figure 3. Typical Microphone Interface microphone mute function The MICMUTE input causes the digital circuitry to transmit all zero code on DOUT. transmit filter A low-pass antialiasing section is implemented by connecting a RC-pair externally between MICGS and MICIN. The RC-pair, together with the microphone amplifier, provides a single-pole low pass filter. The antialiased signal is 1bit-modulated by second-order sigma-delta modulator. The modulated signal is then applied to the input of high-performance FIR-type digital decimation filters with frequency response equalization. 14 GM0936TQ PRINCIPLES OF OPERATION encoding The encoder performs an A/D conversion on a 2nd-order Sigma-Delta (Σ-∆) modulator using a switched-capacitor technology and high-performance FIR-type digital decimation filters with frequency response equalization. The resulting data is then clocked out of DOUT as a serial data. data word structure The data word is 16 bits long. The first 13 bits comprises the audio data sample, and the last three bits form the volume control word in the receive direction (DIN) and are zero pad bits in the transmit direction (DOUT). The sign bit is transmitted first. receive operation decoding The serial data word is received at DIN on the first 13 clock cycles. The receive section converts a frame of sereal data to analog through high-performance FIR-type digital interpolation filter together with frequency response equalization, second-order digital sigma-delta modulator, and analog reconstruction filters. receive buffer The receive buffer contains the volume control. earphone amplifier The output can be used to drive a single-ended load with the output signal voltage centered around VMID. EARA in Figure 4 is the output pin for the decoded analog signal. EARB in the figure is used for sidetone signal output which is used internally. A resistor-capacitor pair attached to EARB is embedded to reduce the number of on-board components. See the next section for more information on sidetone generation. 15 GM0936TQ PRINCIPLES OF OPERATION 40 pF 50 kΩ 30 kΩ 44 EARA 50 kΩ 40 pF VMID 30 kΩ VMID 45 EARB 40 pF 100 kΩ 46 EARGS GM0936TQ NOTE A: Terminal numbers shown are for the 48 LQFP package. Figure 4. Earphone Audio-Output Amplifier Configuration receive data format In the decoding operation, 16 bits of data are received. The first 13 bits are the D/A code, and the remaining three bits from the volume control word(see Table 2). The volume control function is actually an attenuation control in which the first bit received is the most significant. The maximum volume occurs when all three volume control bits are zero. Eight levels of attenuation are selectable in 3-dB steps, giving a maximum attenuation of 21 dB when all bits are 1s. The volume control bit are not latched into the GM0936TQ and must be present in each received data word. 16 GM0936TQ Table 2. Receive-Data Bit Definitions BIT NO. 0 1 2 3 4 5 6 7 8 9 A B C D E F Data D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 V2 V1 V0 MSB (sign bit) LSB D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 V2 V1 V0 PCM Data Time Volume Control Where: D12-D0 = PCM Data word V2, V1, V0 = Volume (attenuation control) 000 = maximum volume, 0 dB 111 = minimum volume, -21 dB 17 GM0936TQ APPLICATION INFORMATION output gain set and sidetone considerations The single-ended outputs EARA and EARB are capable of driving output power level up to 1mW into load impedance of 1kΩ separately.The sidetone signal and the received signal can be summed by configuring external components like in Figure 5. The amount of sidetone mixing is controlled by the resistor connected between EARB and EARGS. If the resistance become greater, the amount of sidetone mixing increases. EARA 44 To speaker driving amp. EARB 42 GM0936TQ 1 kΩ EARGS 46 2.2 nF 41 100 kΩ MICGS 40 22 kΩ 22 kΩ 100nF MICIN Electret Microphone NOTE A: Terminal numbers shown are for the 48 TQFP package. Figure 5. Configuration for Gain-Setting and Sidetone higher clock frequencies and sample rates The GM0936TQ is designed to work with sample rates up to 16kHz where the frequency of the frame sync determines the sampling frequency. However, there is a fundamental requirement to maintain the ratio of the master clock frequency, fCLK, to the frame sync frequency, fFSR/ fFSX. This ratio for the GM0936TQ is 2.048 MHz/8 kHz, or 256 master clocks per frame sync. For example, to operate the GM0936TQ at a sampling rate of fFSR and fFSX equal to 16 kHz, fCLK must be 256 times 16 kHz, or 4.096 MHz. If the GM0936TQ is operated above an 8-kHz sample rate, however, it is expected that the performance becomes somewhat degraded. Exact parameter specifications for rates up to 16-kHz sample rate are not specified at this time. 18 GM0936TQ 19 GM0936TQ 20 GM0936TQ 21