GM72V66841ET-7

GM72V66841ET/ELT 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM Description T he GM72V66841ET/ELT is a synchronous dynamic random access memory comprised of 67,108,864 memory cells and logic including input and output circuits operating synchronously by referring to the positive edge of the externally provided Clock. The GM72V66841ET/ELT provides four banks of 2,097,152 word by 8 bit to realize high bandwidth with the Clock frequency up to 143 Mhz. Pin Configuration VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC /WE /CAS /RAS /CS BA0/A13 BA1/A12 A10,AP A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 JEDEC STANDARD 400 mil 54 PIN TSOP II (TOP VIEW) Features * PC133/PC100/PC66 Compatible -7(143MHz)/-75(133MHz)/-8(125MHz) -7K(PC100,2-2-2)/-7J(PC100,3-2-2) * 3.3V single Power supply * LVTTL interface * Max Clock frequency 143/133/125/100MHz * 4,096 refresh cycle per 64 ms * Two kinds of refresh operation Auto refresh / Self refresh * Programmable burst access capability ; - Sequence:Sequential / Interleave - Length :1/2/4/8/FP * Programmable CAS latency : 2/3 * 4 Banks can operate independently or simultaneously * Burst read/burst write or burst read/single write operation capability * Input and output masking by DQM input * One Clock of back to back read or write command interval * Synchronous Power down and Clock suspend capability with one Clock latency for both entry and exit * JEDEC Standard 54Pin 400mil TSOP II Package VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS Pin Name CLK CKE CS RAS CAS WE A0~A9,A11 A10 / AP BA0/A13 ~BA1/A12 DQ0~DQ7 DQM VCCQ VSSQ V CC VSS NC Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address input Address input or Auto Precharge Bank select Data input / Data output Data input / output Mask V CC f or DQ V SS f or DQ Power for internal circuit Ground for internal circuit No Connection This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any -1responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1/Apr.01 GM72V66841ET/ELT Block Diagram A0 to A13 A0 to A8 A0 to A13 Column address counter Column address buffer Row address counter Refresh counter Row decoder Row decoder Row decoder Row decoder Column decoder Sense amplifier & I/O bus Column decoder Sense amplifier & I/O bus Column decoder Sense amplifier & I/O bus Memory array Bank 0 4096 row x 512 column x 8 bit Memory array Bank 1 4096 row x 512 column x 8 bit Memory array Bank 2 4096 row x 512 column x 8 bit Column decoder Sense amplifier & I/O bus Memory array Bank 3 4096 row x 512 column x 8 bit Input buffer Output buffer Control logic & timing generator RAS CAS WE CKE CLK DQ0 to DQ7 DQM -2- Rev. 1.1/Apr.01 CS GM72V66841ET/ELT Absolute Maximum Ratings Parameter Voltage on any pin relative to VSS Supply voltage relative to V SS Short circuit output current Power dissipation Operating temperature Storage temperature Notes : 1. Respect to VS S Symbol VT V CC I OUT PT Topr Tstg Value -0.5 to Vcc+0.5 ( =VCC - 0.2 V IL