H55S5132DFR-A3M

512MBit MOBILE SDR SDRAMs based on 4M x 4Bank x32 I/O Specification of 512M (16Mx32bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 4,194,304 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.5 / Jan. 2009 1 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series Document Title 4Bank x 4M x 32bits Synchronous DRAM Revision History Revision No. 0.1 0.2 0.3 1.0 1.1 1.2 1.3 1.4 1.5 Initial Draft Correction - PKG Height: 1.0mm (without Ball Height) -> 1.0mm (with Ball Height) Update: IDD values Final Version -. Corrected the description of BURST TERMINATE -. Corrected the CKE state on every command -. Deleted the extended temperature products Modify : tRAS (166MHz/133Mhz: 42ns/45ns) Modify : tCK (CL=2, 166MHz [12ns -> 9.6ns]) Insert the reduced page Information Change the ball height (page 54) History Draft Date Sep. 2007 Feb. 2008 Mar. 2008 Apr. 2008 May 2008 Jun. 2008 Jul. 2008 Jul. 2008 Jan. 2009 Remark Preliminary Preliminary Preliminary Rev 1.5 / Jan. 2009 2 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series DESCRIPTION The Hynix H55S5122DFR is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, hand-held PCs. The Hynix 512M Mobile SDRAM is 536,870,912-bit CMOS Mobile Synchronous DRAM(Mobile SDR), ideally suited for the main memory applications which requires large memory density and high bandwidth. It is organized as 4banks of 4,194,304x32. Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x32 Input/ Output bus. All the commands are latched in synchronization with the rising edge of CLK. The Mobile SDRAMs provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8 locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The Mobile SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randomaccess operation. Read and write accesses to the Hynix Mobile SDRAMs are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. A burst of Read or Write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or Write command on any cycle(This pipelined design is not restricted by a 2N rule). The Hynix Mobile SDR also provides for special programmable options including Partial Array Self Refresh of full array, half array, quarter array Temperature Compensated Self Refresh of 45 or 85 degrees oC. The Hynix Mobile SDR has the special Low Power function of Auto TCSR(Temperature Compensated Self Refresh) to reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to automatically adjust refresh rate according to temperature without external EMRS command. Deep Power Down Mode is a additional operating mode for Mobile SDR. This mode can achieve maximum power reduction by removing power to the memory array within each Mobile SDR. By using this feature, the system can cut off almost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout flexibility. All inputs are LV-CMOS compatible. Devices will have a VDD and VDDQ supply of 1.8V (nominal). Rev 1.5 / Jan. 2009 3 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series INFORMATION for Hynix KNOWN GOOD DIE With the advent of Multi-Chip package (MCPs), Package on Package (PoP) and system in a package (SiP) applications, customer demand for Known Good Die (KGD) has increased. Requirements for smaller form factors and higher memory densities are fueling the need for Wafer-level memory solutions due to their superior flexibility. Hynix Known Good Die (KGD) products can be used in packaging technologies such as systems-in-a-package (SIPs) and multi-chip packages (MCPs) to reduce the board area required, making them ideal for hand-held PCs, and many other portable digital applications. Hynix Mobile DRAM will be able to continue its constant effort of enabling the Advanced package products of all application customers. - Please Contact Hynix Office for Hynix KGD product availability and informations. Rev 1.5 / Jan. 2009 4 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series FEATURES ● ● ● Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK) MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - During burst Read or Write operation, a different bank is activated and burst Read or Write for that bank is performed - During auto precharge burst Read or Write, burst Read or Write for a different bank is performed ● ● ● ● ● ● ● ● Power Supply Voltage: VDD = 1.8V, VDDQ = 1.8V LVCMOS compatible I/O Interface Low Voltage interface to reduce I/O power Programmable burst length: 1, 2, 4, 8 or full page Programmable Burst Type: sequential or interleaved Programmable CAS latency of 3 or 2 Programmable Drive Strength Low Power Features - Programmable PASR(Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - Programmable DS (Drive Strength) - Deep Power Down Mode ● ● Operation Temperature - Mobile Temp.: -30oC ~ 85oC Package Type: 90ball FBGA, 0.8mm pitch, 8 x 13 [mm2], t=1.0mm max, Lead & Halogen Free 512M SDRAM ORDERING INFORMATION Part Number H55S5122DFR-60M H55S5122DFR-75M H55S5122DFR-A3M H55S5132DFR-60M H55S5132DFR-75M H55S5132DFR-A3M Clock Frequency 166MHz 133MHz 105MHz 4banks x 4Mb x 32 166MHz 133MHz 105MHz 1KBytes (Reduced) LVCMOS 2KBytes (Normal) 90 Ball FBGA Lead & Halogen Free Page Size Organization Interface Package Rev 1.5 / Jan. 2009 5 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series BALL DESCRIPTION (A13 is used as 1KBytes reduced page) 1 A B C D E F G H J K L M N P R DQ 26 DQ 28 VSSQ 2 DQ 24 VDDQ DQ 27 DQ 29 DQ 31 DQM 3 A5 3 VSS VSSQ DQ 25 DQ 30 NC 4 6 7 VDD VDDQ DQ 22 DQ 17 NC 8 DQ 23 VSSQ DQ 20 DQ 18 DQ 16 DQM 2 A0 BA 1 /CS 9 DQ 21 DQ 19 VDDQ VSSQ VDDQ VDDQ VSSQ VSS A3 A2 VDD A4 A6 A10 A1 A7 A8 A12 CLK CKE A9 TOP VIEW A13 BA 0 /CAS A11 /RAS DQM 0 DQM 1 VDDQ NC DQ 8 DQ 10 DQ 12 VDDQ DQ 15 NC /WE DQ 7 DQ 5 DQ 3 VSSQ DQ 0 VSS DQ 9 DQ 14 VSSQ VDD DQ 6 DQ 1 VDDQ VSSQ VSSQ VDDQ VSSQ DQ 11 DQ 13 VDDQ DQ 4 DQ2 VSS VDD Rev 1.5 / Jan. 2009 6 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series BALL DESCRIPTION SYMBOL TYPE DESCRIPTION Clock: The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Clock Enable: Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Chip Select: Enables or disables all inputs except CLK, CKE, DQM0~DQM3 Bank Address: Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity For 1KBytes Page Size, Row Address: RA0 ~ RA13, Column Address: CA0 ~ CA7 A0 ~ A13 INPUT For 2KBytes Page Size, Row Address: RA0 ~ RA12, Column Address: CA0 ~ CA8 Auto-precharge flag: A10 Command Inputs: RAS, CAS and WE define the operation Refer function truth table for details Data Mask: Controls output buffers in read mode and masks input data in write mode Data Input/Output: Multiplexed data input/output pin Power supply for internal circuits Power supply for output buffers No connection CLK INPUT CKE INPUT CS INPUT BA0, BA1 INPUT RAS, CAS, WE INPUT DQM0 ~ DQM3 INPUT DQ0 ~ DQ31 VDD/VSS VDDQ/VSSQ NC I/O SUPPLY SUPPLY - Rev 1.5 / Jan. 2009 7 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series ABSOLUTE MAXIMUM RATING Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature . Time Symbol TA TSTG VIN, VOUT VDD VDDQ IOS PD TSOLDER Rating -30 ~ 85 -55 ~ 125 -1.0 ~ 2.6 -1.0 ~ 2.6 -1.0 ~ 2.6 50 1 260 . 20 Unit o C C o V V V mA W oC . Sec DC OPERATING CONDITION (TA= -30 to 85oC) Parameter Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage Note: 1. All Voltages are referenced to VSS = 0V 2. VDDQ must not exceed the level of VDD Symbol VDD VDDQ VIH VIL Min 1.7 1.7 0.8*VDDQ -0.3 Typ 1.8 1.8 Max 1.95 1.95 VDDQ+0.3 0.3 Unit V V V V Note 1 1, 2 1, 2 1, 2 - AC OPERATING TEST CONDITION (TA= -30 to 85 oC, VDD = 1.8V, VSS = 0V) Parameter AC Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise/Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Symbol VIH / VIL Vtrip tR / tF Voutref CL Value 0.9*VDDQ/0.2 0.5*VDDQ 1 0.5*VDDQ 30 Unit V V ns V pF Note Rev 1.5 / Jan. 2009 8 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series CAPACITANCE (TA= 25 oC, f=1MHz) 6/H Parameter Pin CLK Input capacitance Data input/output capacitance A0~A13, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM0~3 DQ0 ~ DQ31 Symbol Min CI1 CI2 CI/O 2 2 2 Max 4.0 4.0 4.5 pF pF pF Unit DC CHARACTERRISTICS I (TA= -30 to 85oC) Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Note: 1. VIN = 0 to 1.8V. All other pins are not tested under VIN=0V. 2. DOUT is disabled. VOUT= 0 to 1.95V. 3. IOUT = - 0.1mA 4. IOUT = + 0.1mA Symbol ILI ILO VOH VOL Min -1 -1 VDDQ-0.2 - Max 1 1 0.2 Unit uA uA V V Note 1 2 3 4 Rev 1.5 / Jan. 2009 9 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series DC CHARACTERISTICS II (TA= -30 to 85oC) Speed Parameter Symbol Test Condition 166MHz 133MHz 105MHz Operating Current Precharge Standby Current in Power Down Mode IDD1 IDD2P IDD2PS Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mA CKE ≤ VIL(max), tCK = 15ns CKE ≤ VIL(max), tCK = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V CKE ≥ VIH(min), tCK = ∞ Input signals are stable. CKE ≤ VIL(max), tCK = 15ns CKE ≤ VIL(max), tCK = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V CKE ≥ VIH(min), tCK = ∞ Input signals are stable. tCK ≥ tCK(min), IOL=0mA All banks active tRFC ≥ tRFC(min) CKE ≤ 0.2V See the pages for the Deep Power Down operation. 70 60 45 0.3 0.3 45 mA mA mA 1 Unit Note Precharge Standby Current in Non Power Down Mode IDD2N 5 mA IDD2NS Active Standby Current IDD3P in Power Down Mode IDD3PS 1 5 mA 3 Active Standby Current IDD3N in Non Power Down Mode IDD3NS Burst Mode Operating IDD4 Current Auto Refresh Current Self Refresh Current Standby Current in Deep Power Down Mode Notes: 10 mA 5 60 100 See Next Page 10 60 mA mA mA uA 2 3 1 IDD5 IDD6 IDD7 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. See the tables of next page for more specific IDD6 current values. 3. Please contact Hynix office for more information and ability for DPD operation. Deep Power Down operation is a hynix optional function. Rev 1.5 / Jan. 2009 10 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series DC CHARACTERISTICS III - Low Power (IDD6) Temp. (oC) 45 85 1. VDD / VDDQ = 1.8V 2. Related numerical values in this 45oC are examples for reference sample value only. 3. With a on-chip temperature sensor of Mobile memory, auto temperature compensated self refresh will automatically adjust the interval of self-refresh operation according to ambient temperature variations. Memory Array 4 Banks 250 500 2 Banks 220 400 1 Bank 200 350 Unit uA uA Rev 1.5 / Jan. 2009 11 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) 166MHz Parameter System Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width CAS Latency=3 Access Time From Clock CAS Latency=2 Data-out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command Setup Time Command Hold Time CLK to Data Output in Low-Z Time CLK to Data Output in High-Z Time CAS Latency=3 CAS Latency=2 Notes: 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF> 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR> 1ns, then (tR/2-0.5)ns should be added to the parameter. 3. Output Load: 30pF+No termination ● ● ● ● ● AC high level input voltage / low level input voltage: 1.6 / 0.2V Z = 50Ω tCK tCH tCL 1.6V 0.9V 0.2V tSETUP tHOLD 1.6V 0.9V 0.2V 133MHz Min 7.5 12 2.5 2.5 2.6 2.0 1.0 2.0 1.0 2.0 1.0 2.0 1.0 1.0 Max 1000 1000 6.0 8.0 6.0 8.0 105MHz Unit Note Min 9.5 15 3.0 3.0 2.6 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 1.0 Max 1000 1000 7.0 10 7.0 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 2, 3 2, 3 3 1 1 1 1 1 1 1 1 Symbol Min Max 1000 1000 5.4 6.0 5.4 6.0 tCK3 tCK2 tCHW tCLW tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ3 tOHZ2 6.0 9.6 2.0 2.0 2.6 2.0 1.0 2.0 1.0 2.0 1.0 2.0 1.0 1.0 CAS Latency=3 CAS Latency=2 Input timing measurement reference level: 0.9V Transition time (input rise and fall time): 0.5ns Output CLK 30pF Output Load Input Output timing measurement reference level: 0.9V Output load: CL = 30pF Output tAC tOH Rev 1.5 / Jan. 2009 12 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) 166MHz Parameter Symbol Min RAS Cycle Time RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay AUTO REFRESH Period CAS to CAS Delay Write Command to Data-In Delay Data-in to Precharge Command Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data Output High-Z CAS Latency=3 CAS Latency=2 tRC tRCD tRAS tRP tRRD tRFC tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 2 0 2 3 2 1CLK + tCKS 120 60 18 42 18 12 72 1 0 2 Max 100K Min 72.5 22.5 45 22.5 15 72 1 0 2 Max 100K Min 90 28.5 60 28.5 19 72 1 0 2 Max 100K ns ns ns ns ns ns CLK CLK CLK 133MHz 105MHz Unit Note tDPL+tRP 2 0 2 3 2 1CLK + tCKS 120 2 0 2 3 2 1CLK + tCKS 120 CLK CLK CLK CLK CLK Power Down Exit Time tDPE - - - CLK Self Refresh Exit Time Refresh Time tXSR tREF 64 64 64 ns ms Rev 1.5 / Jan. 2009 13 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series FUNCTIONAL BLOCK DIAGRAM 4Mbit x 4banks x 32 I/O Mobile Synchronous DRAM P A SR E x tend ed M od e R eg ister Self refresh log ic & tim er Internal R ow C ou nter C LK CKE State Machine CS RAS CAS WE DQM 0 ~3 R o w A ctive Row P re D eco d er Row decoders 4M x32 BAN K3 4 M x3 2 B A N K 2 4 M x3 2 B A N K 1 4M x 3 2 B A N K 0 Row decoders Sense AMP & I/O Gate Row decoders DQ0 Output Buffer & Logic Row decoders R efresh C olu m n A ctive M em ory C ell A rray 32 C olum n P re D eco d er DQ 31 C olu m n d ecod ers B ank Select A0 A1 A d d ress R eg ister C olu m n A d d C ou nter B u rst C o un ter CAS Latenc y Address Buffers Burst Length A13 BA1 B A0 M od e R eg ister D ata O ut C on trol (A13 is used as 1KBytes reduced page) Rev 1.5 / Jan. 2009 14 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series BASIC FUNCTIONAL DESCRIPTION Mode Register BA1 0 BA0 0 A13 0 A12 0 A11 0 A10 0 A9 OP Code A8 0 A7 0 A6 (A13 is used as 1KBytes reduced page) A5 A4 A3 BT A2 A1 A0 CAS Latency Burst Length OP Code A9 0 1 Write Mode Burst Read and Burst Write Burst Read and Single Write Burst Type A3 0 1 Burst Type Sequential Interleave CAS Latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved Burst Length Burst Length A3 = 0 1 2 4 8 Reserved Reserved Reserved Full page A3=1 1 2 4 8 Reserved Reserved Reserved Reserved A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Rev 1.5 / Jan. 2009 15 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series BASIC FUNCTIONAL DESCRIPTION (Continued) Extended Mode Register BA1 1 BA0 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 A6 DS (A13 is used as 1KBytes reduced page) A5 A4 0 A3 0 A2 A1 PASR A0 DS (Driver Strength) A7 0 0 0 0 1 A6 0 0 1 1 0 A5 0 1 0 1 0 Driver Strength Full 1/2 Strength 1/4 Strength Reserved 3/4 Strength PASR (Partial Array Self Refresh) A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Self Refresh Coverage All Banks Half of Total Bank (BA1=0 or Bank 0,1) Quarter of Total Bank (BA1=BA0=0 or Bank 0) Reserved Reserved Half of Bank 0(Bank 0 and Row Address MSB=0) Quarter of Bank 0(Bank 0 and Row Address 2 MSBs=0) Reserved Rev 1.5 / Jan. 2009 16 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series COMMAND TRUTH TABLE Function Mode Register Set Extended Mode Register Set No Operation Device Deselect Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst stop Data Write/Output Enable Data Mask/Output Disable Auto Refresh Self Refresh Entry Self Refresh Exit Precharge Power Down Entry Precharge Power Down Exit Clock Suspend Entry Clock Suspend Exit Deep Power Down Entry Deep Power Down Exit Notes: 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high. 2. BA1/BA0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set. CKEn-1 H H H H H H H H H H H H H H H H L CKEn X X X X X X X X X X X X X X H L H CS L L L H L L L L L L L L RAS L L H X L H H H H L L H X X CAS L L H X H L L L L H H H WE L L H X H H H L L L L L DQM X X X X X ADDR A10 /AP BA Note 2 2 Op Code Op Code X X Row Address Column L H L H H L X X X X X X V V V V V X V X X X X X X X V Column Column Column X X L L H L H L H L H L L L X H X H X H X V X L L X H X H X H X V H H X H X H X H X V X X X 1 H L X X L H X X H L H L L H L H X X X X X X L H X H L X X Rev 1.5 / Jan. 2009 17 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series CURRENT STATE TRUTH TABLE (Sheet 1 of 4) Command Current State CS RAS CAS WE L L L L Idle L L L H L L L L Row Active L L L H L L L Read L L L L L L L L H H H X L L L L H H H X L L L L H H H L L H H L L H X L L H H L L H X L L H H L L H L H L H L H H X L H L H L H H X L H L H L H H X BA BA BA BA X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 Amax-A0 OP CODE X X Row Add. Col. Add. A10 Col. Add. A10 X X OP CODE X X Row Add. Col. Add. A10 Col. Add. A10 X X OP CODE X X Row Add. Col. Add. A10 Col. Add. A10 X Action Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Set the Mode Register Start Auto or Self Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write: optional AP(A10=H) Start Read: optional AP(A10=H) No Operation No Operation ILLEGAL ILLEGAL Termination Burst: Start the Precharge ILLEGAL Termination Burst: Start Write(optional AP) Termination Burst: Start Read(optional AP) Continue the Burst 4 8,9 8 13,14 13 4 4 3 3 13,14 13 7 4 6 6 14 5 Notes Rev 1.5 / Jan. 2009 18 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series CURRENT STATE TRUTH TABLE (Sheet 2 of 4) Command Current State Read CS RAS CAS WE H L L L L Write L L L H L L L Read with Auto Precharge L L L L H L L L Write with Auto Precharge L L L L H H H H X L L L L H H H X L L L L H H H X L L H X L L H H L L H X L L H H L L H X L H H X L H L H L H H X L H L H L H H X X BA BA BA BA X X X BA BA BA BA X X BA BA X X X L L L L X L L H H X L H L H X BA BA BA0/ BA1 X Amax-A0 X OP CODE X X Row Add. Col. Add. A10 Col. Add. A10 X X OP CODE X X Row Add. Col. Add. A10 Col. Add. A10 X X OP CODE X X Row Add. Col. Add. A10 Col. Add. A10 X X Action Description Device Deselect Mode Register Set Continue the Burst ILLEGAL 13,14 13 10 4 8 8,9 Notes Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Termination Burst: Start the Precharge ILLEGAL Termination Burst: Start Write(optional AP) Termination Burst: Start Read(optional AP) Continue the Burst Continue the Burst ILLEGAL 13,14 13 4,12 4,12 12 12 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL 13,14 13 4,12 4,12 12 12 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst Rev 1.5 / Jan. 2009 19 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series CURRENT STATE TRUTH TABLE (Sheet 3 of 4) Command Current State CS RAS CAS WE L L L L Precharging L L L H L L L L Row Activating L L L H L L L L Write Recovering L L L L L L L H H H X L L L L H H H X L L L L H H H L L H H L L H X L L H H L L H X L L H H L L H L H L H L H H X L H L H L H H X L H L H L H H X BA BA BA BA X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 Amax-A0 OP CODE X X Row Add. Col. Add. A10 Col. Add. A10 X X OP CODE X X Row Add. Col. Add. A10 Col. Add. A10 X X OP CODE X X Row Add. Col. Add. A10 Col. Add. A10 X Action Description Mode Register Set ILLEGAL 13,14 13 Notes Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set No Operation: Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation: Bank(s) idle after tRP No Operation: Bank(s) idle after tRP ILLEGAL 4,12 4,12 4,12 13,14 13 4,12 4,11,1 2 4,12 4,12 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: Row Active after tRCD No Operation: Row Active after tRCD ILLEGAL 13,14 13 4,13 4,12 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation ILLEGAL ILLEGAL Start Write: Optional AP(A10=H) Start Read: Optional AP(A10=H) No Operation: Row Active after tDPL 9 Rev 1.5 / Jan. 2009 20 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series CURRENT STATE TRUTH TABLE (Sheet 4 of 4) Command Current State Write Recovering CS RAS CAS WE H L L L Write Recovering with Auto Precharge L L L L H L L L L Refreshing L L L H L L L L Mode Register Accessing L L L H X L L L L H H H X L L L L H H H X L L L L H H H X X L L H H L L H X L L H H L L H X L L H H L L H X X L H L H L H H X L H L H L H H X L H L H L H H X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 X Amax-A0 X OP CODE X X Row Add. Col. Add. A10 Col. Add. A10 X X OP CODE X X Row Add. Col. Add. A10 Col. Add. A10 X X OP CODE X X Row Add. Col. Add. A10 Col. Add. A10 X X Action Description Device Deselect Mode Register Set No Operation: Row Active after tDPL ILLEGAL 13,14 13 4,13 4,12 4,12 4,9,12 Notes Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: Precharge after tDPL No Operation: Precharge after tDPL ILLEGAL 13,14 13 13 13 13 13 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: idle after tRC No Operation: idle after tRC ILLEGAL 13,14 13 13 13 13 13 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: idle after 2 clock cycles No Operation: idle after 2 clock cycles Rev 1.5 / Jan. 2009 21 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series Notes: 1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge. 2. All entries assume that CKE was active during the preceding clock cycle. 3. If both banks are idle and CKE is inactive, then in power down cycle 4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address, depending on the state of that bank. 5. If both banks are idle and CKE is inactive, then Self Refresh mode. 6. Illegal if tRCD is not satisfied. 7. Illegal if tRAS is not satisfied. 8. Must satisfy burst interrupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. Must mask preceding data which don't satisfy tDPL. 11. Illegal if tRRD is not satisfied 12. Illegal for single bank, but legal for other banks in multi-bank devices. 13. Illegal for all banks. 14. Mode Register Set and Extended Mode Register Set is same command truth table except BA1. Rev 1.5 / Jan. 2009 22 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series CKE Enable(CKE) Truth TABLE (Sheet 2 of 1) CKE Current State Previous Cycle H L Current Cycle X H Command BA0, Amax -A0 BA1 X X X X INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down mode exit, all banks idle 1 Action Notes CS RAS CAS WE X H X X X X X X 1 2 L Self Refresh L L L L H H H H H L X L L L L X X H H H H L X X X H L H H L X X X X H X L X X X X H L X X X X X H X X L X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 2 2 2 2 L Power Down L H L 2 H L X X ILLEGAL 2 L H Deep Power Down L L X H X X X X X X Maintain Power Down Mode INVALID Deep Power Down mode exit Maintain Deep Power Down Mode 1 5 L L X X X X X X Rev 1.5 / Jan. 2009 23 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series CKE Enable(CKE) Truth TABLE (Sheet 2 of 2) Current State CKE Previous Current Cycle Cycle H H H H All Banks Idle H H H H H H L H Any State other than listed above H H H H H L L L L L X H CS H L L L L H L L L L X X RAS X H L L L X H L L L X X Command CAS X X H L L X X H L L X X WE X X X H L X X X H L X X X X X X BA0, AmaxBA1 A0 Action Notes 3 3 3 Refer to the idle State section of the Current State Truth Table Auto Refresh Mode Register Set Refer to the idle State section of the Current State Truth Table Entry Self Refresh Mode Register Set Power Down Refer to operations of the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend OP CODE 4 3 3 3 4 OP CODE X X X X 4 H L L L H L X X X X X X X X X X X X X X X X X X Notes: 1. For the given current state CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high. 3. The address inputs depend on the command that is issued. 4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state. 5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high and is maintained for a minimum 200usec. Rev 1.5 / Jan. 2009 24 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series Mobile SDR SDRAM OPERATION State Diagram Power On ACT : Active DPDSX Precharge All Bank FA RE Auto Refresh DPDS : Enter Deep Power-Down DPDSX : Exit Deep PowerDownEMRS EMRS : Ext. Mode Reg. Set MRS : Mode Register Set PRE : Precharge (EXTENDED) Mode Register Set (E)MRS REFS IDLE REFX E CK igh H DS DP Self Refresh DEEP POWER DOWN READA SUSPEND E CK igh H E CK w Lo Power Down PREALL : Precharge All Banks REFA : Auto Refresh REFS : Enter Self Refresh REFSX : Exit Self Refresh READ : Read w/o Auto Precharge Active Power Down ow CK EH C Lo K E w WRITEA SUSPEND C Hi KE gh ACT CK EL Read Read W RI T EA C Lo K E w E CK w Lo READ SUSPEND E PR Rev 1.5 / Jan. 2009 E CK w Lo READ with AP A AD RE WRITE with AP igh Write READ ROW ACTIVE Write WRITE E CK igh H READA : Read with Auto Precharge WRITE : Write w/o Auto Precharge WRITEA : Write with Auto Precharge C H i KE gh WRITE SUSPEND PR E PRE Automatic Sequence Manual input Precharge All 25 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series DESELECT The DESELECT function (CS = High) prevents new commands from being executed by the Mobile SDRAM, the Mobile SDRAM ignore command input at the clock. However, the internal status is held. The Mobile SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION The NO OPERATION (NOP) command is used to perform a NOP to a Mobile SDRAM that is selected (CS = Low, RAS = CAS = WE = High). This command is not an execution command. However, the internal operations continue. This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. (see to next figure) ACTIVE The Active command is used to activate a row in particular bank for a subsequent Read or Write access. The value of the BA0,BA1 inputs selects the bank, and the address provided on A0-A13(only for the 1KBytes page size. For the 2KBytes page size, A0~A12 are provided) selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. (see to next figure) CLK CKE High CLK CKE High CS CS RAS RAS CAS CAS WE WE A0~A13 BA0,1 A0~A13 Row Address RA BA0,1 Bank Address Don't Care BA Don't Care NOP command ACTIVATING A SPECIFIC ROW IN A SPECIFIC BANK (A13 is used as 1KBytes reduced page) Rev 1.5 / Jan. 2009 26 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series READ / WRITE COMMAND Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACT) command. An interval of tRCD is required between the bank active command input and the following read/write command input. The READ command is used to initiate a Burst Read to an active row. The value of BA0 and BA1 selects the bank and address inputs select the starting column location. The value of A10 determines whether or not auto precharge is used. If auto-precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent access. The valid data-out elements will be available CAS latency after the READ command is issued. The WRITE command is used to initiate a Burst Write access to an active row. The value of BA0, BA1 selects the bank and address inputs select the starting column location. The value of A10 determines whether or not auto precharge is used. If auto-precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent access. When READ or WRITE command issues, the A0~A7 (column address) are provided if only 1KBytes page size. If the page size is 2KBytes, the A0~A8 (column address) are provided as shown below figure. CLK CKE H ig h CLK CKE H ig h CS CS RAS RAS CAS CAS WE WE A0 ~ A8 CA A0 ~ A8 H ig h to E n a b le A u to P re c h a rg e A10 L o w to D is a b le A u to P re c h a r g e B A 0 ,1 CA A10 B A 0 ,1 BA BA R ead Com m and O p e ra tio n D o n 't C a re W r ite C o m m a n d O p e ra tio n READ / WRITE COMMAND (A13 is used as 1KBytes reduced page) Rev 1.5 / Jan. 2009 27 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series READ A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1) cycle after read command set. The SDRAM can perform a burst read operation. The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address and the bank select address at the read command set cycle. In a read operation, data output starts after the number of clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3. When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the successive burst-length data has been output. The /CAS latency and burst length must be specified at the mode register. tCK CLK Command REA D NOP tLZ NOP tOH Do0 tAC Do1 Do2 Do3 DQ CL = 2 REA D Command NOP NOP tLZ NOP tOH Do0 tAC Do1 Do2 Do3 DQ CL = 3 Undefined Don't Care Read Burst Showing CAS Latency Rev 1.5 / Jan. 2009 28 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series READ to READ Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the new burst follows either the last element of a completed burst or the last desired element of a longer burst that is being truncated. When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. CLK Command READ NOP READ ’ NOP Address BA, Col BA, Col a CL =2 b DQ CL =3 DQ Do a0 Do a1 Do b0 Do b1 Do a0 Do a1 Don't Care Do b0 Consecutive Read Bursts A READ command can be initiated on any clock cycle following a previous READ command. Non-consecutive Reads are shown in Figure. Full-speed random read accesses within a page or pages can be performed as shown in Fig. Rev 1.5 / Jan. 2009 29 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series CLK Command READ READ Address BA, Col BA, Col n CL =2 b DQ CL =3 Don Dob DQ Don Dob Don't Care 1) Don (or b): Data out from column n 2) BA, Col n (b) = Bank A, Column n (b) 3) Burst Length = 4 : 3 subseqnent elements of Data Out appear in the programmed order following Do n (b) Non-Consecutive Read Bursts CLK Command READ READ READ READ Address BA, Col BA, Col BA, Col BA, Col n CL =2 x b g DQ CL =3 DQ Don Don' Dox Dox' Dob Dob' Dog Dog' Don Don' Dox Dox' Dob Dob' Dog Dog’ 1) Don, etc: Data out from column n, etc n', x', etc : Data Out elements, accoding to the programmd burst order 2) BA, Col n = Bank A, Column n 3) Burst Length = 1, 2, 4, 8 or full page in cases shown 4) Read are to active row in any banks Don't Care Random Read Bursts Rev 1.5 / Jan. 2009 30 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series READ BURST TERMINATE Data from any READ burst may be truncated with a BURST TERMINATE command. The BURST TERMINATE latency is equal to the read (CAS) latency, i.e., the BURST TERMINATE command should be issued X cycles after the READ command where X equals the desired data-out element. CLK Com m and READ BURST Address BA, Col n CL =2 DQ CL =3 DQ Do n Do n' Do n Do n' Don't Care 1) Do n : D ata out from column n 2) BA, Col n = B ank A, Column n 3) Cases shown are bursts of 4, 8, or full page terminated after 2 data elem ents Terminating a Read Burst Rev 1.5 / Jan. 2009 31 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series READ to WRITE Data from READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in next fig. CLK Com m and READ BURST W RITE Address BA, Col BA, Col n CL = 2 b DQ CL = 3 DQ Do n Do n' D I b0 D I b1 D I b2 DI b3 D on D o n' D I b0 D I b1 D I b2 D I b3 1) D O n = D ata Out from colum n n; DI b = D ata In to colum n b D on't Care Read to Write Notes: 1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. However, DQM must be set High so that the output buffer becomes High-Z before data input. 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank active state. However, DQM must be set High so that the output buffer becomes High-Z before data input. Rev 1.5 / Jan. 2009 32 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series READ to PRECHARGE Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. CLK Com m and R EAD PRE tRP Address BA, Col ACT n CL = 2 Bank A, All BA, Row DQ CL = 3 DQ D on Don D on't Care 1) D O n = D ata O ut from colum n n 2) Note that Precharge m ay not be issued before tRAS ns after the ACTIVE com m and for applicable banks. 3) The ACT IVE com m and m ay be applied if tRC has been m et. READ to PRECHARGE Rev 1.5 / Jan. 2009 33 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series Write Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered Low, the corresponding data will be written to the memory; if the DM signal is registered High, the corresponding data inputs will be ignored, and a write will not be executed to that byte / column location. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQ will remain High-Z and any additional input data will be ignored. A full-page burst will continue until terminated. Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. CLK Command WRITE Address BA, Col b DQ DQ DQ DQ D Ib0 D Ib0 D Ib0 D Ib0 D Ib1 D Ib1 D Ib1 D Ib2 D Ib2 D Ib3 D Ib3 D Ib4 D Ib5 D Ib6 D Ib7 BL = 1 BL = 2 BL = 4 BL = 8 CL = 2 or 3 Basic Write timing parameters for Don't Care Write Burst Operation Notes: 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 clock. In the case of burst writes, the second write command has priority. 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. In the case of burst write, the second write command has priority. Rev 1.5 / Jan. 2009 34 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series WRITE to WRITE Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data, can be maintained. The new WRITE command can be issued on any positive edge of the clock following the previous WRITE command. The first data-in element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new WRITE command should be issued X cycles after the first WRITE command, where X equals the number of desired data-in element. CLK Command WRITE WRITE Address DQ BA, Col BA, Col b D Ib0 D Ib1 D Ib2 D Ib3 n D In0 D In1 D In2 D In3 DM CL = 2 or 3 Don't Care Concatenated Write Bursts CLK Com m and W RITE W RITE W RITE W RITE W RITE N OP Address BA, Col BA, Col BA, Col BA, Col BA, Col b D Ib D I b' x D Ix D Ix ’ n D In D In ’ a D Ia D Ia ’ g D Ig D Ig ’ DQ DM CL = 2 or 3 D on't Care Random Write Cycles Rev 1.5 / Jan. 2009 35 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series WRITE to READ CLK Command WRITE READ Address BA, Col BA, Col b DIb0 DIb1 n DO n0 DO n1 DOn2 DOn3 CL = 2 BL = 4 DQ DQ DIb0 DIb1 DOn0 DOn1 D On2 DOn3 CL = 3 BL = 4 Don't Care The preceding burst write operation can be aborted and a new burst read operation can be started by inputting a new read command in the write cycle. The data of the read command (READ) is output after the lapse of the /CAS latency. The preceding write operation (WRIT) writes only the data input before the read command. The data bus must go into a high-impedance state at least one cycle before output of the latest data. Notes: 1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed. 2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address). Rev 1.5 / Jan. 2009 36 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series WRITE to PRECHARGE Data for any WRITE burst may be followed by a subsequent PRECHARGE command to the same bank (provided Auto Precharge was not activated). When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data must be masked by means of DQM for assurance of the clock defined by tDPL. To follow a WRITE without truncating the WRITE burst, tDPL should be met as shown in Fig. CLK Command WRITE PRE Address BA, Col b D Ib0 D Ib3 tDPL CL = 2 or 3 BL = 4 DQ D Ib1 D IO b2 Non-Interrupting Write to Precharge Data for any WRITE burst may be truncated by a subsequent PRECHARGE command as shown in Figure. Note that only data-in that are registered prior to the tDPL period are written to the internal array, and any subsequent data-in should be masked with DM, as shown in next Fig. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. CLK Command WRITE PRE Address BA, Col b DIb0 DIb1 DIOb2 tDPL CL = 2 or 3 BL = 4 DQ Interrupting Write to Precharge Rev 1.5 / Jan. 2009 37 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series WRITE BURST TERMINATE WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. CLK Command WRITE BST Address BA, Col b DIb0 DIb1 DIOb2 High-Z BL = 4 or higher CL = 2 or 3 DQ Don’t care - Data ignored Terminating a Burst Write command with BST Rev 1.5 / Jan. 2009 38 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series BURST TERMINATE The BURST TERMINATE command is used to truncate read bursts or write bursts (with auto precharge disabled). The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this datasheet. The BURST TERMINATE command is not bank specific. The below figure shows in case of 1KByte page size. If the page size is 2KByte, A0~A12 are provided. CLK CKE High CS RAS CAS WE A0~A13 Don't Care BA0, 1 BURST TERMINATE COMMAND (A13 is used as 1KBytes reduced page) Rev 1.5 / Jan. 2009 39 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. Another command to the same bank (or banks) being precharged must not be issued until the precharge time (tRP) is completed. If one bank is to be precharged, the particular bank address needs to be specified. If all banks are to be precharged, A10 should be set high along with the PRECHARGE command. If A10 is high, BA0 and BA1 are ignored. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging. The below figure shows in case of 1KByte page size. If the page size is 2KByte, A0~A12 are provided. CKE High A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = High when read or write command, autoprecharge function is enabled. While A10 = Low, autoprecharge function is disabled. Don't Care CS RAS CAS WE A0~A9 A11~A13 A10 BA0,1 Bank Address BA PRECHARGE command (A13 is used as 1KBytes reduced page) AUTO PRECHARGE Auto Precharge is a feature which performs the same individual bank precharge function as described above, but without requiring an explicit command. This is accomplished by using A10 (A10=high), to enable auto precharge in conjunction with a specific Read or Write command. This precharges the bank/row after the Read or Write burst is complete. Auto precharge is non persistent, so it should be enabled with a Read or Write command each time auto precharge is desired. Auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. Rev 1.5 / Jan. 2009 40 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series AUTO REFRESH AND SELF REFRESH Mobile SDRAM devices require a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of two ways: by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode: - AUTO REFRESH. This command is used during normal operation of the Mobile SDRAM. It is non persistent, so must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller.The Mobile SDRAM requires AUTO REFRESH commands at an average periodic interval of tREF. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given Mobile SDRMA, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8*tREF. -SELF REFRESH. This state retains data in the Mobile SDRAM, even if the rest of the system is powered down. Note refresh interval timing while in Self Refresh mode is scheduled internally in the Mobile SDRAM and may vary and may not meet tREF time. After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self refresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within tREF (max.) period on the condition 1 and 2 below. 1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. 2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below* after exiting from self-refresh mode. Note: tREF (max.) / refresh cycles. The use of SELF REFRESH mode introduces the possibility that an internally timed event can be missed when CKE is raised for exit from self refresh mode. Upon exit from SELF REFRESH an extra AUTO REFRESH command is recommended. In the self refresh mode, two additional power-saving options exist. They are Temperature Compensated Self Refresh and Partial Array Self Refresh and are described in the Extended Mode Register section. The Self Refresh command is used to retain cell data in the Mobile SDRAM. In the Self Refresh mode, the Mobile SDRAM operates refresh cycle asynchronously. The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled(Low). The Mobile SDRAM can accomplish an special Self Refresh operation by the specific modes(PASR) programmed in extended mode registers. The Mobile SDRAM can control the refresh rate automatically by the temperature value of Auto TCSR(Temperature Compensated Self Refresh) to reduce self refresh current and select the memory array to be refreshed by the value of PASR(Partial Array Self Refresh). The Mobile SDRAM can reduce the self refresh current(IDD6) by using these two modes. The figure of next page shows in case of 1KByte page size. If the page size is 2KByte, A0~A12 are provided. Rev 1.5 / Jan. 2009 41 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series CLK CKE High CLK CKE CS CS RAS RAS CAS CAS WE WE A0~A13 Don't Care A0~A13 Don't Care BA0, 1 BA0, 1 AUTO REFRESH COMMAND SELF REFRESH ENTRY COMMAND (A13 is used as 1KBytes reduced page) Note 1: If all banks are in the idle status and CKE is inactive (low level), the self refresh mode is set. Function CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10/AP BA Auto Refresh Self Refresh Entry H H H L L L L L L L H H X X X X Rev 1.5 / Jan. 2009 42 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series MODE REGISTER SET The mode registers are loaded via the address bits. BA0 and BA1 are used to select between the Mode Register and the Extended Mode Register. See the Mode Register description in the register definition section. The MODE REGISTER SET command can only be issued when all banks are idle and no bursts are in progress, and a subsequent executable command cannot be issued until tMRD is met. The below figure shows in case of 1KByte page size. If the page size is 2KByte, A0~A12 are provided. (A13 is used as 1KBytes reduced page) CLK CKE H ig h CS RA S CA S WE A0~ A13 C ode C ode MODE REGISTER SET COMMAND D on 't C are BA 0, 1 Note: BA0=BA1=Low loads the Mode Register, whereas BA0=Low and BA1=High loads the Extended Mode Register. CLK Command MRS NOP tMRD Valid Address Code Valid Don't Care Code = Mode Register / Extended Mode Register selection (BA0, BA1) and op-code (A0 - An) tMRD DEFINITION Rev 1.5 / Jan. 2009 43 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series POWER DOWN Power down occurs if CKE is set low coincident with Device Deselect or NOP command and when no accesses are in progress. If power down occurs when all banks are idle, it is Precharge Power Down. If Power down occurs when one or more banks are Active, it is referred to as Active power down. The device cannot stay in this mode for longer than the refresh requirements of the device, without losing data. The power down state is exited by setting CKE high while issuing a Device Deselect or NOP command. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. DEEP POWER-DOWN The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside the Mobile SDRAM are stopped and all memory data is lost in this mode. All the information in the Mode Register and the Extended Mode Register is lost. Next Figure, DEEP POWER-DOWN COMMAND shows the DEEP POWER-DOWN command All banks must be in idle state with no activity on the data bus prior to entering the DPD mode. While in this state, CKE must be held in a constant low state. To exit the DPD mode, CKE is taken high after the clock is stable and NOP command must be maintained for at least 200 us. After 200 us a complete re-initialization routing is required defined for the initialization sequence. The below figure shows in case of 1KByte page size. If the page size is 2KByte, A0~A12 are provided. CLK CKE CLK CKE CS RAS CS RAS CAS CAS WE WE A0~A13 A0~A13 BA0, 1 Don't Care BA0, 1 Don't Care POWER-DOWN COMMAND DEEP POWER-DOWN COMMAND (A13 is used as 1KBytes reduced page) Rev 1.5 / Jan. 2009 44 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series CLK CKE COMMAND All banks idle NOP NOP ACTIVE tRCD Input buffers gated off Enter power-down mode. Exit power-down mode. tRAS tRC DON’T CARE CLK CKE tCKS COMMAND PCG NOP NOP Input buffers gated off Pre-charge all Deep Power down entry tCKS NOP 200us(min) APCG Deep Power down Exit DON’T CARE Rev 1.5 / Jan. 2009 45 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series CLK tCKS tCKS tCKS tCKS CKE Power down Exit Time CS RAS CAS WE Ra VDDR Ca BA0, BA1 Ra Hi-Z AP DQ DQM Qa0 Qa1 Qa2 Row Active Precharge Power down Entry Precharge Power down Exit Active Power down Entry Read Active Power down Exit Precharge Don’t care Note : CKE should be set high at least 1CLK + tCKS prior to Row active command. Rev 1.5 / Jan. 2009 46 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series tCK CLK tCH tCL tCKS tCKH tCKS tRAS(MIN) CKE tCMS tCMH NOP AUTO REFRESH NOP or COMMAND INHIBIT Any COM COMMAND PRECHARGE DQM A0A9,Amax ALL BANKS A10 SINGLE BANK tAS tAH BA0, BA1 BANKS DQ High-Z Precharge all active banks tRP Enter self refresh mode tXSR Exit self refresh mode (Restart refresh time base) DON’T CARE Rev 1.5 / Jan. 2009 47 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series Power-up and Initialization Like a Synchronous DRAM, Low Power SDRAM(Mobile SDRAM) must be powered up and initialized in a predefined manner. Power must be applied to VDD and VDDQ(simultaneously). The clock signal must be started at the same time. After power up, an initial pause of 200 usec is required. And a precharge all command will be issued to the Mobile SDRAM. Then, 8 or more Auto refresh cycles will be provided. After the Auto refresh cycles are completed, a mode register set(MRS) command will be issued to program the specific mode of operation (Cas Latency, Burst length, etc.) And a extended mode register set command will be issued to program specific mode of self refresh operation(PASR). The following these cycles, the Mobile SDRAM is ready for normal operation. Programming the registers Mode Register The mode register contains the specific mode of operation of the Mobile SDRAM. This register includes the selection of a burst length(1, 2, 4, 8, Full Page), a cas latency(2 or 3), a burst type. The mode register set must be done before any activate command after the power up sequence. Any contents of the mode register be altered by re-programming the mode register through the execution of mode register set command. Extended Mode Register The extended mode register contains the specific features of self refresh operation of the Mobile SDRAM. This register includes the selection of partial arrays to be refreshed(half array, quarter array, etc.). The extended mode register set must be done before any activate command after the power up sequence. Any contents of the mode register be altered by re-programming the mode register through the execution of extended mode register set command. Bank(Row) Active The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by activating CS, RAS and deasserting CAS, WE at the positive edge of the clock. The value on the BA1 and BA0 selects the bank, and the value on the A0-A13(or A12 which depends on page size) selects the row. This row remains active for column access until a precharge command is issued to that bank. Read and write operations can only be initiated on this activated bank after the minimum tRCD time is passed from the activate command. Read The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and deasserting WE, RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses. The length of burst and the CAS latency will be determined by the values programmed during the MRS command. Write The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE and deasserting RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses. Rev 1.5 / Jan. 2009 48 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series Precharge The Precharge command is used to close the open row in a particular bank or the open row in all banks. When the precharge command is issued with address A10, high, then all banks will be precharged, and If A10 is low, the open row in a particular bank will be precharged. The bank(s) will be available when the minimum tRP time is met after the precharge command is issued. Auto Precharge The Auto Precharge command is issued to close the open row in a particular bank after READ or WRITE operation. If A10 is high when a READ or WRITE command is issued, the READ or WRITE with Auto Precharge is initiated. Burst Termination The Burst Termination is used to terminate the burst operation. This function can be accomplished by asserting a Burst Stop command or a Precharge command during a burst READ or WRITE operation. The Precharge command interrupts a burst cycle and close the active bank, and the Burst Stop command terminates the existing burst operation leave the bank open. Data Mask The Data Mask command is used to mask READ or WRITE data. During a READ operation, When this command is issued, data outputs are disabled and become high impedance after two clock delay. During a WRITE operation, When this command is issued, data inputs can't be written with no clock delay. If data mask is initiated by asserting low on DQM during the read cycle, the data outputs are enabled. If DQM is asserted to High. the data outputs are masked (disabled) and become Hi-Z state after 2 cycle later. During the write cycle, DQM mask data input with zero latency CK CM D W RIT DM Data M asking H i- Z D ata M asking 0 Latency D 0D IN0 D 1 D0 MK D1 D 0D IN2 D 1 0 Latency D0 MK D1 DQ W rite D ata M asking CK CMD READ DM D a ta M asking H i- Z 2 Laten cy D0 OUT0 1 D D D 0 O U T1 1 D D D0 DOT2 1 D D D0 MK D1 DQ R ead D ata M askin g Rev 1.5 / Jan. 2009 49 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series Clock Suspend The Clock Suspend command is used to suspend the internal clock of Mobile SDRAM. The clock suspend operation stops transmission of the clock to the internal circuits of the device during burst transfer of data to stop the operation of the device. During normal access mode, CKE is keeping High. When CKE is low, it freezes the internal clock and extends data Read and Write operations. (See examples in next Figures) CLK Command CKE Internal CLK Frozen Int. CLK by CKE (CKE = Fixed Low) RD Masked by CKE DQ Q1 Q2 Clock Suspend Mode Q3 Q4 Command CKE WR Masked by CKE Internal CLK Frozen Int. CLK by CKE (CKE = Fixed Low) DQ D1 D2 D3 Clock Suspend Mode D4 Rev 1.5 / Jan. 2009 50 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series Power Down The Power Down command is used to reduce stand-by current. Before this command is issued, all banks must be precharged and tRP must be passed after a precharge command. Once the Power Down command is initiated by keeping CKE low, all of the input buffer except CKE are gated off. Auto Refresh The Auto Refresh command is used during normal operation and is similar to CBR refresh in Conventional DRAMs. This command must be issued each time a refresh is required. When an Auto Refresh command is issued, the address bits is ''Don't care'', because the specific address bits is generated by internal refresh address counter. Self Refresh The Self Refresh command is used to retain cell data in the Mobile SDRAM. In the Self Refresh mode, the Mobile SDRAM operates refresh cycle asynchronously. The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled(Low). The Mobile SDRAM can accomplish an special Self Refresh operation by the specific modes(PASR) programmed in extended mode registers. The Mobile SDRAM can control the refresh rate automatically by the temperature value of Auto TCSR(Temperature Compensated Self Refresh) to reduce self refresh current and select the memory array to be refreshed by the value of PASR(Partial Array Self Refresh). The Mobile SDRAM can reduce the self refresh current(IDD6) by using these two modes. Deep Power Down The Deep Power Down Mode is used to achieve maximum power reduction by cutting the power of the whole memory array of the devices. For more information, see the special operation for Low Power consumption of this data sheet. Rev 1.5 / Jan. 2009 51 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series Special Operation for Low Power Consumption Deep Power Down Mode Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory array of the devices. Data will not be retained once the device enters Deep Power Down Mode. Full initialization is required when the device exits from Deep Power Down Mode. Truth Table Current State Command CKEn-1 CKEn CS RAS CAS WE Idle Deep Power Down Deep Power Down Entry Deep Power Down Exit H L L H L X H X H X L X Deep Power Down Mode Entry The Deep Power Down Mode is entered by having CS and WE held low with RAS and CAS high at the rising edge of the clock, while CKE is low. The following diagram illustrates deep power down mode entry. CKE CS RAS CAS WE tRP Pre-charge if needed Rev 1.5 / Jan. 2009 Deep Power Down Entry 52 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series Deep Power Down Mode (Continued) Deep Power Down Mode Exit Sequence The Deep Power Down mode is exited by asserting CKE high. After the exit, the following sequence is needed to enter a new command. 1. Maintain NOP input conditions for a minimum of 200usec 2. Issue precharge commands for all banks of the device 3. Issue 8 or more auto refresh commands 4. Issue a mode register set command to initialize the mode register 5. Issue an extended mode register set command to initialize the extended mode register The following timing diagram illustrates deep power down mode exit sequence. CLK CKE CS RAS CAS WE 200us tRP tRC Deep Power Down Exit All Banks Precharge Auto Refresh Auto Refresh Mode Register Set Extended Mode Register Set New Command Accepted Here Rev 1.5 / Jan. 2009 53 11 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122DFR Series / H55S5132DFR Series PACKAGE INFORMATION 90 Ball FBGA 0.8mm pitch (8.0mm x 13.0mm) A1 INDEX MARK 8.00 Typ. 0.8Typ. 0.8 Unit [mm] 0.90. 0.80 Typ. 13.0 Typ. 11.2 Typ. Bottom View 0.45 +/- 0.05 0.35 +/- 0.05 0.90 0.8 6.40 Typ. 1.00 max Rev 1.5 / Jan. 2009 54