H57V2562GTR-50L

256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O 256M (16Mx16bit) Hynix SDRAM Memory Memory Cell Array - Organized as 4banks of 4,194,304 x 16 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Aug. 2009 1 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series H57V2562GTR Document Title 256Mbit (16M x16) Synchronous DRAM Revision History Revision No. 0.1 1.0 History Preliminary Release Draft Date Jun. 2009 Aug. 2009 Remark Rev 1.0 / Aug. 2009 2 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series DESCRIPTION The Hynix H57V2562GTR Synchronous DRAM is 268,435,456bit CMOS Synchronous DRAM, ideally suited for the consumer memory applications which requires large memory density and high bandwidth. It is organized as 4banks of 4,194,304 x 16 I/O. Synchronous DRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Synchronous DRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16 Input/ Output bus. All the commands are latched in synchronization with the rising edge of CLK. The Synchronous DRAM provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8 locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The Synchronous DRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compartible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randon-access operation. Read and write accesses to the Hynix Synchronous DRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. All inputs are LVTTL compatible. Devices will have a VDD and VDDQ supply of 3.3V (nominal). Rev 1.0 / Aug. 2009 3 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series 256Mb Synchronous DRAM(16M x 16) FEATURES ● ● ● ● ● ● ● ● Standard SDRAM Protocol Internal 4bank operation Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V All device pins are compatible with LVTTL interface Low Voltage interface to reduce I/O power 8,192 Refresh cycles / 64ms Programmable CAS latency of 2 or 3 Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst Commercial Temp : 0oC ~ 70oC Operation Package Type : 54_Pin TSOPII This product is in compliance with the directive pertaining of RoHS. ● ● ● ORDERING INFORMATION Part Number H57V2562GTR-60C H57V2562GTR-75C H57V2562GTR-50C H57V2562GTR-60L H57V2562GTR-75L H57V2562GTR-50L Clock Frequency 166MHz 133MHz 200MHz 166MHz 133MHz 200MHz CAS Latency 3 3 3 3 3 3 Low Power Normal 3.3V 4Banks x 4Mbits x16 LVTTL Power Voltage Organization Interface Note: 1. H57V2562GTR-XXC Series: Normal power & Commercial temp. 2. H57V2562GTR-XXL Series: Low Power & Commercial temp. Rev 1.0 / Aug. 2009 4 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series 54 TSOP II Pin ASSIGNMENTS VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS 54 Pin TSOPII 400mil x 875mil 0.8mm pin pitch 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Rev 1.0 / Aug. 2009 5 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series 54_TSOPII Pin DESCRIPTIONS SYMBOL CLK TYPE INPUT DESCRIPTION Clock : The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Clock Enable: Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Chip Select: Enables or disables all inputs except CLK, CKE and DQM Bank Address: Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address: RA0 ~ RA12, Column Address: CA0 ~ CA8 Auto-precharge flag: A10 Command Inputs: RAS, CAS and WE define the operation Refer function truth table for details Data Mask: Controls output buffers in read mode and masks input data in write mode Data Input / Output: Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection : These pads should be left unconnected CKE INPUT CS INPUT BA0, BA1 INPUT A0 ~ A12 INPUT RAS, CAS, WE INPUT LDQM, UDQM DQ0 ~ DQ15 VDD / VSS VDDQ / VSSQ NC I/O I/O SUPPLY SUPPLY - Rev 1.0 / Aug. 2009 6 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series FUNCTIONAL BLOCK DIAGRAM 4Mbit x 4banks x 16 I/O Synchronous DRAM Self refresh logic & timer Internal Row Counter CLK CKE CS RAS CAS WE LDQM, UDQM State Machine Row Active Row Pre Decoder X Decorders 4M x16 Bank3 4M x16 Bank2 4M x16 Bank1 4M x16 Bank0 X Decorders DQ0 I/O Buffer & Logic Sense AMP & I/O Gate X Decorders X Decoders Refresh Column Active Memory Cell Array Column Pre Decoder Y decoerders DQ15 Bank Select Column Add Counter A0 A1 Address Buffers Address Register Burst Length Burst Counter Pipe Line Control A12 BA1 BA0 Mode Register CAS Latency Data Out Control Rev 1.0 / Aug. 2009 7 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series ABSOLUTE MAXIMUM RATING Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD supply relative to VSS Short Circuit Output Current Power Dissipation Symbol TA TSTG VIN, VOUT VDD, VDDQ IOS PD Rating 0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 Unit o o C C V V mA W Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITION Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VDD, VDDQ VIH VIL Min 3.0 2.0 -0.3 Max 3.6 VDDQ + 0.3 0.8 Unit V V V Note 1 1, 2 1, 3 Note: 1. All voltages are referenced to VSS = 0V. 2. VIH(Max) is acceptable VDDQ + 2V for a pulse width with 1ns, then (tR/2-0.5)ns should be added to the parameter. Rev 1.0 / Aug. 2009 11 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series AC CHARACTERISTICS II Parameter Operation Auto Refresh (AC operating conditions unless otherwise noted) Speed (MHz) tRC tRRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD 2 0 2 3 1 1 64 200 Min 55 55 15 38.7 15 10 1 0 2 Max 100K 166 Min 60 60 18 42 18 12 1 0 2 Max 100K 133 Min 63 63 20 42 20 15 1 0 2 Max 100K Unit ns ns ns ns ns ns CLK CLK CLK Note RAS Cycle Time RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay CAS to CAS Delay Write Command to Data-In Delay Data-in to Precharge Command Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data Output High-Z Power Down Exit Time Self Refresh Exit Time Refresh Time CL = 3 CL = 2 tDPL + tRP 2 0 2 3 1 1 64 2 0 2 3 2 1 1 64 CLK CLK CLK CLK CLK CLK CLK ms 1 tPROZ3 tPROZ2 tDPE tSRE tREF Note: 1. A new command can be given tRC after self refresh exit. Rev 1.0 / Aug. 2009 12 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series BASIC FUNCTIONAL DESCRIPTION Mode Register BA1 0 BA0 0 A12 0 A11 0 A10 0 A9 OP Code A8 0 A7 0 A6 A5 A4 A3 BT A2 A1 A0 CAS Latency Burst Length OP Code A9 0 1 Write Mode Burst Read and Burst Write Burst Read and Single Write Burst Type A3 0 1 Burst Type Sequential Interleave CAS Latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved Burst Length A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length A3 = 0 1 2 4 8 Reserved Reserved Reserved Full page A3=1 1 2 4 8 Reserved Reserved Reserved Reserved Rev 1.0 / Aug. 2009 13 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series COMMAND TRUTH TABLE Function Mode Register Set No Operation Device Deselect Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst stop DQM Auto Refresh Burst-Read Single-Write Self Refresh Entry Self Refresh Exit Precharge Power Down Entry Precharge Power Down Exit Clock Suspend Entry Clock Suspend Exit CKEn-1 H H H H H H H H H H H H H H H L H L H L CKEn X X X X X X X X X X X X H X L H L H L H L L L H L H L H L H L L L L X H X H X H X V X CS L L H L L L L L L L L RAS L H X L H H H H L L H X L L L X H X H X H X V H H H X H X H X H X V CAS L H X H L L L L H H H WE L H X H H H L L L L L X X X X X X V X X X X X X X X DQM X X X X Column Column Column Column X X ADDR A10 /AP X X Row Address L H L H H L X X X A9 Pin High (Other Pins OP code) X X X X X X 1 2 V V V V V X V BA Note Op Code Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high. 2. see to Next page (DQM TRUTH TABLE) Rev 1.0 / Aug. 2009 14 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series DQM TRUTH TABLE Function Data Write/Output enable Data Mask/Output disable Lower byte write/Output enable, Upper byte mask/Output disable Lower byte Mask/Output disable, Upper byte write/Output enable CKEn-1 H H H H CKEn X X X X LDQM L H L H UDQM L H H L Note 1. H: High Level, L: Low Level, X: Don't Care 2. Write DQM Latency is 0 CLK and Read DQM Latency is 2 CLK Rev 1.0 / Aug. 2009 15 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series CURRENT STATE TRUTH TABLE (Sheet 1 of 4) Current State Command CS RAS CAS WE L L L L idle L L L H L L L L Row Active L L L H L L L Read L L L L L L L L H H H X L L L L H H H X L L L L H H H L L H H L L H X L L H H L L H X L L H H L L H L H L H L H H X L H L H L H H X L H L H L H H X BA BA BA BA X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 Amax-A0 OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Action Set the Mode Register Start Auto or Self Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write : optional AP(A10=H) Start Read : optional AP(A10=H) No Operation No Operation ILLEGAL ILLEGAL Termination Burst: Start the Precharge ILLEGAL Termination Burst: Start Write(optional AP) Termination Burst: Start Read(optional AP) Continue the Burst 4 8,9 8 13 13 4 4 3 3 13 13 7 4 6 6 5 Notes Rev 1.0 / Aug. 2009 16 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series CURRENT STATE TRUTH TABLE Current State Read CS RAS CAS WE H L L L L Write L L L H L L L Read with Auto Precharge L L L L H L L Write with Auto Precharge L L L L L H X L L L L H H H X L L L L H H H X L L L L H H H X X L L H H L L H X L L H H L L H X L L H H L L H X X L H L H L H H X L H L H L H H X L H L H L H H X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 X (Sheet 2 of 4) Command Amax-A0 X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X Description Device Deselect Mode Register Set Action Continue the Burst ILLEGAL 13 13 10 4 8 8,9 Notes Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Termination Burst: Start the Precharge ILLEGAL Termination Burst: Start Write(optional AP) Termination Burst: Start Read(optional AP) Continue the Burst Continue the Burst ILLEGAL 13 13 4,12 4,12 12 12 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL 13 13 4,12 4,12 12 12 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst Rev 1.0 / Aug. 2009 17 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series CURRENT STATE TRUTH TABLE Current State CS RAS CAS WE L L L L Precharging L L L H L L L L Row Activating L L L H L L L L Write Recovering L L L L L L L H H H X L L L L H H H X L L L L H H H L L H H L L H X L L H H L L H X L L H H L L H L H L H L H H X L H L H L H H X L H L H L H H X BA BA BA BA X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 (Sheet 3 of 4) Command Amax-A0 OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X Description Mode Register Set ILLEGAL Action Notes 13 13 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set No Operation: Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation: Bank(s) idle after tRP No Operation: Bank(s) idle after tRP ILLEGAL 4,12 4,12 4,12 13 13 4,12 4,11,1 2 4,12 4,12 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: Row Active after tRCD No Operation: Row Active after tRCD ILLEGAL 13 13 4,13 4,12 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation ILLEGAL ILLEGAL Start Write: Optional AP(A10=H) Start Read: Optional AP(A10=H) No Operation: Row Active after tDPL 9 Rev 1.0 / Aug. 2009 18 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series CURRENT STATE TRUTH TABLE Current State Write Recovering CS RAS CAS WE H L L L Write Recovering with Auto Precharge L L L L H L L L L Refreshing L L L H L L L Mode Register Accessing L L L L H X L L L L H H H X L L L L H H H X L L L L H H H X X L L H H L L H X L L H H L L H X L L H H L L H X X L H L H L H H X L H L H L H H X L H L H L H H X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 X (Sheet 4 of 4) Command Amax-A0 X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X Description Device Deselect Mode Register Set Action No Operation: Row Active after tDPL ILLEGAL 13 13 4,13 4,12 4,12 4,9,12 Notes Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: Precharge after tDPL No Operation: Precharge after tDPL ILLEGAL 13 13 13 13 13 13 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: idle after tRC No Operation: idle after tRC ILLEGAL 13 13 13 13 13 13 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: idle after 2 clock cycles No Operation: idle after 2 clock cycles Rev 1.0 / Aug. 2009 19 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series Note : 1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge. 2. All entries assume that CKE was active during the preceding clock cycle. 3. If both banks are idle and CKE is inactive, then in power down cycle 4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address, depending on the state of that bank. 5. If both banks are idle and CKE is inactive, then Self Refresh mode. 6. Illegal if tRCD is not satisfied. 7. Illegal if tRAS is not satisfied. 8. Must satisfy burst interrupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. Must mask preceding data which don't satisfy tDPL. 11. Illegal if tRRD is not satisfied 12. Illegal for single bank, but legal for other banks in multi-bank devices. 13. Illegal for all banks. Rev 1.0 / Aug. 2009 20 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series CKE Enable(CKE) Truth TABLE Current State CKE Previous Current Cycle Cycle H L L L L L L H L Power Down L H L X H H H H H L X H CS X H L L L L X X H L RAS X X H H H L X X X H L X X L H H H H All Banks Idle H H H H H H L L H H H H H L L L L L X X H L L L L H L L L L X X X H L L L X H L L L X (Sheet 2 of 1) Command CAS X X H H L X X X X H X L X X X X H L L X X H L L X WE X X H L X X X X X H X X L X X X X H L X X X H L X X X X X BA0, ADDR BA1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X Maintain Power Down Mode Refer to the idle State section of the Current State Truth Table Auto Refresh Mode Register Set Refer to the idle State section of the Current State Truth Table Entry Self Refresh Mode Register Set Power Down 4 4 3 3 3 4 3 3 3 ILLEGAL 2 INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down mode exit, all banks idle 1 2 Action Notes 1 2 2 2 2 2 Self Refresh OP CODE OP CODE X X Rev 1.0 / Aug. 2009 21 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series CKE Enable(CKE) Truth TABLE Current State CKE Previous Current Cycle Cycle H Any State other than listed above H CS RAS (Sheet 2 of 2) Command CAS WE BA0, ADDR BA1 X X Action Refer to operations of the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend Notes X X X X H L L L H L X X X X X X X X X X X X X X X X X X Note : 1. For the given current state CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high. 3. The address inputs depend on the command that is issued. 4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state. 5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high and is maintained for a minimum 200usec. Rev 1.0 / Aug. 2009 22 111 Synchronous DRAM Memory 256Mbit H57V2562GTR Series PACKAGE INFORMATION e B 54 28 E1 E 27 1 DIE A2 D1 A1 Symbol A A1 A2 B C CP D1 E E1 e L L1 alpha 22.149 11.735 10.058 0.406 millimeters Min 0.991 0.050 0.950 0.300 0.120 Typ 0.100 1.000 0.10 22.22 11.76 10.16 0.8 0.8 22.327 11.938 10.262 0.597 0.8720 0.4620 0.3950 0.0160 Max 1.194 0.150 1.050 0.400 0.210 Min 0.0390 0.0020 0.0374 0.012 0.0047 0.0039 0.0394 0.0039 0.8748 0.4630 0.4 0.0315 0.0315 0.8790 0.4700 0.4040 0.0235 - C L1 CP A αL inches Typ Max 0.0470 0.0059 0.0413 0.016 0.0083 0 / 5 (min / max) Rev 1.0 / Aug. 2009 23