8Gb DDR4 SDRAM
8Gb DDR4 SDRAM
Lead-Free&Halogen-Free
(RoHS Compliant)
H5AN8G4NAFR-xxC
H5AN8G8NAFR-xxC
H5AN8G6NAFR-xxC
* SK hynix reserves the right to change products or specifications without notice.
Rev. 1.2 / Jul.2017
1
Revision History
Revision No.
History
Draft Date
Remark
0.01
Initial Release
Oct. 2015
Priliminary
0.1
Updated JEDEC Specification
Changed Ordering Frequency
Changed Speed Bin : 2666Mbps CL19(VK)
Dec.2015
1.0
Updated 2133Mbps (tCK(min) : 0.938ns->0.937ns)
Updated IDD Specification
Apr.2016
1.1
Updated IDD Specification (2133/2666Mbps)
Jun.2016
1.2
Collected typo
Jun.2017
Rev. 1.2 / Jul.2017
2
Description
The H5AN8G4NAFR-xxC, H5AN8G8NAFR-xxC and H5AN8G6NAFR-xxC are a 8Gb CMOS Double Data Rate
IV (DDR4) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK hynix 8Gb DDR4 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on
the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are
sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched
to achieve very high bandwidth.
Device Features and Ordering Information
FEATURES
• VDD=VDDQ=1.2V +/- 0.06V
• Fully differential clock inputs (CK, CK) operation
• Two Termination States such as RTT_PARK and
RTT_NOM switchable by ODT pin
• Differential Data Strobe (DQS, DQS)
• Asynchronous RESET pin supported
• On chip DLL align DQ, DQS and DQS transition with CK • ZQ calibration supported
transition
• TDQS (Termination Data Strobe) supported (x8 only)
• DM masks write data-in at the both rising and falling
edges of the data strobe
• Write Levelization supported
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
• This product in compliance with the RoHS directive.
• Programmable CAS latency 9, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19 and 20 supported
• Write CRC is supported at all speed grades
• Programmable additive latency 0, CL-1, and CL-2
supported (x4/x8 only)
• TCAR(Temperature Controlled Auto Refresh) mode is
supported
• Programmable CAS Write latency (CWL) = 9, 10, 11,
12, 14, 16, 18
• LP ASR(Low Power Auto Self Refresh) mode is supported
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 16banks
• Average Refresh Cycle (Tcase of 0 oC~ 95 oC)
- 7.8 µs at 0oC ~ 85 oC
- 3.9 µs at 85oC ~ 95 oC
• 8 bit pre-fetch
• Internal Vref DQ level generation is available
• Maximum Power Saving Mode is supported
• Fine Granularity Refresh is supported
• Per DRAM Addressability is supported
• Geardown Mode(1/2 rate, 1/4 rate) is supported
• Programable Preamble for read and write is supported
• Self Refresh Abort is supported
• CA parity (Command/Address Parity) mode is supported
• JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16) • Bank Grouping is applied, and CAS to CAS latency
(tCCD_L, tCCD_S) for the banks in the same or different
• Driver strength selected by MRS
bank group accesses are available
• Dynamic On Die Termination supported
• DBI(Data Bus Inversion) is supported(x8)
Rev. 1.2 / Jul.2017
3
ORDERING INFORMATION
Part No.
Configuration
H5AN8G4NAFR-*xxc
2G x 4
H5AN8G8NAFR-*xxC
1G x 8
H5AN8G6NAFR-*xxC
512M x 16
Package
78ball FBGA
96ball FBGA
* xx means Speed Bin Grade
OPERATING FREQUENCY
MT/s
Grade
tCK
(ns)
CAS
Latency
(tCK)
DDR4-1600
-PB
1.25
11
DDR4-1866
-RD
1.071
DDR4-2133
-TF
DDR4-2400
DDR4-2666
tRCD
(ns)
tRP
(ns)
tRAS
(ns)
tRC
(ns)
CL-tRCD-tRP
13.75
13.75
(13.50)* (13.50)*
35
48.75
(48.50)*
11-11-11
13
13.92
13.92
(13.50)* (13.50)*
34
47.92
(47.50)*
13-13-13
0.937
15
14.06
14.06
(13.50)* (13.50)*
33
47.06
(46.50)*
15-15-15
-UH
0.833
17
14.16
14.16
(13.75)* (13.75)*
32
46.16
(45.75)*
17-17-17
-VK
0.75
19
14.25
14.25
(13.75)* (13.75)*
32
46.25
(45.75)*
19-19-19
*SK hynix DRAM devices support optional downbinning to CL17, CL15, CL13 and CL11. SPD setting is programmed to match.
Rev. 1.2 / Jul.2017
4
Package Ballout/Mechanical Dimension
x4 Package Ball out (Top view): 78ball FBGA Package
1
2
3
4
5
6
7
8
9
A
VDD
VSSQ
NC
DM_n, DBI_n
VSSQ
VSS
A
B
VPP
VDDQ
DQS_c
DQ1
VDDQ
ZQ
B
C
VDDQ
DQ0
DQS_t
VDD
VSS
VDDQ
C
D
VSSQ
NC
DQ2
DQ3
NC
VSSQ
D
E
VSS
VDDQ
NC
NC
VDDQ
VSS
E
F
VDD
NC
ODT
CK_t
CK_c
VDD
F
G
VSS
NC
CKE
CS_n
NC
TEN
G
H
VDD
WE_n
A14
ACT_n
CAS_n
A15
RAS_n
A16
VSS
H
J
VREFCA
BG0
A10
AP
A12
BC_n
BG1
VDD
J
K
VSS
BA0
A4
A3
BA1
VSS
K
L
RESET_n
A6
A0
A1
A5
ALERT_n
L
M
VDD
A8
A2
A9
A7
VPP
M
N
VSS
A11
PAR
NC
A13
VDD
N
1
2
3
7
8
9
Rev. 1.2 / Jul.2017
4
5
6
5
x8 Package Ball out (Top view): 78ball FBGA Package
1
2
3
7
8
9
VDD
VSSQ
TDQS_c
DM_n/DBI_n
TDQS_t
VSSQ
VSS
A
B
VPP
VDDQ
C
VDDQ
DQ0
DQS_c
DQ1
VDDQ
ZQ
B
DQS_t
VDD
VSS
VDDQ
D
VSSQ
DQ4
C
DQ2
DQ3
DQ5
VSSQ
D
E
VSS
VDDQ
F
VDD
NC
DQ6
DQ7
VDDQ
VSS
E
ODT
CK_t
CK_c
VDD
G
VSS
NC
F
CKE
CS_n
NC
TEN
G
H
VDD
WE_n
A14
ACT_n
CAS_n
A15
RAS_n
A16
VSS
H
J
VREFCA
BG0
A10
AP
A12
BC_n
BG1
VDD
J
K
VSS
BA0
A4
A3
BA1
VSS
K
L
RESET_n
A6
A0
A1
A5
ALERT_n
L
M
VDD
A8
A2
A9
A7
VPP
M
N
VSS
A11
PAR
NC
A13
VDD
N
1
2
3
7
8
9
A
Rev. 1.2 / Jul.2017
4
4
5
5
6
6
6
x16 Package Ball out (Top view): 96ball FBGA Package
A
1
2
3
VDDQ
VSSQ
4
5
6
7
8
9
DQU0
DQSU_c
VSSQ
VDDQ
A
B
VPP
VSS
VDD
DQSU_t
DQU1
VDD
B
C
VDDQ
DQU4
DQU2
DQU3
DQU5
VSSQ
C
D
VDD
VSSQ
DQU6
DQU7
VSSQ
VDDQ
D
VSS
DMU_n/
DBIU_n
VSSQ
DML_n/
DBIL_n
VSSQ
VSS
E
E
F
VSSQ
VDDQ
DQSL_c
DQL1
VDDQ
ZQ
F
G
VDDQ
DQL0
DQSL_t
VDD
VSS
VDDQ
G
H
VSSQ
DQL4
DQL2
DQL3
DQL5
VSSQ
H
J
VDD
VDDQ
DQL6
DQL7
VDDQ
VDD
J
K
VSS
CKE
ODT
CK_t
CK_c
VSS
K
L
VDD
WE_n
A14
ACT_n
CS_n
RAS_n
A16
VDD
L
M
VREFCA
BG0
A10/AP
A12
BC_n
CAS_n
A15
VSS
M
N
VSS
BA0
A4
A3
BA1
TEN
N
P
RESET_n
A6
A0
A1
A5
ALERT_n
P
R
VDD
A8
A2
A9
A7
VPP
R
T
VSS
A11
PAR
NC
A13
VDD
T
1
2
3
7
8
9
Rev. 1.2 / Jul.2017
4
5
6
7
Pin Functional Description
Symbol
Type
CK_t, CK_c
Input
Clock: CK_t and CK_c are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c.
CKE, (CKE1)
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge PowerDown and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in
any bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have
become stable during the power on and initialization sequence, they must be maintained
during all operations (including Self-Refresh). CKE must be maintained high throughout
read and write accesses. Input buffers, excluding CK, CK_c, ODT and CKE, are disabled
during power-down. Input buffers, excluding CKE, are disabled during Self-Refresh.
CS_n, (CS1_n)
Input
Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for
external Rank selection on systems with multiple Ranks. CS_n is considered part of the
command code.
C0,C1,C2
Input
Chip ID: Chip ID is only used for 3DS for 2,4,8high stack via TSV to select each slice of
stacked compnent. Chip ID is considered part of the command code.
ODT, (ODT1)
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to
the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c and
DM_n/DBI_n/TDQS_t,NU/TDQS_c (When TDQS is enabled via Mode Register A11=1 in
MR1) signal for x8 configurations. For x16 configuration ODT is applied to each DQ,
DQSU_c, DQSU_t, DQSL_t, DQSL_c, DMU_n, and DML_n signal. The ODT pin will be
ignored if MR1 is programmed to disable RTT_NOM.
ACT_n
Input
Activation Command Input: ACT_n defines the Activation command being entered along
with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as
Row Address A16, A15 and A14.
Input
Command Inputs RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the
command being entered. Those pins have multi function. For example, for activation
with ACT_n Low, those are Addressing like A16,A15 and A14 but for non-activation command with ACT_n High, those are Command pins for Read, Write and other command
defined in command truth table.
RAS_n/A16,
CAS_n/A15,
WE_n/A14
DM_n/DBI_n/
TDQS_t,
(DMU_n/DBIU_n), (DML_n/
DBIL_n)
Function
Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data.
Input data is masked when DM_n is sampled LOW coincident with that input data during
a Write access. DM_n is sampled on both edges of DQS. DM is muxed with DBI function
Input/ by Mode Register A10,A11,A12 setting in MR5. For x8 device, the function of DM or
Output TDQS is enabled by Mode Register A11 setting in MR1. DBI_n is an input/output identifing wherther to store/output the true or inverted data. If DBI_n is LOW, the data will be
stored/output after inversion inside the DDR4 SDRAM and not inverted if DBI_n is HIGH.
TDQS is only supported in x8.
BG0 - BG1
Input
Bank Group Inputs: BG0 - BG1 define to which bank group an Active, Read, Write or Precharge command is being applied. BG0 also detemines which mode register is to be
accessed during a MRS cycle. x4/8 have BG0 and BG1 but x16 has only BG0.
BA0 - BA1
Input
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or
extended mode register is to be accessed during a MRS cycle.
Rev. 1.2 / Jul.2017
8
Symbol
Type
Function
Input
Address Inputs: Provied the row address for ACTIVATE Commands and the column
address for Read/Write commands th select one location out of the memory array in the
respective bank. (A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have additional functions, see other rows. The address inputs also provide the op-code during
Mode Register Set commands. A17 is only defined for the x4 configration.
A10 / AP
Input
Auto-precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or
all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank
addresses.
A12 / BC_n
Input
Burst Chop: A12 / BC_n is sampled during Read and Write commands to determine if
burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped).
See command truth table for details.
RESET_n
Input
Active Low Asynchronous Reset: Reset is active whenRESET_n is LOW, and inactive
when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n is a
CMOS rail to rail signal with DC high and low at 80% and 20% of VDD.
A0 - A17
DQ
Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then
CRC code is added at the end of Data Burst. Any DQ from DQ0~DQ3 may indicate the
Input /
internal Vref level during test via Mode Register Setting MR4 A4=High. During this
Output
mode, RTT value should be set to Hi-Z. Refer to vendor specific datasheets to determine
which DQ is used.
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
centered in write data. For x16, DQSL corresponds to the data on DQL0-DQL7; DQSU
DQS_t, DQS_c,
Input / corresponds to the data on DQU0-DQU7. The data strobe DQS_t, DQSL_t, and DQSU_t
DQSU_t, DQSU_c,
Output are paired with differential signals DQS_c, DQSL_c, and DQSU_c, respectively, to provide
DQSL_t, DQSL_c
differential pair signaling to the system during reads and writes. DDR4 SDRAM supports
differential data strobe only and does not support single-ended.
TDQS_t, TDQS_c
PAR
ALERT_n
Rev. 1.2 / Jul.2017
Termination Data Strobe: TDQS_t/TDQS_c is applicable for x8 DRAMs only. When
enabled via Mode Register A11 = 1 in MR1, the DRAM will enable the same termination
resistance function on TDQS_t/TDQS_c that is applied to DQS_t/DQS_c. When disabled
Output
via mode register A11 = 0 in MR1, DM/DBI/TDQS will provide the data mask function or
Data Bus Inversion depending on MR5; A11, 12, 10 and TDQS_c is not used. x4/x16
DRAMs must disable the TDQS function via mode register A11 = 0 in MR1.
Input
Command and Address Parity Input : DDR4 Supports Even Parity check in DRAM with
MR setting. Once it’s enabled via Register in MR5, then DRAM calculates Parity with
ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A17-A,0 and C0C2(3DS devices). Input parity should maintain at the rising edge of the clock and at the
same time with command & address with CS_n LOW.
Alert: It has multi functions such as CRC error flag, Command and Address Parity error
flag as Output signal. If there is error in CRC, then Alert_n goes LOW for the period time
interval and goes back HIGH. If there is error in Command Address Parity Check, then
Output Alert_n goes LOW for relatively long period until on going DRAM internal recovery transaction to complete. During Connectivity Test mode, this pin works as input. Using this
signal or not is dependent on system. In case of not connected as Signal, ALERT_n Pin
must be bounded to VDD on board.
9
Symbol
TEN
NC
Type
Function
Input
Connectivity Test Mode Enable: Required on x16 devices and optional input on x4/x8
with densities equal to or greater than 8Gb. HIGH in this pin will enable Connectivity Test
Mode operation along with other pins. It is a CMOS rail to rail signal with AC high and
low at 80% and 20% of VDD. Using this signal or not is dependent on System. This pin
may be DRAM internally pulled low through a weak pull-down resistor to VSS.
No Connect: No internal electrical connection is present.
VDDQ
Supply DQ Power Supply: 1.2 V +/- 0.06 V
VSSQ
Supply DQ Ground
VDD
Supply Power Supply: 1.2 V +/- 0.06 V
VSS
Supply Ground
Vpp
Supply DRAM Activation Power Supply: 2.5V (2.375V min , 2.75 max)
VREFCA
ZQ
Supply Reference voltage for CA
Supply Reference Pin for ZQ calibration
Note:
Input only pins (BG0-BG-1, BA0-BA1, A0-A17, ACT_n, RAS_n,/A16, CAS_n/A15, WE_n/A14, CS_n, CKE, ODT, and
RESET_n) do not supply termination.
Rev. 1.2 / Jul.2017
10
ROW AND COLUMN ADDRESS TABLE
8Gb
Configuration
2Gb x 4
1Gb x 8
512Mb x 16
# of Bank Groups
Bank Address BG Address
Bank Address in a BG
Row Address
Column Address
Page size
4
BG0~BG1
BA0~BA1
A0~A16
A0~ A9
512B
4
BG0~BG1
BA0~BA1
A0~A15
A0~ A9
1 KB
2
BG0
BA0~BA1
A0~A15
A0~ A9
2KB
Rev. 1.2 / Jul.2017
11
Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol
VDD
VDDQ
VPP
VIN, VOUT
TSTG
Parameter
Rating
Units
NOTE
Voltage on VDD pin relative to Vss
-0.3 ~ 1.5
V
1,3
Voltage on VDDQ pin relative to Vss
-0.3 ~ 1.5
V
1,3
Voltage on VPP pin relative to Vss
-0.3 ~ 3.0
V
4
Voltage on any pin except VREFCA relative to Vss
-0.3 ~ 1.5
V
1,3,5
Storage Temperature
-55 to +100
°C
1,2
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than 0.6 x
VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA may be equal to or less than 300 mV
4. VPP must be equal or greater than VDD/VDDQ at all times
5. Overshoot area above 1.5V is specified in DDR4 Device Operation.
DRAM Component Operating Temperature Range
Temperature Range
Symbol
TOPER
Parameter
Normal Operating Temperature Range
Extended Temperature Range
Rating
Units
Notes
0 to 85
oC
1,2
85 to 95
oC
1,3
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported.
During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is
also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use
the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b)
or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).
Rev. 1.2 / Jul.2017
12
AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions
Rating
Symbol
Parameter
VDD
Supply Voltage
1.14
1.2
1.26
V
1,2,3
VDDQ
Supply Voltage for Output
1.14
1.2
1.26
V
1,2,3
VPP
Supply Voltage for DRAM Activating
2.375
2.5
2.75
V
3
Min.
Typ.
Unit
Max.
NOTE
NOTE:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. DC bandwidth is limited to 20MHz.
Rev. 1.2 / Jul.2017
13
IDD and IDDQ Specification Parameters and Test Conditions
IDD, IPP and IDDQ Measurement Conditions
In this chapter, IDD, IPP and IDDQ measurement conditions such as test load and patterns are defined.
Figure shows the setup and test load for IDD, IPP and IDDQ measurements.
•
IDD currents (such as IDD0, IDD0A, IDD1, IDD1A, IDD2N, IDD2NA, IDD2NL, IDD2NT, IDD2P, IDD2Q,
IDD3N, IDD3NA, IDD3P, IDD4R, IDD4RA, IDD4W, IDD4WA, IDD5B, IDD5F2, IDD5F4, IDD6N, IDD6E,
IDD6R, IDD6A, IDD7 and IDD8) are measured as time-averaged currents with all VDD balls of the
DDR4 SDRAM under test tied together. Any IPP or IDDQ current is not included in IDD currents.
•
IPP currents have the same definition as IDD except that the current on the VPP supply is measured.
•
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR4 SDRAM under test tied together. Any IDD current is not included in IDDQ currents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR4 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD, IPP and IDDQ measurements, the following definitions apply:
•
“0” and “LOW” is defined as VIN = VIHAC(min).
•
“MID-LEVEL” is defined as inputs are VREF = VDD / 2.
•
Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns are provided in Table 1.
•
Basic IDD, IPP and IDDQ Measurement Conditions are described in Table 2.
•
Detailed IDD, IPP and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 11.
•
IDD Measurements are done after properly initializing the DDR4 SDRAM. This includes but is not limited to setting
RON = RZQ/7 (34 Ohm in MR1);
RTT_NOM = RZQ/6 (40 Ohm in MR1);
RTT_WR = RZQ/2 (120 Ohm in MR2);
RTT_PARK = Disable;
Qoff = 0B (Output Buffer enabled) in MR1;
TDQS_t disabled in MR1;
CRC disabled in MR2;
CA parity feature disabled in MR5;
Gear down mode disabled in MR3
Read/Write DBI disabled in MR5;
DM disabled in MR5
•
Attention: The IDD, IPP and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
•
Define D = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, LOW, LOW, LOW, LOW} ; apply BG/BA
changes when directed.
•
Define D# = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, HIGH, HIGH, HIGH, HIGH} ; apply
invert of BG/BA changes when directed above.
Rev. 1.2 / Jul.2017
14
IDD
VDD
RESET
CK_t/CK_c
CKE
CS
C
ACT,RAS,CAS,WE
A,BG,BA
ODT
ZQ
IPP
IDDQ
VPP
VDDQ
DDR4 SDRAM
DQS_t/DQS_c
DQ
DM
VSSQ
VSS
NOTE:
1. DIMM level Output test load condition may be different from above
Figure 1 - Measurement Setup and Test Load for IDD, IPP and IDDQ Measurements
Application specific
IDDQ
TestLad
memory channel
environment
Channel
IO Powe
Simulatin
X
IDDQ
Simuaion
IDDQ
Measurement
X
Correlation
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ
Measurement
Rev. 1.2 / Jul.2017
15
Table 1 -Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
11-11-11
13-13-13
15-15-15
17-17-17
tCK
1.25
1.071
0.937
0.833
ns
CL
11
13
15
17
nCK
CWL
11
12
14
17
nCK
Symbol
Unit
nRCD
11
13
15
17
nCK
nRC
39
45
51
56
nCK
nRAS
28
32
36
39
nCK
nRP
11
13
15
17
nCK
x4
16
16
16
16
nCK
x8
20
22
23
26
nCK
x16
28
28
32
36
nCK
x4
4
4
4
4
nCK
nFAW
nRRDS x8
4
4
4
4
nCK
x16
5
5
6
7
nCK
x4
5
5
6
6
nCK
nRRDL x8
5
5
6
6
nCK
x16
6
6
7
8
nCK
tCCD_S
4
4
4
4
nCK
tCCD_L
5
5
6
6
nCK
tWTR_S
2
3
3
3
nCK
tWTR_L
6
7
8
9
nCK
nRFC 2Gb
128
150
171
193
nCK
nRFC 4Gb
208
243
278
313
nCK
nRFC 8Gb
280
327
374
421
nCK
nRFC 16Gb
TBD
TBD
TBD
TBD
nCK
Rev. 1.2 / Jul.2017
16
Table 2 -Basic IDD, IPP and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current (AL=0)
IDD0
IDD0A
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 81; AL: 0; CS_n: High
between ACT and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially
toggling according to Table 3; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: Cycling with one
bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 3
Operating One Bank Active-Precharge Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD0
IPP0
Operating One Bank Active-Precharge IPP Current
Same condition with IDD0
IDD1
Operating One Bank Active-Read-Precharge Current (AL=0)
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 81; AL: 0; CS_n: High
between ACT, RD and PRE; Command, Address, Bank Group Address, Bank Address Inputs,
Data IO: partially toggling according to Table 4; DM_n: stable at 1; Bank Activity: Cycling with one
bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 4
IDD1A
Operating One Bank Active-Read-Precharge Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD1
IPP1
Operating One Bank Active-Read-Precharge IPP Current
Same condition with IDD1
IDD2N
Precharge Standby Current (AL=0)
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,
Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 5; Data
IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 5
IDD2NA
Precharge Standby Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD2N
IPP2N
IDD2NT
Precharge Standby IPP Current
Same condition with IDD2N
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,
Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 6; Data
IO: VSSQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers2; ODT Signal: toggling according to Table 6; Pattern Details: see Table 6
IDDQ2NT Precharge Standby ODT IDDQ Current
(Optional) Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
IDD2NL
Precharge Standby Current with CAL enabled
Same definition like for IDD2N, CAL enabled3
IDD2NG
Precharge Standby Current with Gear Down mode enabled
Same definition like for IDD2N, Gear Down mode enabled3,5
IDD2ND
Precharge Standby Current with DLL disabled
Same definition like for IDD2N, DLL disabled3
Rev. 1.2 / Jul.2017
17
IDD2N_par
Precharge Standby Current with CA parity enabled
Same definition like for IDD2N, CA parity enabled3
IDD2P
Precharge Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 81; AL:
0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at
0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT:
Enabled in Mode Registers2; ODT Signal: stable at 0
IPP2P
Precharge Power-Down IPP Current
Same condition with IDD2P
IDD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,
Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable
at 1;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT
Signal: stable at 0
IDD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,
Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 5; Data
IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks open; Output Buffer and RTT: Enabled in
Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 5
IDD3NA
Active Standby Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD3N
IPP3N
Active Standby IPP Current
Same condition with IDD3N
IDD3P
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,
Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable
at 1; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:
stable at 0
IPP3P
Active Power-Down IPP Current
Same condition with IDD3P
IDD4R
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 82; AL: 0; CS_n: High between RD;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to
Table 7; Data IO: seamless read data burst with different data between one burst and the next one
according to Table 7; DM_n: stable at 1; Bank Activity: all banks open, RD commands cycling through
banks: 0,0,1,1,2,2,... (see Table 7); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:
stable at 0; Pattern Details: see Table 7
IDD4RA
Operating Burst Read Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD4R
IDD4RB
Operating Burst Read Current with Read DBI
Read DBI enabled3, Other conditions: see IDD4R
IPP4R
Operating Burst Read IPP Current
Same condition with IDD4R
IDDQ4R Operating Burst Read IDDQ Current
(Optional) Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
IDDQ4RB Operating Burst Read IDDQ Current with Read DBI
(Optional) Same definition like for IDD4RB, however measuring IDDQ current instead of IDD current
Rev. 1.2 / Jul.2017
18
IDD4W
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: High between WR;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to
Table 8; Data IO: seamless write data burst with different data between one burst and the next one
according to Table 8; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through
banks: 0,0,1,1,2,2,... (see Table 8); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:
stable at HIGH; Pattern Details: see Table 8
IDD4WA
Operating Burst Write Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD4W
IDD4WB
Operating Burst Write Current with Write DBI
Write DBI enabled3, Other conditions: see IDD4W
IDD4WC
Operating Burst Write Current with Write CRC
Write CRC enabled3, Other conditions: see IDD4W
IDD4W_par
Operating Burst Write Current with CA Parity
CA Parity enabled3, Other conditions: see IDD4W
IPP4W
Operating Burst Write IPP Current
Same condition with IDD4W
IDD5B
Burst Refresh Current (1X REF)
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 81; AL: 0; CS_n: High between REF;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to
Table 9; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: REF command every nRFC (see Table 9);
Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see
Table 9
IPP5B
Burst Refresh Write IPP Current (1X REF)
Same condition with IDD5B
IDD5F2
Burst Refresh Current (2X REF)
tRFC=tRFC_x2, Other conditions: see IDD5B
IPP5F2
Burst Refresh Write IPP Current (2X REF)
Same condition with IDD5F2
IDD5F4
Burst Refresh Current (4X REF)
tRFC=tRFC_x4, Other conditions: see IDD5B
IPP5F4
Burst Refresh Write IPP Current (4X REF)
Same condition with IDD5F4
Self Refresh Current: Normal Temperature Range
IDD6N
TCASE: 0 - 85°C; Low Power Array Self Refresh (LP ASR) : Normal4; CKE: Low; External clock:
Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group
Address, Bank Address, Data IO: High; DM_n: stable at 1; Bank Activity: Self-Refresh operation;
Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL
IPP6N
Self Refresh IPP Current: Normal Temperature Range
Same condition with IDD6N
IDD6E
Self-Refresh Current: Extended Temperature Range)
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Extended4; CKE: Low; External clock:
Off; CK_t and CK_c: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n, Command, Address, Bank Group
Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL
IPP6E
Self Refresh IPP Current: Extended Temperature Range
Same condition with IDD6E
Rev. 1.2 / Jul.2017
19
IDD6R
Self-Refresh Current: Reduced Temperature Range
TCASE: 0 - TBD (~35-45)°C; Low Power Array Self Refresh (LP ASR) : Reduced4; CKE: Low;
External clock: Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command,
Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity:
Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2;
ODT Signal: MID-LEVEL
IPP6R
Self Refresh IPP Current: Reduced Temperature Range
Same condition with IDD6R
IDD6A
Auto Self-Refresh Current
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Auto4; CKE: Low; External clock: Off;
CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group
Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Auto Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL
IPP6A
Auto Self-Refresh IPP Current
Same condition with IDD6A
IDD7
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 1; BL: 81; AL:
CL-1; CS_n: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address
Inputs: partially toggling according to Table 10; Data IO: read data bursts with different data between
one burst and the next one according to Table 10; DM_n: stable at 1; Bank Activity: two times
interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 10; Output Buffer and
RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 10
IPP7
Operating Bank Interleave Read IPP Current
Same condition with IDD7
IDD8
Maximum Power Down Current
TBD
IPP8
Maximum Power Down IPP Current
Same condition with IDD8
Rev. 1.2 / Jul.2017
20
NOTE :
1. Burst Length: BL8 fixed by MRS: set MR0 [A1:0=00].
2. Output Buffer Enable
- set MR1 [A12 = 0] : Qoff = Output buffer enabled
- set MR1 [A2:1 = 00] : Output Driver Impedance Control = RZQ/7
RTT_Nom enable
- set MR1 [A10:8 = 011] : RTT_NOM = RZQ/6
RTT_WR enable
- set MR2 [A10:9 = 01] : RTT_WR = RZQ/2
RTT_PARK disable
- set MR5 [A8:6 = 000]
3. CAL enabled : set MR4 [A8:6 = 001] : 1600MT/s
010] : 1866MT/s, 2133MT/s
011] : 2400MT/s
Gear Down mode enabled :set MR3 [A3 = 1] : 1/4 Rate
DLL disabled : set MR1 [A0 = 0]
CA parity enabled :set MR5 [A2:0 = 001] : 1600MT/s,1866MT/s, 2133MT/s
010] : 2400MT/s
Read DBI enabled : set MR5 [A12 = 1]
Write DBI enabled : set :MR5 [A11 = 1]
4. Low Power Array Self Refresh (LP ASR) : set MR2 [A7:6 = 00] : Normal
01] : Reduced Temperature range
10] : Extended Temperature range
11] : Auto Self Refresh
5. IDD2NG should be measured after sync pulse(NOP) input.
Rev. 1.2 / Jul.2017
21
Sub-Loop
Cycle
Number
Command
CS_n
ACT_n
RAS_n/ A16
CAS_n/ A15
WE_n/ A14
ODT
C[2:0]3
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
CKE
CK_t /CK_c
Table 3 - IDD0, IDD0A and IPP0 Measurement-Loop Pattern1
Data4
0
0
ACT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
1,2
D, D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
3,4
D_#,
D_#
1
1
1
1
1
0
0
32
3
0
0
0
7
F
0
-
0
0
0
0
0
-
...
nRAS
toggling
Static High
...
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
0
1
0
1
0
0
0
0
0
0
repeat pattern 1...4 until nRC - 1, truncate if necessary
1
1*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 1 instead
2
2*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
3
3*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 3 instead
4
4*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
5
5*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 2 instead
6
6*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
7
7*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 0 instead
8
8*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead
9
9*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 1 instead
10
10*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
11
11*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 3 instead
12
12*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead
13
13*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 2 instead
14
14*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead
15
15*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 0 instead
For x4
and x8
only
NOTE:
1 .DQS_t, DQS_c are VDDQ.
2. BG1 is don’t care for x16 device
3. C[2:0] are used only for 3DS device
4. DQ signals are VDDQ.
Rev. 1.2 / Jul.2017
22
Static High
toggling
A[9:7]
A[10]/AP
0
0
0
A[17,13,11]
ODT
0
0
1
A12/BC_n
WE_n/A14
0
0
1
BA[1:0]
CAS_n/A15
0
0
1
BG[1:0]2
RAS_n/A16
0
0
1
C[2:0]3
ACT_n
0
1
1
A[2:0]
1
ACT
D, D
D#, D#
A[6:3]
...
nRCD -AL
CS_n
0 0
1, 2
3, 4
Command
Cycle
Number
CKE
Sub-Loop
CK_t, CK_c
Table 4 - IDD1, IDD1A and IPP1 Measurement-Loop Patterna)
Data4
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 3b 3 0 0 0 7 F
repeat pattern 1...4 until nRCD - AL - 1, truncate if necessary
RD
0 1 1 0 1 0 0 0 0 0 0 0 0 0
0
0
0
-
0
D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
0
0
-
0
0
F
0
0
0
-
...
nRAS
...
1*nRC + 0
1*nRC + 1, 2
1*nRC + 3, 4
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
0 1 0 1 0 0 0 0 0 0 0 0 0
repeat pattern 1...4 until nRC - 1, truncate if necessary
ACT
0 0 0 1 1 0 0 1 1 0 0 0 0
D, D
1 0 0 0 0 0 0 0 0 0 0 0 0
D#, D# 1 1 1 1 1 0 0 3b 3 0 0 0 7
...
repeat pattern nRC + 1...4 until 1*nRC + nRAS - 1, truncate if
1*nRC + nRCD RD
0 1 1 0 1 0 0 1 1 0 0 0 0
- AL
necessary
0 0 D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
...
repeat pattern 1...4 until nRAS - 1, truncate if necessary
1*nRC + nRAS PRE
0 1 0 1 0 0 0 1 1 0 0 0 0 0
...
repeat nRC + 1...4 until 2*nRC - 1, truncate if necessary
2 2*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
3 3*nRC
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
4 4*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
5 5*nRC
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead
6 6*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
8 7*nRC
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead
9 9*nRC
repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 0 instead
10 10*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 1 instead
11 11*nRC
repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 2 instead
12 12*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 3 instead
13 13*nRC
repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 1 instead
14 14*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 2 instead
15 15*nRC
repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 3 instead
16 16*nRC
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 0 instead
0
-
For x4 and x8 only
NOTE:
1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ
2. BG1 is don’t care for x16 device
3. C[2:0] are used only for 3DS device
4.Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ.
Rev. 1.2 / Jul.2017
23
Table 5 - IDD2N, IDD2NA, IDD2NL, IDD2NG, IDD2ND, IDD2N_par, IPP2,IDD3N,
IDD3NA and IDD3P
Static High
toggling
ACT_n
RAS_n/A16
CAS_n/A15
WE_n/A14
ODT
C[2:0]3
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
D, D
CS_n
0 0
Command
Cycle
Number
Sub-Loop
CKE
CK_t, CK_c
Measurement-Loop Pattern1
Data4
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
D, D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
D#,
D#
1
1
1
1
1
0
0
32
3
0
0
0
7
F
0
0
3
D#,
D#
1
1
1
1
1
0
0
32
3
0
0
0
7
F
0
0
1 4-7
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 1 instead
2 8-11
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
3 12-15
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 3 instead
4 16-19
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
5 20-23
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 2 instead
6 24-27
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
7 28-31
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 0 instead
8 32-35
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead
9 36-39
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 1 instead
10 40-43
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
11 44-47
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 3 instead
12 48-51
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead
13 52-55
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 2 instead
14 56-59
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead
15 60-63
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 0 instead
NOTE :
1. DQS_t, DQS_c are VDDQ.
2. BG1 is don’t care for x16 device
3. C[2:0] are used only for 3DS device
4. DQ signals are VDDQ.
Rev. 1.2 / Jul.2017
24
A[2:0]
A[6:3]
A[9:7]
A[10]/AP
A[17,13,11]
A12/BC_n
BA[1:0]
BG[1:0]2
C[2:0]3
ODT
WE_n/A14
CAS_n/A15
RAS_n/A16
ACT_n
CS_n
Command
Cycle
Number
Sub-Loop
CKE
Static High
toggling
CK_t, CK_c
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern1
Data4
0 0
D, D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
1
D, D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
2
D#, D#
1
1
1
1
1
0
0
32
3
0
0
0
7
F
0
-
3
D#, D#
1
1
1
1
1
0
0
32
3
0
0
0
7
F
0
-
1 4-7
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 1 instead
2 8-11
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 0, BA[1:0] = 2 instead
3 12-15
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 3 instead
4 16-19
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 0, BA[1:0] = 1 instead
5 20-23
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 2 instead
6 24-27
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 0, BA[1:0] = 3 instead
7 28-31
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 0 instead
8 32-35
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 0 instead
9 36-39
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 1 instead
10 40-43
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 2 instead
11 44-47
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 3 instead
12 48-51
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 1 instead
13 52-55
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 2 instead
14 56-59
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 3 instead
15 60-63
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 0 instead
For x4
and x8
only
NOTE :
1. DQS_t, DQS_c are VDDQ.
2. BG1 is don’t care for x16 device
3. C[2:0] are used only for 3DS device
4. DQ signals are VDDQ.
Rev. 1.2 / Jul.2017
25
WE_n/A14
ODT
C[2:0]3
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]
1
0
0
0
0
0
0
1
D
1
0
0
0
0
0
0
0
0
0
0
2,3
D#, D#
1
1
1
1
1
0
0
3
2
3
0
0
4
RD
0
1
1
0
1
0
0
1
1
0
0
5
D
1
0
0
0
0
0
0
0
0
0
6,7
D#, D#
1
1
1
1
1
0
0
2
3
0
2
8-11
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
3
12-15 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
4
16-19 repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
5
20-23 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead
6
24-27 repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
7
28-31 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead
8
32-35 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead
9
36-39 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead
Static High
toggling
1
3
A[2:0]
CAS_n/A15
0
A[6:3]
RAS_n/A16
1
A[9:7]
ACT_n
1
A[10]/AP
CS_n
0
Command
RD
0
Cycle
Number
CKE
0
Sub-Loop
CK_t, CK_c
Table 7 - IDD4R, IDDR4RA, IDD4RB and IDDQ4R Measurement-Loop Pattern1
0
0
0
0
0
0
0
0
-
0
7
F
0
-
0
7
F
0
D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
0
0
0
0
0
-
0
0
7
F
0
-
10 40-43 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
11 44-47 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead
Data4
D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
For x4 and x8 only
12 48-51 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead
13 52-55 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead
14 56-59 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead
15 60-63 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead
NOTE :
1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ.
2. BG1 is don’t care for x16 device
3. C[2:0] are used only for 3DS device
4. Burst Sequence driven on each DQ signal by Read Command.
Rev. 1.2 / Jul.2017
26
Static High
toggling
C[2:0]3
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]
1
0
1
1
0
0
0
0
0
1
D
1
0
0
0
0
1
0
0
0
0
0
2,3
D#, D#
1
1
1
1
1
1
0
3
2
3
0
0
4
WR
0
1
1
0
1
1
0
1
1
0
0
0
5
D
1
0
0
0
0
1
0
0
0
0
0
6,7
D#, D#
1
1
1
1
1
1
0
2
3
0
0
3
A[2:0]
ODT
1
A[6:3]
WE_n/A14
0
A[9:7]
CAS_n/A15
WR
A[10]/AP
RAS_n/A16
0
Command
ACT_n
1
CS_n
0
Cycle
Number
CKE
Sub-Loop
CK_t, CK_c
Table 8 - IDD4W, IDD4WA, IDD4WB and IDD4W_par Measurement-Loop Pattern1
0
0
0
0
0
0
0
0
-
0
7
F
0
-
7
F
0
D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
0
0
0
0
-
0
7
F
0
-
2
8-11
3
12-15 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
4
16-19 repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
5
20-23 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead
6
24-27 repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
7
28-31 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead
8
32-35 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead
9
36-39 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead
Data4
D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
2
repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 2 instead
10 40-43 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
11 44-47 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead
For x4 and x8 only
12 48-51 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead
13 52-55 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead
14 56-59 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead
15 60-63 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead
NOTE :
1. DQS_t, DQS_c are used according to WR Commands, otherwise VDDQ.
2. BG1 is don’t care for x16 device
3. C[2:0] are used only for 3DS device
4. Burst Sequence driven on each DQ signal by Write Command.
Rev. 1.2 / Jul.2017
27
CS_n
ACT_n
RAS_n/A16
CAS_n/A15
WE_n/A14
ODT
C[2:0]c
BG[1:0]b
BA[1:0]
A12/BC_n
A[17,13,11]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
D8=CRC
1,2
D, D
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
-
3,4
D#, D#
1
1
1
1
1
1
0
2
3
3
0
0
0
7
F
0
-
5
WR
0
1
1
0
1
1
0
1
1
0
0
0
7
F
0
D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
D8=CRC
6,7
D, D
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
-
8,9
D#, D#
1
1
1
1
1
1
0
32 3
0
0
0
7
F
0
-
Static High
toggling
Cycle
Number
0 0
Command
WR
Sub-Loop
CKE
CK_t, CK_c
Table 9 - IDD4WC Measurement-Loop Pattern1
2 10-14
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
3 15-19
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
4 20-24
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
5 25-29
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead
6 30-34
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
7 35-39
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead
8 40-44
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead
9 45-49
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead
10 50-54
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
11 55-59
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead
12 60-64
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead
13 65-69
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead
14 70-74
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead
15 75-79
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead
Datad
For x4 and x8 only
NOTE :
1. DQS_t, DQS_c are VDDQ.
2. BG1 is don’t care for x16 device.
3. C[2:0] are used only for 3DS device.
4. Burst Sequence driven on each DQ signal by Write Command.
Rev. 1.2 / Jul.2017
28
CS_n
ACT_n
RAS_n/A16
CAS_n/A15
WE_n/A14
ODT
C[2:0]3
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
0 0
REF
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
1 1
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
2
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
3
D#, D#
1
1
1
1
1
0
0
32
3
0
0
0
7
F
0
-
4
D#, D#
1
1
1
1
1
0
0
32 3
0
0
0
7
F
0
-
4-7
repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 1 instead
8-11
repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 2 instead
12-15
repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 3 instead
16-19
repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 1 instead
20-23
repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 2 instead
24-27
repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 3 instead
28-31
repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 0 instead
32-35
repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 0 instead
36-39
repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 1 instead
40-43
repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 2 instead
44-47
repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 3 instead
48-51
repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 1 instead
52-55
repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 2 instead
56-59
repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 3 instead
60-63
repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 0 instead
Cycle
Number
Command
Data4
Sub-Loop
CKE
Static High
toggling
CK_t, CK_c
Table 10 - IDD5B Measurement-Loop Pattern1
For x4 and x8
only
2 64 ... nRFC - 1 repeat Sub-Loop 1, Truncate, if necessary
NOTE :
1. DQS_t, DQS_c are VDDQ.
2. BG1 is don’t care for x16 device.
3. C[2:0] are used only for 3DS device.
4. DQ signals are VDDQ.
Rev. 1.2 / Jul.2017
29
C[2:0]3
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]
A[10]/AP
A[9:7]
A[6:3]
0
0
0
1
0
0
0
0
0
0
0,
1,
0,
1,
4
use
use
use
use
BG[1:0]2 = 0, BA[1:0] = 1
BG[1:0]2 = 1, BA[1:0] = 2
BG[1:0]2 = 0, BA[1:0] = 3
BG[1:0]2 = 1, BA[1:0] = 0
instead
instead
instead
instead
Sub-Loop
Sub-Loop
Sub-Loop
Sub-Loop
Sub-Loop
0,
1,
0,
1,
4
use
use
use
use
BG[1:0]2 = 2, BA[1:0] = 0
BG[1:0]2 = 3, BA[1:0] = 1
BG[1:0]2 = 2, BA[1:0] = 2
BG[1:0]2 = 3, BA[1:0] = 3
instead
instead
instead
instead
Sub-Loop
Sub-Loop
Sub-Loop
Sub-Loop
Sub-Loop
0,
1,
0,
1,
4
use
use
use
use
BG[1:0]2 = 2, BA[1:0] = 1 instead
BG[1:0]2 = 3, BA[1:0] = 2 instead
BG[1:0]2 = 2, BA[1:0] = 3 instead
BG[1:0]2 = 3, BA[1:0] = 0 instead
ACT
RDA
0
0
0
1
2
3
...
1 nRRD
nRRD + 1
D
D#
repeat
ACT
RDA
...
2 2*nRRD
3 3*nRRD
4 4*nRRD
repeat
repeat
repeat
repeat
0
0 D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 32 3 0 0 0 7 F 0
pattern 2...3 until nRRD - 1, if nRRD > 4. Truncate if necessary
0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
0 1 1 0 1 0
1 1 0 0 1 0 0 0 D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
pattern 2 ... 3 until 2*nRRD - 1, if nRRD > 4. Truncate if necessary
Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
pattern 2 ... 3 until nFAW - 1, if nFAW > 4*nRRD. Truncate if necessary
5
6
7
8
9
nFAW
nFAW
nFAW
nFAW
nFAW
repeat
repeat
repeat
repeat
repeat
Sub-Loop
Sub-Loop
Sub-Loop
Sub-Loop
Sub-Loop
10
11
12
13
14
2*nFAW
2*nFAW + nRRD
2*nFAW + 2*nRRD
2*nFAW + 3*nRRD
2*nFAW + 4*nRRD
repeat
repeat
repeat
repeat
repeat
15
16
17
18
19
3*nFAW
3*nFAW + nRRD
3*nFAW + 2*nRRD
3*nFAW + 3*nRRD
3*nFAW + 4*nRRD
repeat
repeat
repeat
repeat
repeat
Cycle
Number
+
+
+
+
20 4*nFAW
nRRD
2*nRRD
3*nRRD
4*nRRD
A[2:0]
ACT_n
0
1
CS_n
0
0
Command
ODT
0
0
WE_n/A14
0
0
CAS_n/A15
0
0
RAS_n/A16
0
0
1
0 0
1
CKE
Sub-Loop
Static High
toggling
CK_t, CK_c
Table 11 - IDD7 Measurement-Loop Pattern1
Data4
For x4 and x8
only
repeat pattern 2 ... 3 until nRC - 1, if nRC > 4*nFAW. Truncate if necessary
NOTE :
1. DQS_t, DQS_c are VDDQ.
2. BG1 is don’t care for x16 device.
3. C[2:0] are used only for 3DS device.
4. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ
Rev. 1.2 / Jul.2017
30
IDD Specifications
IDD and IPP values are for full operating range of voltage and temperature unless otherwise noted. IDD
and IPP values are for full operating range of voltage and temperature unless otherwise noted.
IDD and IDDQ Specification
Symbol
IDD0
IDD0A
IDD1
IDD1A
IDD2N
IDD2NA
IDD2NT
IDD2NL
IDD2NG
IDD2ND
IDD2N_par
IDD2P
IDD2Q
IDD3N
IDD3NA
IDD3P
IDD4R
IDD4RA
IDD4RB
IDD4W
IDD4WA
IDD4WB
IDD4WC
IDD4WC_par
IDD5B
IDD5F2
IDD5F4
IDD6N
IDD6E
IDD6R
IDD6A
IDD7
IDD8
2133
2400
2666
x4
x8
x16
x4
x8
x16
x4
x8
x16
37
37
44
46
26
26
31
18
26
26
26
18
22
44
44
36
104
113
112
98
100
94
91
108
195
140
123
22
28
14
28
160
12
37
37
46
49
26
26
31
18
26
26
26
18
22
44
44
36
115
124
124
111
114
110
106
113
195
140
123
22
28
14
28
145
12
44
44
57
60
26
26
31
18
26
26
26
18
22
44
44
36
177
187
184
154
157
154
148
164
195
140
123
22
28
14
28
181
12
38
38
46
48
27
27
32
18
26
26
26
18
22
45
45
37
113
123
122
107
109
102
99
122
196
142
127
22
28
14
28
177
12
38
38
48
51
27
27
32
18
26
26
26
18
22
45
45
37
124
134
134
120
123
120
114
136
196
142
127
22
28
14
28
152
12
46
46
60
63
27
27
32
18
26
26
26
18
22
45
45
37
195
204
204
170
172
170
164
186
196
142
127
22
28
14
28
185
12
40
40
49
51
29
29
35
19
29
29
29
19
24
47
47
38
122
134
132
116
119
110
108
131
197
144
129
22
28
14
28
244
12
40
40
51
54
29
29
35
19
29
29
29
19
24
47
47
38
134
146
145
131
134
130
124
146
197
144
129
22
28
14
28
160
12
48
48
62
66
29
29
35
19
29
29
29
19
24
47
47
38
229
222
221
185
187
185
179
200
197
144
129
22
28
14
28
210
12
Unit
NOTE
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
NOTE :
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR4 SDRAM devices support the following options or requirements referred to in this material.
Rev. 1.2 / Jul.2017
31
IPP Specification
Symbol
IPP0
IPP1
IPP2N
IPP2P
IPP3N
IPP3P
IPP4R
IPP4W
IPP5B
IPP5F2
IPP5F4
IPP6N
IPP6E
IPP6R
IPP6A
IPP7
IPP8
2133
2400
2666
x4
x8
x16
x4
x8
x16
x4
x8
x16
6
7
3.2
3.2
15
15
15
15
65
45
40
4
7
4.1
7
25
3.2
6
7
3.2
3.2
15
15
15
15
65
45
40
4
7
4.1
7
19
3.2
10
10
3.2
3.2
18
18
18
18
65
45
40
4
7
4.1
7
24
3.2
6
7
3.2
3.2
15
15
15
15
65
46
40
4
7
4.1
7
25
3.2
6
7
3.2
3.2
15
15
15
15
65
46
40
4
7
4.1
7
19
3.2
10
10
3.2
3.2
18
18
18
18
65
46
40
4
7
4.1
7
24
3.2
6
7
3.2
3.2
15
15
15
15
65
47
40
4
7
4.1
7
29
3.2
6
7
3.2
3.2
15
15
15
15
65
47
40
4
7
4.1
7
21
3.2
10
10
3.2
3.2
18
18
18
18
65
47
40
4
7
4.1
7
28
3.2
Unit
NOTE
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
NOTE :
1.Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR4 SDRAM devices support the following
options or requirements referred to in this material.
IDD6 Specification
Symbol
Temperature
Range
IDD6N
IDD6E
IDD6R
IDD6A
0
0
0
0
-
85
95
45
85
oC
oC
oC
oC
2133/2400/2666
x4
x8
x16
Unit
NOTE
22
28
14
28
22
28
14
28
22
28
14
28
mA
mA
mA
mA
3,4
4,5,6
4,6,8
4,6,7
NOTE :
1. Some IDD currents are higher for x16 organization due to larger page-size architecture.
2. Max. values for IDD currents considering worst case conditions of process, temperature and voltage.
3. Applicable for MR2 settings A6=0 and A7=0.
4. Supplier data sheets include a max value for IDD6.
5. Applicable for MR2 settings A6=0 and A7=1. IDD6E is only specified for devices which support the Extended Temperature Range
feature.
6. Refer to the supplier data sheet for the value specification method (e.g. max, typical) for IDD6E and IDD6A
7. Applicable for MR2 settings A6=1 and A7=0. IDD6A is only specified for devices which support the Auto Self Refresh feature.
8. Applicable for MR2 settings MR2 [A7:A6 = 01] : Reduced Temperature range. IDD6R is verified by design and characterization, and
may not be subject to production test
Rev. 1.2 / Jul.2017
32
Input/Output Capacitance
Silicon pad I/O Capacitance
Symbol
Parameter
DDR41600,1866,2133
DDR4-2400,2666
min
max
min
max
Unit
NOTE
CIO
Input/output capacitance
0.55
1.4
0.55
1.15
pF
1,2,3
CDIO
Input/output capacitance delta
-0.1
0.1
-0.1
0.1
pF
1,2,3,11
CDDQS
Input/output capacitance delta
DQS_t and DQS_c
0.05
pF
1,2,3,5
CCK
Input capacitance, CK_t and
CK_c
0.7
pF
1,3
CDCK
Input capacitance delta CK_t and
CK_c
0.05
pF
1,3,4
CI
Input capacitance
(CTRL, ADD, CMD pins only)
0.2
0.8
0.2
0.7
pF
1,3,6
CDI_ CTRL
Input capacitance delta
(All CTRL pins only)
-0.1
0.1
-0.1
0.1
pF
1,3,7,8
CDI_ ADD_CMD
Input capacitance delta
(All ADD/CMD pins only)
-0.1
0.1
-0.1
0.1
pF
1,2,9,10
CALERT
Input/output capacitance of
ALERT
0.5
1.5
0.5
1.5
pF
1,3
CZQ
Input/output capacitance of ZQ
-
2.3
-
2.3
pF
1,3,12
CTEN
Input capacitance of TEN
0.2
2.3
0.2
2.3
pF
1,3,13
0.05
0.2
0.8
0.2
0.05
NOTE :
1. This parameter is not subject to production test. It is verified by design and characterization. The silicon only capacitance is validated by de-embedding the package L & C parasitic. The capacitance is measured with VDD, VDDQ, VSS, VSSQ applied with all
other signal pins floating. Measurement procedure tbd.
2. DQ, DM_n, DQS_T, DQS_C, TDQS_T, TDQS_C. Although the DM, TDQS_T and TDQS_C pins have different functions, the loading
matches DQ and DQS
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value CK_T-CK_C
5. Absolute value of CIO(DQS_T)-CIO(DQS_C)
6. CI applies to ODT, CS_n, CKE, A0-A17, BA0-BA1, BG0-BG1, RAS_n/A16, CAS_n/A15, WE_n/A14, ACT_n and PAR.
7. CDI CTRL applies to ODT, CS_n and CKE
8. CDI_CTRL = CI(CTRL)-0.5*(CI(CLK_T)+CI(CLK_C))
9. CDI_ADD_ CMD applies to, A0-A17, BA0-BA1, BG0-BG1,RAS_n/A16, CAS_n/A15, WE_n/A14, ACT_n and PAR.
10. CDI_ADD_CMD = CI(ADD_CMD)-0.5*(CI(CLK_T)+CI(CLK_C))
11. CDIO = CIO(DQ,DM)-0.5*(CIO(DQS_T)+CIO(DQS_C))
12. Maximum external load capacitance on ZQ pin: tbd pF.
13. TEN pis may be DRAM internally pulled low through a weak pull-down resistor to VSS. In this case CTEN might not be valid and
system shall verify TEN signal with Vendor specific information.
Rev. 1.2 / Jul.2017
33
DRAM package electrical specifications (x4/x8)
Symbol
Parameter
ZIO
DDR4-1600,1866,2133,2400,2666
Unit
NOTE
85
1,2,4,5,10,11
14
42
ps
1,3,4,5,11
Input/output Lpkg
-
3.3
nH
11,12
CIO
Input/output Cpkg
-
0.78
pF
11,13
ZIO DQS
DQS_t, DQS_c Zpkg
45
85
1,2,5,10,11
TdIO DQS
DQS_t, DQS_c Pkg Delay
14
42
ps
1,3,5,10,11
LIO DQS
DQS Lpkg
-
3.3
nH
11,12
CIO DQS
DQS Cpkg
-
0.78
pF
11,13
DZDIO DQS
Delta Zpkg DQS_t, DQS_c
-
10
1,2,5,7,10
DTdDIO DQS
Delta Delay DQS_t, DQS_c
-
5
ps
1,3,5,7,10
ZI CTRL
Input- CTRL pins Zpkg
50
90
1,2,5,9,10,11
TdI CTRL
Input- CTRL pins Pkg Delay
14
42
ps
1,3,5,9,10,11
LI CTRL
Input CTRL Lpkg
-
3.4
nH
11,12
CI CTRL
Input CTRL Cpkg
-
0.7
pF
11,13
ZIADD CMD
Input- CMD ADD pins Zpkg
50
90
1,2,5,8,10,11
14
45
ps
1,3,5,8,10,11
min
max
Input/output Zpkg
45
TDIO
Input/output Pkg Delay
LIO
TdIADD CMD Input- CMD ADD pins Pkg Delay
LI ADD CMD
Input CMD ADD Lpkg
-
3.6
nH
11,12
CI ADD CMD
Input CMD ADD Cpkg
-
0.74
pF
11,13
ZCK
CLK_t & CLK_c Zpkg
50
90
1,2,5,10,11
TdCK
CLK_t & CLK_c Pkg Delay
14
42
ps
1,3,5,10,11
LI CLK
Input CLK Lpkg
-
3.4
nH
11,12
CI CLK
Input CLK Cpkg
-
0.7
pF
11,13
DZDLK
Delta Zpkg CLK_t & CLK_c
-
10
1,2,5,6,10
DTdLK
Delta Delay CLK_t & CLK_c
-
5
ps
1,3,5,6,10
ZO ZQ
ZQ Zpkg
-
100
1,2,5,10,11
TdO ZQ
ZQ Delay
20
90
ps
1,3,5,10,11
ZO ALERT
ALERT Zpkg
40
100
1,2,5,10,11
TdO ALERT
ALERT Delay
20
55
ps
1,3,5,10,11
NOTE :
Rev. 1.2 / Jul.2017
34
1. This parameter is not subject to production test. It is verified by design and characterization. The package parasitic( L & C) are validated using package only samples. The capacitance is measured with VDD, VDDQ, VSS, VSSQ shorted with all other signal pins
floating. The inductance is measured with VDD, VDDQ, VSS and VSSQ shorted and all other signal pins shorted at the die side(not
pin). Measurement procedure tbd
2. Package only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a given pin where:
Zpkg(total per pin) =
Lpkg/Cpkg
3. Package only delay(Tpkg) is calculated based on Lpkg and Cpkg total for a given pin where:
Tdpkg(total per pin) = LpkgCpkg
4. Z & Td IO applies to DQ, DM, TDQS_T and TDQS_C
5. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
6. Absolute value of ZCK_t-ZCK_c for impedance(Z) or absolute value of TdCK_t-TdCK_c for delay(Td).
7. Absolute value of ZIO(DQS_t)-ZIO(DQS_c) for impedance(Z) or absolute value of TdIO(DQS_t)-TdIO(DQS_c) for delay(Td)
8. ZI & Td ADD CMD applies to A0-A13, ACT_n, BA0-BA1, BG0-BG1, RAS_n/A16, CAS_n/A15, WE_n/A14 and PAR.
9. ZI & Td CTRL applies to ODT, CS_n and CKE
10. This table applies to monolithic X4 and X8 devices.
11. Package implementations shall meet spec if the Zpkg and Pkg Delay fall within the ranges shown, and the maximum Lpkg and
Cpkg do not exceed the maximum values shown.
12. It is assumed that Lpkg can be approximated as Lpkg = Zo*Td.
13. It is assumed that Cpkg can be approximated as Cpkg = Td/Zo.
Rev. 1.2 / Jul.2017
35
DRAM package electrical specifications (x16)
Symbol
Parameter
ZIO
DDR4-1600,1866,2133,2400,2666
Unit
NOTE
85
1
14
45
ps
1
Input/output Lpkg
-
3.4
nH
1,2
CIO
Input/output Cpkg
-
0.82
pF
1,3
ZIO DQS
DQS_t, DQS_c Zpkg
45
85
1
TdIO DQS
DQS_t, DQS_c Pkg Delay
14
45
ps
1
LIO DQS
DQS Lpkg
-
3.4
nH
1,2
CIO DQS
DQS Cpkg
-
0.82
pF
1,3
Delta Zpkg DQSU_t, DQSU_c
-
10
-
min
max
Input/output Zpkg
45
TDIO
Input/output Pkg Delay
LIO
DZDIO DQS
Delta Zpkg DQSL_t, DQSL_c
-
10
-
Delta Delay DQSU_t, DQSU_c
-
5
ps
-
Delta Delay DQSL_t, DQSL_c
-
5
ps
-
ZI CTRL
Input- CTRL pins Zpkg
50
90
1
TdI CTRL
Input- CTRL pins Pkg Delay
14
42
ps
1
LI CTRL
Input CTRL Lpkg
-
3.4
nH
1,2
CI CTRL
Input CTRL Cpkg
-
0.7
pF
1,3
ZIADD CMD
Input- CMD ADD pins Zpkg
50
90
1
14
52
ps
1
DTdDIO DQS
TdIADD CMD Input- CMD ADD pins Pkg Delay
LI ADD CMD
Input CMD ADD Lpkg
-
3.9
nH
1,2
CI ADD CMD
Input CMD ADD Cpkg
-
0.86
pF
1,3
ZCK
CLK_t & CLK_c Zpkg
50
90
1
TdCK
CLK_t & CLK_c Pkg Delay
14
42
ps
1
LI CLK
Input CLK Lpkg
-
3.4
nH
1,2
CI CLK
Input CLK Cpkg
-
0.7
pF
1,3
DZDLK
Delta Zpkg CLK_t & CLK_c
-
10
-
DTdLK
Delta Delay CLK_t & CLK_c
-
5
ps
-
ZO ZQ
ZQ Zpkg
-
100
-
TdO ZQ
ZQ Delay
20
90
ps
-
ZO ALERT
ALERT Zpkg
40
100
-
TdO ALERT
ALERT Delay
20
55
ps
-
NOTE :
Rev. 1.2 / Jul.2017
36
1. Package implementations shall meet spec if the Zpkg and Pkg Delay fall within the ranges shown, and the maximum Lpkg and
Cpkg do not exceed the maximum values shown.
2. It is assumed that Lpkg can be approximated as Lpkg = Zo*Td.
3. It is assumed that Cpkg can be approximated as Cpkg = Td/Zo.
Rev. 1.2 / Jul.2017
37
Standard Speed Bins
DDR4-1600 Speed Bins and Operations
Speed Bin
DDR4-1600K
CL-nRCD-nRP
11-11-11
Parameter
Symbol
min
Unit
NOTE
18.00
ns
11
max
13.7513
Internal read command to first
data
tAA
Internal read command to first
data with read DBI enabled
tAA_DBI
tAA(min) + 2nCK
tAA(max) +2nCK
ns
11
ACT to internal read or write
delay time
tRCD
13.75
(13.50)5,11
-
ns
11
PRE command period
tRP
13.75
(13.50)5,11
-
ns
11
ACT to PRE command period
tRAS
35
9 x tREFI
ns
11
ACT to ACT or REF command
period
tRC
48.75
(48.50)5,11
-
ns
11
1.5
1.6
ns
1,2,3,4,10
,13
CWL = 9
(13.50)5,11
Normal
Read DBI
CL = 9
CL = 11
tCK(AVG)
CL = 10
CL = 12
tCK(AVG)
Reserved
ns
1,2,3,4,10
CL = 10
CL = 12
tCK(AVG)
Reserved
ns
1,2,3,4
CWL = 9,11 CL = 11
CL = 13
tCK(AVG)
1.25
