H5MS5162DFR-E3M

512Mbit MOBILE DDR SDRAM based on 8M x 4Bank x16 I/O Specification of 512Mb (32Mx16bit) Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 8,388,608 x16 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.3 / Apr. 2009 1 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series Document Title 512Mbit (4Bank x 8M x 16bits) MOBILE DDR SDRAM Revision History Revision No. 0.1 0.2 1.0 Initial Draft Update: IDD values Final Version -. Corrected max tDQSCK/tAC at DDR333 from 5.5ns to 5.0ns -. Corrected tDIPW, tIPW and tHZ at DDR400 (tDIPW: 1.8 to 1.4; tIPW: 2.7 to 2.2; tHZ: 5.5 to 5.0) -. Added the 200MHz product in ordering information -. Deleted the extended temperature products -. Change the ball height (page62) -. Insert DDR370 DC/AC Characteristics History Draft Date Sep.2007 Mar. 2008 Apr. 2008 Remark Preliminary Preliminary 1.1 May 2008 1.2 1.3 Jan. 2009 Apr. 2009 Rev 1.3 / Apr. 2009 2 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series FEATURES SUMMARY - Double data rate architecture: two data transfer per clock cycle Mobile DDR SDRAM INTERFACE CAS LATENCY TER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM) - Multiplexed Address (Row and Column address) SUPPLY VOLTAGE - 1.8V device: VDD and VDDQ = 1.7V to 1.95V MEMORY CELL ARRAY DATA STROBE AUTO REFRESH AND SELF REFRESH MODE CLOCK STOP MODE - Bidirectional, data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver - Data and data mask referenced to both edges of DQS LOW POWER FEATURES - AUTO TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength) - DPD (Deep Power Down): DPD is an optional feature, so please contact Hynix office for the DPD feature INPUT CLOCK - Differential clock inputs (CK, CK) Operating Temperature Data MASK - LDM and UDM: Input mask signals for write data - DM masks write data-in at the both rising and falling edges of the data strobe Rev 1.3 / Apr. 2009 ● ● ● ● - PASR (Partial Array Self Refresh) ● ● ● ● - x16 device: LDQS and UDQS ● ● ● ● - 512Mbit (x16 device) = 8M x 4Bank x 16 I/O ● - x16 bus width ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● Mobile DDR SDRAM MODE RERISTER SET, EXTENDED MODE REGIS- ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● - Programmable CAS latency 2 or 3 supported BURST LENGTH - Programmable burst length 2 / 4 / 8 with both sequential and interleave mode AUTO PRECHARGE - Option for each burst access - Clock stop mode is a feature supported by Mobile DDR SDRAM. - Keep to the JEDEC Standard regulation INITIALIZING THE MOBILE DDR SDRAM - Occurring at device power up or interruption of device power PACKAGE - 60 Ball, 0.8mm pitch FBGA, 8x10[mm2], t=1.0mm max, Lead & Halogen Free - Mobile Temp.: -30oC ~ 85oC 3 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series DESCRIPTION The Hynix H5MS5162DFR Series is 536,870,912-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile DDR SDRAM), ideally suited for mobile applications which use the battery such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, hand-held PCs. It is organized as 4banks of 8,388,608 x16. The HYNIX H5MS5162DFR series uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data per clock cycle at the I/O pins. The Hynix H5MS5162DFR Series offers fully synchronous operations referenced to both rising and falling edges of the clock. While all address and control inputs are latched on the rising edges of the CK (Mobile DDR SDRAM operates from a differential clock: the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK), data, data strobe and data mask inputs are sampled on both rising and falling edges of it (Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK). The data paths are internally pipelined and 2-bit prefetched to achieve high bandwidth. All input voltage levels are compatible with LVCMOS. Read and write accesses to the Low Power DDR SDRAM (Mobile DDR SDRAM) are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The Low Power DDR SDRAM (Mobile DDR SDRAM) provides for programmable read or write bursts of 2, 4 or 8 locations. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAM, the pipelined and multibank architecture of Low Power DDR SDRAM (Mobile DDR SDRAM) allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation times. The Low Power DDR SDRAM (Mobile DDR SDRAM) also provides for special programmable Self Refresh options which are Partial Array Self Refresh (full, half, quarter and 1/8 and 1/16 array) and Temperature Compensated Self Refresh. A burst of Read or Write cycles in progress can be interrupted and replaced by a new burst Read or Write command on any cycle (this pipelined design is not restricted by a 2N rule). Only Read bursts in progress with auto precharge disabled can be terminated by a burst terminate command. Burst Terminate command is undefined and should not be used for Read with Autoprecharge enabled and for Write bursts. Rev 1.3 / Apr. 2009 4 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series The Hynix H5MS5162DFR series has the special Low Power function of Auto TCSR (Temperature Compensated Self Refresh) to reduce self refresh current consumption. Since an internal temperature sensor is implemented, it enables to automatically adjust refresh rate according to temperature without external EMRS command. Deep Power Down Mode is an additional operating mode for Low Power DDR SDRAM (Mobile DDR SDRAM). This mode can achieve maximum power reduction by removing power to the memory array within Low Power DDR SDRAM (Mobile DDR SDRAM). By using this feature, the system can cut off almost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout flexibility. All inputs are LVCMOS compatible. Devices will have a VDD and VDDQ supply of 1.8V (nominal). The Hynix H5MS5162DFR series is available in the following package: - 60Ball FBGA [size: 8mm x 10mm, t=1.0mm max] 512M Mobile DDR SDRAM ORDERING INFORMATION Part Number H5MS5162DFR-E3M H5MS5162DFR-J3M H5MS5162DFR-K3M H5MS5162DFR-L3M Clock Frequency 200MHz(CL3) / 83MHz(CL2) 166MHz(CL3) / 83MHz(CL2) 133MHz(CL3) / 83MHz(CL2) 100MHz(CL3) / 66MHz(CL2) Mobile Temp. -30oC ~ 85oC Lead & Halogen Free Temperature Organization Interface Package 4banks x 8Mb x 16 LVCMOS Rev 1.3 / Apr. 2009 5 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series INFORMATION for Hynix KNOWN GOOD DIE With the advent of Multi-Chip package (MCP), Package on Package (PoP) and System in a Package (SiP) applications, customer demand for Known Good Die (KGD) has increased. Requirements for smaller form factors and higher memory densities are fueling the need for Wafer-level memory solutions due to their superior flexibility. Hynix Known Good Die (KGD) products can be used in packaging technologies such as systems-in-a-package (SIP) and multi-chip package (MCP) to reduce the board area required, making them ideal for hand-held PCs, and many other portable digital applications. Hynix Mobile SDRAM will be able to continue its constant effort of enabling the advanced package products of all application customers. - Please Contact Hynix Office for Hynix KGD product availability and informations. Rev 1.3 / Apr. 2009 6 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series 60Ball FBGA ASSIGNMENT 1 2 3 4 5 6 7 8 9 A B C D E F G H J K VSS DQ15 VSSQ VDDQ DQ1 DQ3 DQ5 DQ0 DQ2 DQ4 DQ6 VDD VSSQ VDDQ VSSQ VDDQ DQ13 DQ14 VSSQ DQ11 DQ12 VDDQ DQ9 DQ10 DQ8 NC /CK A12 A8 A5 VSSQ UDQS VSS CKE A9 A6 VSS UDM CK A11 A7 A4 Top view DQ7 NC /WE /CS A10 A2 LDQS VDDQ LDM /CAS BA0 A0 A3 VDD /RAS BA1 A1 VDD Rev 1.3 / Apr. 2009 7 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series Mobile DDR SDRAM PIN DESCRIPTION SYMBOL CK, CK TYPE INPUT DESCRIPTION Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for all functions except for SELF REFRESH EXIT, which is achieved asynchronously. Chip Select: CS enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. BA0 and BA1 also determine which mode register is to be loaded during a MODE REGISTER SET command (MRS, EMRS or SRR). Address inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. The address inputs also provide the op-code during a MODE REGISTER SET command. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. For 512Mb (x16), Row Address: A0 ~ A12, Column Address: A0 ~ A9 Auto-precharge flag: A10 Data Bus: data input / output pin Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled. HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Data Mask pins include dummy loading internally, to match the DQ and DQS loading. For x16 devices, LDM corresponds to the data on DQ0-DQ7, and UDM corresponds to the data on DQ8-DQ15. Data Strobe: Output with read data, input with write data. Edge-aligned with read data, center-aligned with write data. Used to capture write data. For x16 device, LDQS corresponds to the data on DQ0-DQ7, and UDQS corresponds to the data on DQ8-DQ15. Power supply Ground I/O Power supply I/O Ground No Connect: No internal electrical connection is present. CKE INPUT CS INPUT RAS, CAS, WE BA0, BA1 INPUT INPUT A0 ~ A12 INPUT DQ0 ~ DQ15 I/O LDM ~ UDM INPUT LDQS ~ UDQS I/O VDD VSS VDDQ VSSQ NC SUPPLY SUPPLY SUPPLY SUPPLY - Rev 1.3 / Apr. 2009 8 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series FUNCTIONAL BLOCK DIAGRAM 8Mbit x 4banks x 16 I/O Mobile DDR SDRAM PASR Extended Mode Register Self refresh logic & timer Write Data Register 2-bit Prefetch Unit 32 Input Buffer & Logic 16 Internal Row Counter CLK CLK Row Active CKE State Machine CS RAS CAS Column Active WE U/LDM Column Pre Decoder Row Pre Decoder 8Mx16 Bank3 DS 8Mx16 Bank2 Row decoders 8Mx16 Bank1 Row decoders 8Mx16 Bank0 Row decoders DQ0 Sense AMP & I/O Gate Output Buffer & Logic Row decoders Refresh Memory Cell Array 32 16 DQ15 Column decoders Bank Select Column Add Counter A0 A1 Address Buffers Address Register Burst Length LDQS , UDQS Burst Counter CAS Latency Data Strobe Transmitter DS Data Strobe Receiver Data Out Control A12 BA1 BA0 Mode Register Rev 1.3 / Apr. 2009 9 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series REGISTER DEFINITION I Mode Register Set (MRS) for Mobile DDR SDRAM BA1 0 BA0 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 A5 CAS Latency A4 A3 BT A2 A1 Burst Length A0 Burst Type A3 0 1 Burst Type Sequential Interleave CAS Latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved Burst Length Burst Length A3 = 0 Reserved 2 4 8 Reserved Reserved Reserved Reserved A3=1 Reserved 2 4 8 Reserved Reserved Reserved Reserved A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Rev 1.3 / Apr. 2009 10 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series REGISTER DEFINITION II Extended Mode Register Set (EMRS) for Mobile DDR SDRAM BA1 1 BA0 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 A6 DS A5 A4 0 A3 0 A2 A1 PASR A0 DS (Drive Strength) A7 0 0 0 0 1 A6 0 0 1 1 0 A5 0 1 0 1 0 Drive Strength Full Half (Default) Quarter Octant Three-Quarters PASR (Partial Array Self Refresh) A2 0 0 0 0 1 1 A1 0 0 1 1 0 0 A0 0 1 0 1 0 1 Self Refresh Coverage All Banks (Default) Half of Total Bank (BA1=0) Quarter of Total Bank (BA1=BA0=0) Reserved Reserved One Eighth of Total Bank (BA1 = BA0 = Row Address MSB=0) One Sixteenth of Total Bank (BA1 = BA0 = Row Address 2 MSBs=0) Reserved 1 1 1 1 0 1 Rev 1.3 / Apr. 2009 11 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series REGISTER DEFINITION III Status Register (SR) for Mobile DDR SDRAM BA1 0 BA0 1 A12 0 A11 0 A10 0 A9 0 A8 0 DQ8 A7 0 DQ7 A6 0 DQ6 A5 0 DQ5 A4 0 DQ4 A3 0 DQ3 A2 0 DQ2 A1 0 DQ1 A0 0 DQ0 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 Density 0 1 0 0 DW 0 X Refresh Rate X X Revision Identification X1) X1) X1) X1) Manufacturers Identification 0 1 1 0 Refresh Rate DW (Device Width) DQ11 Device Width 0 1 16 bits 32 bits DQ10 DQ9 0 0 0 1 1 1 1 DQ15 DQ14 DQ13 Density 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 128 256 512 1024 Reserved Reserved Reserved Reserved x x x x 0 1 1 0 0 1 1 DQ8 Refresh Rate x 0 1 0 1 0 1 42) 4 2 1 0.5 0.25 0.253) Density Manufacturers Identification DQ3 0 DQ2 1 DQ1 1 DQ0 0 Manufacturer Hynix Reserved or other companies Note) 1. The revision number starts at ‘0000’ and increments by ‘0001’ each time a change in the manufacturer’s specification, IBIS, or process occurs. 2. Low temperature out of range. 3. High temperature out of range - no refresh rate can guarantee functionality. 4. The refresh rate multiplier is based on the memory’s temperature sensor. 5. Required average periodic refresh interval = tREFI * multiplier. 6. Status Register is only for Read. 7. To read out Status Register values, BA[1:0] set to 01b and A[12:0] set to all 0 with MRS command followed by Read command with that BA[1:0] are Don’t care and A[12:0] set to all 0. Rev 1.3 / Apr. 2009 12 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series COMMAND TRUTH TABLE Function DESELECT (NOP) NO OPERATION (NOP) ACTIVE (Select Bank and activate Row) READ (Select bank and column and start read burst) READ with AP (Read Burst with Autoprecharge) WRITE (Select bank and column and start write burst) WRITE with AP (Write Burst with Autoprecharge) BURST TERMINATE or enter DEEP POWER DOWN PRECHARGE (Deactivate Row in selected bank) PRECHARGE ALL (Deactivate rows in all Banks) AUTO REFRESH or enter SELF REFRESH MODE REGISTER SET CS H L L L L L L L L L L L RAS X H L H H H H H L L L L CAS X H H L L L L H H H L L WE X H H H H L L L L L H L BA X X V V V V V X V X X V A10/AP ADDR Note X X Row L H L H X L H X Op code X X Row Col Col Col Col X X X X 3 4, 5 6 6 7,8,9 10 3 2 2 DM TRUTH TABLE Function Write Enable Write Inhibit DM L H DQ Valid X Note 11 11 Note: 1. All states and sequences not shown are illegal or reserved. 2. DESLECT and NOP are functionally interchangeable. 3. Autoprecharge is non-persistent. A10 High enables Autoprecharge, while A10 Low disables Autoprecharge 4. Burst Terminate applies to only Read bursts with auto precharge disabled. This command is undefined and should not be used for Read with Autoprecharge enabled, and for Write bursts. 5. This command is BURST TERMINATE if CKE is High and DEEP POWER DOWN entry if CKE is Low. 6. If A10 is low, bank address determines which bank is to be precharged. If A10 is high, all banks are precharged and BA0-BA1 are don't care. 7. This command is AUTO REFRESH if CKE is High, and SELF REFRESH if CKE is low. 8. All address inputs and I/O are ''don't care'' except for CKE. Internal refresh counters control Bank and Row addressing. 9. All banks must be precharged before issuing an AUTO-REFRESH or SELF REFRESH command. 10. BA0 and BA1 value select among MRS, EMRS and SRR. 11. Used to mask write data, provided coincident with the corresponding data. 12. CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN. Rev 1.3 / Apr. 2009 13 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series CKE TRUTH TABLE CKEn-1 L L L L L L H CKEn L L L H H H L Current State Power Down Self Refresh Deep Power Down Power Down Self Refresh Deep Power Down All Banks Idle COMMANDn ACTIONn Note X X X NOP or DESELECT NOP or DESELECT NOP or DESELECT NOP or DESELECT Maintain Power Down Maintain Self Refresh Maintain Deep Power Down Exit Power Down Exit Self Refresh Exit Deep Power Down Precharge Power Down Entry Active Power Down Entry Self Refresh entry Enter Deep Power Down 5,6,9 5,7,10 5,8 5 H H H H L L L H Bank(s) Active All Banks Idle All Banks Idle NOP or DESELECT AUTO REFRESH BURST TERMINATE See the other Truth Tables 5 Note: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of LP DDR immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is the result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. DESELECT and NOP are functionally interchangeable. 6. Power Down exit time (tXP) should elapse before a command other than NOP or DESELECT is issued. 7. SELF REFRESH exit time (tXSR) should elapse before a command other than NOP or DESELECT is issued. 8. The Deep Power-Down exit procedure must be followed as discussed in the Deep Power-Down section of the Functional Description. 9. The clock must toggle at least one time during the tXP period. 10. The clock must toggle at least once during the tXSR time. Rev 1.3 / Apr. 2009 14 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series CURRENT STATE BANKn TRUTH TABLE (COMMAND TO BANK n) Command Current State CS H Any L L L Idle L L L Row Active L L L Read (without Auto recharge) L L L L Write (without Auto precharge) L L L L H H L H H L H H H L L H L L H L L H H L L H L H H L L H L L L H L L MODE REGISTER SET PRECHARGE READ WRITE PRECHARGE READ WRITE PRECHARGE BURST TERMINATE READ WRITE PRECHARGE Mode register set No action if bank is idle Select Column & start read burst Select Column & start write burst Deactivate Row in bank (or banks) Truncate Read & start new Read burst Truncate Read & start new Write burst Truncate Read, start Precharge Burst terminate Truncate Write & start new Read burst Truncate Write & start new Write burst Truncate Write, start Precharge 11 5,6,12 5,6 12 4 5,6 5,6,13 10 H L L H H L H H H NOP ACTIVE AUTO REFRESH Continue previous Operation Select and activate row Auto refresh 10 RAS X CAS X WE X Description DESELECT (NOP) Continue previous Operation Action Notes Note: 1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh or Power Down. 2. DESELECT and NOP are functionally interchangeable. 3. All states and sequences not shown are illegal or reserved. 4. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging. 5. A command other than NOP should not be issued to the same bank while a READ or WRITE Burst with auto precharge is enabled. 6. The new Read or Write command could be auto precharge enabled or auto precharge disabled. Rev 1.3 / Apr. 2009 15 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series 7. Current State Definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. Write: a WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. 8. The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table3, and according to Truth Table 4. Precharging: Starts with the registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the ''row active'' state. Read with AP Enabled: Starts with the registration of the READ command with AUTO PRECHARGE enabled and ends when tRP has been met. Once tRP has been met, the bank will be in the idle state. Write with AP Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 9. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied to each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC is met. Once tRFC is met, the LP DDR will be in an ''all banks idle'' state. Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once tMRD is met, the LP DDR will be in an ''all banks idle'' state. Precharging All: Starts with the registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. 10. Not bank-specific; requires that all banks are idle and no bursts are in progress. 11. Not bank-specific. BURST TERMINATE affects the most recent READ burst, regardless of bank. 12. Requires appropriate DM masking. 13. A WRITE command may be applied after the completion of the READ burst; otherwise, a Burst terminate must be used to end the READ prior to asserting a WRITE command. Rev 1.3 / Apr. 2009 16 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series CURRENT STATE BANKn TRUTH TABLE (COMMAND TO BANK m) Command Current State CS H Any L Idle X L Row Activating, Active, or Precharging L L L L Read with Auto Precharge disabled L L L L Write with Auto precharge disabled L L L L Read with Auto Precharge L L L L Write with Auto precharge L L L H X L H H L L H H L L H H L L H H L L H H L H X H L L H H L L H H L L H H L L H H L L H H X H H L L H H L L H H L L H H L L H H L L NOP ANY ACTIVE READ WRITE PRECHARGE ACTIVE READ WRITE PRECHARGE ACTIVE READ WRITE PRECHARGE ACTIVE READ WRITE PRECHARGE ACTIVE READ WRITE PRECHARGE Continue previous Operation Any command allowed to bank m Activate Row Start READ burst Start WRITE burst Precharge Activate Row Start READ burst Start WRITE burst Precharge Activate Row Start READ burst Start WRITE burst Precharge Activate Row Start READ burst Start WRITE burst Precharge Activate Row Start READ burst Start WRITE burst Precharge 5,8 5,8 5,8 5,8,10 8,9 8 8 8,10 8 8 RAS X CAS X WE X Description DESELECT (NOP) Continue previous Operation Action Notes Rev 1.3 / Apr. 2009 17 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series Note: 1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh or Power Down. 2. DESELECT and NOP are functionally interchangeable. 3. All states and sequences not shown are illegal or reserved. 4. Current State Definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. Write: a WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. 5. Read with AP enabled and Write with AP enabled: The read with Autoprecharge enabled or Write with Autoprecharge enabled states can be broken into two parts: the access period and the precharge period. For Read with AP, the precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all the data in the burst. For Write with Auto precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period, of the Read with Autoprecharge enabled or Write with Autoprecharge enabled states, ACTIVE, PRECHARGE, READ, and WRITE commands to the other bank may be applied; during the access period, only ACTIVE and PRECHARGE commands to the other banks may be applied. In either case, all other related limitations apply (e.g. contention between READ data and WRITE data must be avoided). 6. AUTO REFRESH, SELF REFRESH, and MODE REGISTER SET commands may only be issued when all bank are idle. 7. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 8. READs or WRITEs listed in the Command column include READs and WRITEs with AUTO PRECHARGE enabled and READs and WRITEs with AUTO PRECHARGE disabled. 9. Requires appropriate DM masking. 10. A WRITE command may be applied after the completion of data output, otherwise a BURST TERMINATE command must be issued to end the READ prior to asserting a WRITE command. Rev 1.3 / Apr. 2009 18 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series ABSOLUTE MAXIMUM RATING Parameter Operating Case Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Short Circuit Output Current Power Dissipation Symbol TC TSTG VIN, VOUT VDD VDDQ IOS PD Rating -30 ~ 85 -55 ~ 150 -0.3 ~ VDDQ+0.3 -0.3 ~ 2.7 -0.3 ~ 2.7 50 0.7 Unit o o C C V V V mA W AC and DC OPERATING CONDITIONS OPERATING CONDITION Parameter Supply Voltage I/O Supply Voltage Operating Case Temperature Symbol VDD VDDQ TC Min 1.7 1.7 -30 Typ 1.8 1.8 Max 1.95 1.95 85 Unit V V oC Note 1 1 CLOCK INPUTS (CK, CK) Parameter DC Input Voltage DC Input Differential Voltage AC Input Differential Voltage AC Differential Crosspoint Voltage Symbol VIN VID(DC) VID(AC) VIX Min -0.3 0.4*VDDQ 0.6*VDDQ 0.4*VDDQ Max VDDQ+0.3 VDDQ+0.6 VDDQ+0.6 0.6*VDDQ Unit V V V V Note 2 2 3 Address And Command Inputs (A0~An, BA0, BA1, CKE, CS, RAS, CAS, WE) Parameter Input High Voltage Input Low Voltage Symbol VIH VIL Min 0.8*VDDQ -0.3 Max VDDQ+0.3 0.2*VDDQ Unit V V Note Data Inputs (DQ, DM, DQS) Parameter DC Input High Voltage DC Input Low Voltage AC Input High Voltage AC Input Low Voltage Symbol VIHD(DC) VILD(DC) VIHD(AC) VILD(AC) Min 0.7*VDDQ -0.3 0.8*VDDQ -0.3 Max VDDQ+0.3 0.3*VDDQ VDDQ+0.3 0.2*VDDQ Unit V V V V Note Data Outputs (DQ, DQS) Parameter DC Output High Voltage (IOH = -0.1mA) DC Output Low Voltage (IOL = 0.1mA) Symbol VOH VOL Min 0.9*VDDQ Max 0.1*VDDQ Unit V V Note Rev 1.3 / Apr. 2009 19 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series Leakage Current Parameter Input Leakage Current Output Leakage Current Symbol ILI ILO Min -1 -1.5 Max 1 1.5 Unit uA uA Note 4 5 Note: 1. All voltages are referenced to VSS = 0V and VSSQ must be same potential and VDDQ must not exceed the level of VDD. 2. VID(DC) and VID(AC) are the magnitude of the difference between the input level on CK and the input level on CK. 3. The value of VIX is expected to be 0.5*VDDQ and must track variations in the DC level of the same. 4. VIN = 0 to 1.8V. All other pins are not tested under VIN=0V. 5. DOUT is disabled. VOUT= 0 to 1.95V. AC OPERATING TEST CONDITION Parameter AC Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise/Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Symbol VIH / VIL Vtrip tR / tF Voutref CL Value 0.8*VDDQ/0.2*VDDQ 0.5*VDDQ 1 0.5*VDDQ Unit V V ns V pF Note 1 Note: 1. The circuit shown on the right represents the timing load used in defining the relevant timing parameters of the part. It is not intended to be either a precise repreZO=50 sentation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools Test Load for Full Drive Strength Buffer to correlate the timing reference load to system environ(20 pF) ment. Manufacturers will correlate to their production (generally a coaxial transmission line terminated at the Test Load for Half Drive Strength Buffer (10 pF) tester electronics). For the half strength driver with a nominal 10pF load parameters tAC and tQH are expected to be in the same range. However, these parameters are not subject to production test but are estimated by design and characterization. Use of IBIS or other simulation tools for system design validation is suggested. Input / Output Capacitance Parameter Input capacitance, CK, CK Input capacitance delta, CK, CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS Input/output capacitance delta, DQ, DM, DQS Symbol CCK CDCK CI CDI CIO CDIO Speed Min 1.5 1.5 2.0 Max 3.5 0.25 3.0 0.5 4.5 0.5 Unit pF pF pF pF pF pF Note Note: 1. These values are guaranteed by design and are tested on a sample base only. 2. These capacitance values are for single monolithic devices only. Multiple die packages will have parallel capacitive loads. 3. Input capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. VDD, VDDQ are applied and all other pins (except the pin under test) floating. DQ's should be in high impedance state. This may be achieved by pulling CKE to low level. 4. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is required to match signal propagation times of DQ, DQS and DM in the system. Rev 1.3 / Apr. 2009 20 tuptuO 4 4 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series Mobile DDR OUTPUT SLEW RATE CHARACTERRISTICS Parameter Pull-up and Pull-Down Slew Rate for Full Strength Driver Pull-up and Pull-Down Slew Rate for Half Strength Driver Output Slew Rate Matching ratio (Pull-up to Pull-down) Min 0.7 0.3 0.7 Max 2.5 1.0 1.4 Unit V/ns V/ns Note 1, 2 1, 2 3 Note: 1. Measured with a test load of 20pF connected to VSSQ 2. Output slew rate for rising edge is measured between VILD(DC) to VIHD(AC) and for falling edge between VIHD(DC) to VILD(AC) 3. The ratio of pull-up slew rate to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. Mobile DDR AC OVERSHOOT / UNDERSHOOT SPECIFICATION Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between overshoot signal and VDD must be less than or equal to The area between undershoot signal and GND must be less than or equal to Note: 1. This specification is intended for devices with no clamp protection and is guaranteed by design. Specification 0.5V 0.5V 3V-ns 3V-ns 2.5V 2.0V Overshoot VDD Voltage (V) 1.5V 1.0V Max. Amplitude = 0.5V Max. Area = 3V-ns 0.5V 0.0V Undershoot -0.5V VSS Time (ns) Rev 1.3 / Apr. 2009 21 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series DC CHARACTERISTICS Max Parameter Symbol Test Condition tRC = tRC(min); tCK = tCK(min); CKE is HIGH; CS is HIGH between valid commands; address inputs are SWITCHING; data bus inputs are STABLE all banks idle; CKE is LOW; CS is HIGH; tCK = tCK(min); address and control inputs are SWITCHING; data bus inputs are STABLE DDR DDR DDR DDR DDR Unit Note 400 370 333 266 200 60 55 50 45 45 mA 1 Operating one bank active-precharge current IDD0 Precharge power-down standby current Precharge power-down standby current with clock stop Precharge non powerdown standby current Precharge non powerdownstandby current with clock stop Active power-down standby current Active power-down standby current with clock stop Active non power-down standby current Active non power-down standby current with clock stop Operating burst read current IDD2P 0.3 mA all banks idle; CKE is LOW; CS is HIGH;CK = IDD2PS LOW; CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE IDD2N all banks idle; CKE is HIGH; CS is HIGH, tCK = tCK(min); address and control inputs are SWITCHING; data bus inputs are STABLE 0.3 mA 12 mA all banks idle; CKE is HIGH; CS is HIGH; CK = IDD2NS LOW; CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE IDD3P one bank active; CKE is LOW; CS is HIGH; tCK = tCK(min); address and control inputs are SWITCHING; data bus inputs are STABLE 8 5 mA one bank active; CKE is LOW; CS is HIGH; CK IDD3PS = LOW; CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE IDD3N one bank active; CKE is HIGH; CS is HIGH; tCK = tCK(min); address and control inputs are SWITCHING; data bus inputs are STABLE 3 15 mA one bank active; CKE is HIGH; CS is HIGH; CK IDD3NS = LOW; CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active; BL=4; CL=3; tCK = tCK(min); continuous read bursts; IOUT=0mA; address 110 inputs are SWITCHING, 50% data change each burst transfer 10 mA IDD4R 100 90 80 80 mA 1 Operating burst write current one bank active; BL=4; tCK=tCK(min); continuous write bursts; address inputs are IDD4W SWITCHING; 50% data change each burst transfer IDD5 tRC=tRFC(min); tCK=tCK(min); burst refresh; CKE is HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE CKE is LOW; CK=LOW; CK=HIGH; Extended Mode Register set to all 0's; address and control inputs are STABLE; data bus inputs are STABLE Address, control and data bus inputs are STABLE 100 95 90 80 80 mA Auto Refresh Current 100 mA Self Refresh Current IDD6 See Next Page uA 2 Deep Power Down Current IDD8 10 uA 4 Rev 1.3 / Apr. 2009 22 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series Note: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is 1V/ns 3. Definitions for IDD: LOW is defined as VIN ≤ 0.1 * VDDQ HIGH is defined as VIN ≥ 0.9 * VDDQ STABLE is defined as inputs stable at a HIGH or LOW level SWITCHING is defined as - address and command: inputs changing between HIGH and LOW once per two clock cycles - data bus inputs: DQ changing between HIGH and LOW once per clock cycle DM and DQS are STABLE 4. Please contact Hynix office for more information and ability for DPD operation. Deep Power Down operation is a hynix optional function. 5. IDD values are for full operating range of voltage and temperature. VDD, VDDQ = 1.7V ~ 1.95V. Temperature = -30oC ~ +85oC DC CHARACTERISTICS - IDD6 Temp. (oC) 45 85 Memory Array 4 Banks 250 500 2 Banks 220 400 1 Bank 200 300 Unit uA uA Note: 1. Related numerical values in this 45oC are examples for reference sample value only. 2. With a on-chip temperature sensor, auto temperature compensated self refresh will automatically adjust the interval of self-refresh operation according to case temperature variations. Rev 1.3 / Apr. 2009 23 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series AC CHARACTERISTICS (AC operating conditions unless otherwise noted) (Sheet 1 of 2) DDR400 DDR370 DDR333 DDR266 DDR200 Parameter DQ Output Access Time (from CK, CK) Symbol Min Max Min Max Min Max Min Max Min Max tAC 2.0 2.0 5.0 5.0 2.0 2.0 5.0 5.0 2.0 2.0 5.0 5.0 2.5 2.5 6.0 6.0 2.5 2.5 7.0 7.0 ns ns Unit Note DQS Output Access Time (from CK, CK) tDQSCK Clock High-level Width Clock Low-level Width Clock Half Period Cycle CL = 3 CL = 2 tCH tCL tHP tCK3 tCK2 tDS tDH tDIPW tIS tIH tIPW tLZ tHZ tDQSQ tQH tQHS 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK tCL, tCH (Min) 5.0 12 0.48 0.48 1.4 0.9 0.9 2.2 1 tHP tQHS 5.0 0.4 0.5 tCL, tCH (Min) 5.4 12 0.54 0.54 1.6 1.0 1.0 2.2 1.0 tHP tQHS 5.0 0.5 0.5 tCL, tCH (Min) 6.0 12 0.6 0.6 1.6 1.1 1.1 2.2 1.0 tHP tQHS 5.0 0.5 0.65 tCL, tCH (Min) 7.5 12 0.8 0.8 1.6 1.3 1.3 2.6 1.0 tHP tQHS 6.0 0.6 0.75 tCL, tCH (Min) 10 15 1.1 1.1 2.2 1.5 1.5 3.0 1.0 tHP tQHS 7.0 0.7 1.0 ns 1,2 System Time Clock ns 3 ns ns 4,5,6 ns 4,5,6 ns 7 DQ and DM Input Setup Time DQ and DM Input Hold Time DQ and DM Input Pulse Width Address and Control Input Setup Time Address and Control Input Hold Time Address and Control Input Pulse Width DQ & DQS Low-impedance time from CK, CK DQ & DQS High-impedance time from CK, CK DQS - DQ Skew DQ / DQS output hold time from DQS Data Hold Skew Factor ns 6,8,9 ns 6,8,9 ns ns 7 10 10 11 2 2 ns ns ns ns Write Command to 1st DQS Latching tDQSS Transition DQS Input High-Level Width DQS Input Low-Level Width DQS Falling Edge of CK Setup Time DQS Falling Edge Hold Time from CK tDQSH tDQSL tDSS tDSH 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK 0.4 0.4 0.2 0.2 0.4 0.4 0.2 0.2 0.4 0.4 0.2 0.2 0.4 0.4 0.2 0.2 0.4 0.4 0.2 0.2 tCK tCK tCK tCK Rev 1.3 / Apr. 2009 24 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series AC CHARACTERISTICS (AC operating conditions unless otherwise noted) (Sheet 2 of 2) DDR400 Parameter MODE REGISTER SET Command Period MRS(SRR) to Read Command Period Minimum Time between Status Register Read to Next Valid Command Write Preamble Setup Time Write Postamble Write Preamble CL = 3 Read Preamble CL = 2 Read Postamble ACTIVE to PRECHARGE Command Period ACTIVE to ACTIVE Command Period AUTO REFRESH to ACTIVE/AUTO REFRESH Command Period ACTIVE to READ or WRITE Delay PRECHARGE Command Period ACTIVE Bank A to ACTIVE Bank B Delay WRITE Recovery Time Auto Precharge Write Recovery + Precharge Time Internal Write to Read Command Delay Self Refresh Exit to next valid Command Delay Exit Power Down to next valid Command Delay CKE min. Pulse Width(High and Low) Average Periodic Refresh Interval Refresh Period Rev 1.3 / Apr. 2009 DDR370 DDR333 DDR266 DDR200 Unit Note Symbol Min Max Min Max Min Max Min Max Min Max tMRD tSRR tSRC tWPRES tWPST 2 2 CL+1 0 0.4 0.6 1.1 1.1 0.6 70,0 00 2 2 CL+1 0 0.4 0.25 0.9 0.5 0.4 42 58.2 72 16.2 16.2 10.8 15 0.6 1.1 1.1 0.6 70,0 00 2 2 CL+1 0 0.4 0.25 0.9 0.5 0.4 42 60 72 18 18 12 15 0.6 1.1 1.1 0.6 70,0 00 2 2 CL+1 0 0.4 0.25 0.9 0.5 0.4 45 75 72 22.5 22.5 15 15 0.6 1.1 1.1 0.6 70,0 00 2 2 CL+1 0 0.4 0.25 0.9 0.5 0.4 50 80 72 30 30 15 15 0.6 1.1 1.1 0.6 70,0 00 - tCK tCK tCK ns tCK tCK tCK tCK tCK ns ns ns ns ns ns ns 16 15 15 14 14 12 13 tWPRE 0.25 tRPRE tRPRE tRPST tRAS tRC tRFC tRCD tRP tRRD tWR tDAL tWTR tXSR tXP tCKE tREFI tREF 1 120 tIS + 2CLK 1 0.9 0.5 0.4 40 55 72 15 15 10 15 (tWR/tCK) + (tRP/tCK) 7.8 64 1 120 tIS + 1CLK 1 7.8 64 1 120 tIS + 1CLK 1 7.8 64 1 120 tIS + 1CLK 1 7.8 64 1 120 tIS + 1CLK 1 7.8 64 tCK ns ns tCK us ms 25 17 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series Note: 1. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH) 2. tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH). tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 3. The only time that the clock frequency is allowed to change is during clock stop, power-down or self-refresh modes. 4. The transition time for DQ, DM and DQS inputs is measured between VIL(DC) to VIH(AC) for rising input signals, and VIH(DC) to VIL(AC) for falling input signals. 5. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. 6. Input slew rate ≥ 1.0 V/ns. 7. These parameters guarantee device timing but they are not necessarily tested on each device. 8. The transition time for address and command inputs is measured between VIH and VIL. 9. A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter. 10. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 11. tDQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 12. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 13. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 14. A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the system. It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled). 15. Speed bin (CL-tRCD-tRP) = 3-3-3 16. Minimum 3CLK of tDAL(= tWR+tRP) is required because it need minimum 2CLK for tWR and minimum 1CLK for tRP. tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms above, if not already an integer, round to the next higher integer. 17. A maximum of eight Refresh commands can be posted to any given Low Power DDR SDRAM (Mobile DDR SDRAM), meaning that the maximum absolute interval between any Refresh command and the next Refresh command is 8*tREFI. 18. All AC parameters are guaranteed by full range of operating voltage and temperature. VDD, VDDQ = 1.7V ~ 1.95V. Temperature = -30oC ~ +85oC. Rev 1.3 / Apr. 2009 26 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series Mobile DDR SDRAM OPERATION State Diagram Power applied POWER ON DPDSX DEEP POWER DOWN ACT : Active B ST : B urst CKEL : E nter Pow er-Dow n PCG. ALL BANKS DPDS SELF REFRESH CKEH : E xit Pow er-Dow n DPDS : E nter Deep Pow er-Dow n READ (E)MRS SET MRS, EMRS REFS REFSX SRR IDLE ALL BANK PCG. REFA SRR DPDSX : E xit Deep Pow erDow nEM R S E M RS : E xt. M ode Reg. Set READ CKEL PCG. POWER DOWN CKEH ACT AUTO REFRESH MRS : M ode Register Set PR E : Precharge ACTIVE POWER DOWN CKEH CKEL BURST STOP PR EALL : Precharge All B anks R EFA : Auto R efresh R EFS : E nter Self R efresh ROW ACTIVE READ BST WRITE WRITE WRITE WRITEA READA READ READ READ R EFSX : E xit Self Refresh R EAD : R ead w /o Auto Precharge WRITEA READA WRITE A PRE PRE PRE READA READ A R EAD A : R ead w ith Auto Precharge W R ITE : W rite w /o Auto Precharge W R ITEA : W rite w ith Auto Precharge COMMAND Input AUTOMATIC Sequence Precharge ALL SR R : Status R egister R ead Rev 1.3 / Apr. 2009 27 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series DESELECT The DESELECT function (CS = High) prevents new commands from being executed by the Mobile DDR SDRAM. The Mobile DDR SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION The NO OPERATION (NOP) command is used to perform a NOP to a Mobile DDR SDRAM that is selected (CS = Low). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. (see to next figure) ACTIVE The Active command is used to activate a row in a particular bank for a subsequent Read or Write access. The value of the BA0,BA1 inputs selects the bank, and the address provided on A0-A12 (or the highest address bit) selects the row. (see to next figure) Before any READ or WRITE commands can be issued to a bank within the Mobile DDR SDRAM, a row in that bank must be opened. This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. The row remains active until a PRECHARGE (or READ with AUTO PRECHARGE or WRITE with AUTO PRECHARGE) command is issued to the bank. A PRECHARGE (or READ with AUTO PRECHARGE or WRITE with AUTO PRECHARGE) command must be issued before opening a different row in the same bank. CLK CLK CKE (High) CLK CLK CKE (High) CS CS RAS RAS CAS CAS WE WE A0~A12 A0~A12 Row Address RA BA0,BA1 Don't Care BA0, BA1 Bank Address BA Don't Care NOP Command ACTIVE Command Rev 1.3 / Apr. 2009 28 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series Once a row is Open (with an ACTIVE command) a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been closed (precharge). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. /CLK CLK Com m and Bank A ACT W rite A W ith A/P Bank B ACT Bank A ACT NOP NOP N OP NOP NOP Address Bank A Row tRCD Bank A Col Bank B Row Bank A Row tRRD tRC D on't C are Once a row is Open(w ith an ACTIVE com m and) a READ or W RITE com m and m ay be issued to that row , subject to the tRCD specification. tRCD (M IN) should be divided by the clock period and rounded up to the next w hole num ber to determ ine the earliest clock edge after the ACTIVE com m and on which a READ or W RITE com m and can be entered . Rev 1.3 / Apr. 2009 29 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series READ / WRITE COMMAND The READ command is used to initiate a Burst Read to an active row. The value of BA0 and BA1 selects the bank and address inputs select the starting column location. The value of A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent access. The valid data-out elements will be available CAS latency after the READ command is issued. The Mobile DDR drives the DQS during read operations. The initial low state of the DQS is known as the read preamble and the last data-out element is coincident with the read postamble. DQS is edge-aligned with read data. Upon completion of a burst, assuming no new READ commands have been initiated, the I/O's will go high-Z. The WRITE command is used to initiate a Burst Write access to an active row. The value of BA0, BA1 selects the bank and address inputs select the starting column location. The value of A10 determines whether or not auto precharge is used.If auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent access. Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data will be written to the memory; if the DM signal is registered high, the corresponding data-inputs will be ignored, and a write will not be executed to that byte/column location. The memory controller drives the DQS during write operations. The initial low state of the DQS is known as the write preamble and the low state following the last data-in element is write postamble. Upon completion of a burst, assuming no new commands have been initiated, the I/O's will stay high-Z and any additional input data will be ignored. CLK CLK CKE (High) CLK CLK CKE (High) CS CS RAS RAS CAS CAS WE WE A0~A9 CA A0~A9 High to enable Auto Precharge A10 Low to disable Auto Precharge BA0, BA1 CA A10 BA0, BA1 BA BA Read Com m and Don't Care W rite Com m and READ / WRITE COMMAND Rev 1.3 / Apr. 2009 30 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series READ The basic Read timing parameters for DQ are shown next figure (Basic Read Timing Parameters). They apply to all Read operations. During Read bursts, DQS is driven by the Mobile DDR SDRAM along with the output data. The initial Low state of the DQS is known as the read preamble; the Low state coincident with last data-out element is known as the read postamble. tCK /C LK CLK tCK tC H tC L tA C m a x DQS tR PRE tD Q SC K tD Q SC K t RPST tD Q SQ m ax tA C DQ tLZ tD Q SC K tR PR E D on tQ H tD Q SC K tRPST tQ H tH Z D o n+ 1 D o n+ 2 D o n + 3 tQ H tA C m in DQS tD Q S Q m ax tA C DQ tLZ D on tQ H tH Z D o n+ 1 D o n+ 2 D o n+ 3 tQ H D o n 't C a re 1) D o n : D a ta O ut from co lu m n n 2) All D Q are vaild tA C after th e C K edge All D Q are vaild tD Q SQ after th e D Q S edge, regardless of tA C Basic Read Timing Parameters Rev 1.3 / Apr. 2009 31 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series The first data-out element is edge aligned with the first rising edge of DQS and the successive data-out elements are edge aligned to successive edges of DQS. This is shown in next figure with a CAS latency of 2 and 3. Upon completion of a read burst, assuming no other READ command has been initiated, the DQ will go to High-Z. /CLK CLK Command READ NOP NOP NOP NOP NOP Address BA, Col n CL =2 DQS DQ CL =3 DQS Do n DQ Do n Don't Care 1) 2) 3) 4) Do n : D ata out from column n BA, Col n = B ank A, Column n Burst Length = 4; 3 subseqnent elements of Data Out appear in the programmed order following Do n Shown with nominal tAC, tDQSCK and tDQSQ Read Burst Showing CAS Latency Rev 1.3 / Apr. 2009 32 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series READ to READ Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the new burst follows either the last element of a completed burst or the last desired element of a longer burst that is being truncated. The new READ command should be issued X cycles after the first READ command, where X equals the number of desired data-out element pairs (pairs are required by the 2n prefetch architecture). /C LK C LK Co m m an d REA D NOP R EA D NOP NOP NOP A ddress BA , C ol n CL =2 BA , C ol b DQS DQ CL =3 DQS Don Dob DQ Don D ob D on't C are 1) 2) 3) 4) 5) D o n ( or b ): D ata out from colum n n (or colum n b) BA , C ol n ( b) = B ank A , C olum n n (b) Burst Length = 4 or 8 (if 4 , the bursts are concatenated; if 8, the second burst interrupts the first) R ead bursts are to an active row in any bank Show n w ith nom inal tA C, tD Q SC K and tD Q SQ Consecutive Read Bursts A READ command can be initiated on any clock cycle following a previous READ command. Non-consecutive Reads are shown in the first figure of next page. Random read accesses within a page or pages can be performed as shown in second figure of next page. Rev 1.3 / Apr. 2009 33 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series /C L K C LK Com m and READ NOP NOP READ NOP NOP A d d re ss BA, Col n CL =2 BA, Col b DQS DQ CL =3 DQS D on Dob DQ Don D o n 't C a r e 1) 2) 3) 4) D o n ( o r b ) : D a t a o u t fr o m c o lu m n n ( o r c o lu m n b ) B A , C o l n ( b ) = B a n k A , C o lu m n n ( b ) B u r s t L e n g t h = 4 ; 3 s u b s e q u e n t e le m e n t s o f D a t a O u t a p p e a r in th e p r o g r a m m e d o r d e r fo llo w in g D o n ( b ) S h o w n w it h n o m in a l t A C , t D Q S C K a n d t D Q S Q Non-Consecutive Read Bursts /C L K CLK Com m and READ READ READ READ NOP NOP A d d re ss BA, Col n CL =2 BA, Col x BA, Col b BA, Col g DQS DQ CL =3 DQS D on Don' D ox D ox' D ob Dob' D og D og' DQ Don Don' D ox D ox' D o n 't C a r e Dob Dob' 1 ) D o n , e t c : D a t a o u t f r o m c o lu m n n , e t c n ', x ', e t c : D a t a O u t e le m e n t s , a c c o d in g t o t h e p r o g r a m m d b u r s t o r d e r 2 ) B A , C o l n = B a n k A , C o lu m n n 3 ) B u r s t L e n g t h = 2 , 4 o r 8 in c a s e s s h o w n ( i f b u r s t o f 4 o r 8 , t h e b u r s t is in t e r r u p t e d ) 4 ) R e a d a r e t o a c t i v e r o w s in a n y b a n k s Random Read Bursts Rev 1.3 / Apr. 2009 34 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series READ BURST TERMINATE Data from any READ burst may be truncated with a BURST TERMINATE command. The BURST TERMINATE latency is equal to the read (CAS) latency, i.e., the BURST TERMINATE command should be issued X cycles after the READ command where X equals the desired data-out element pairs. /CLK CLK Com m and R EAD BUR ST NOP NOP NOP NOP Address BA, Col n CL = 2 DQS DQ CL = 3 DQS DQ D on't Care 1) 2) 3) 4) D o n : D ata out from colum n n BA, Col n = B ank A, Colum n n Cases show n are bursts of 4 or 8 term inated after 2 data elem ents Show n w ith nom inal tAC, tD Q SCK and tD Q SQ Terminating a Read Burst Rev 1.3 / Apr. 2009 35 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series READ to WRITE Data from READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in next fig. for the case of nominal tDQSS. /CLK CLK Com m and READ BST NOP W R ITE NOP NOP Address BA, Col n CL = 2 BA, Col b tD QSS DQS DQ D on DI b Com m and READ BST NOP NOP W RITE NOP Address BA, Col n BA, Col b CL = 3 DQS DQ D on DI b DM Don't Care 1) D O n = D ata O ut from colum n n; D I b = D ata In to colum n b 2) Burst length = 4 or 8 in the cases show n; if the burst length is 2, the BST com m and can be om m itted 3) Show n w ith nom inal tAC, tD Q SCK and tD QSQ Read to Write Rev 1.3 / Apr. 2009 36 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series READ to PRECHARGE A Read burst may be followed by or truncated with a PRECHARGE command to the same bank (provided Auto Precharge was not activated). The PRECHARGE command should be issued X cycles after the READ command, where X equal the number of desired data-out element pairs. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data-out elements.In the case of a Read being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from Read burst with Auto Precharge enabled. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to truncate bursts. /CLK CLK Command READ NOP PRE NOP NOP ACT Address BA, Col n CL =2 Bank ( A or All) tRP BA, Row DQS DQ CL =3 DQS Do n DQ Do n Don't Care 1) 2) 3) 4) 5) 6) DO n = D ata Out from column n Cases shown are either uninterrupted burst of 4, or interrupted bursts of 8 Shown with nominal tAC, tDQSCK and tDQSQ Precharge may be applied at (BL / 2) tCK after the READ command. Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks. The ACTIVE command may be applied if tRC has been met. READ to PRECHARGE Rev 1.3 / Apr. 2009 37 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series Write Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered Low, the corresponding data will be written to the memory; if the DM signal is registered High, the corresponding data inputs will be ignored, and a write will not be executed to that byte / column location. Basic Write timing parameters for DQ are shown in Figure; they apply to all Write operations. tC K /C LK C LK Case 1: tD Q SS = m in DQS tD Q SS tC H tC L tD SH tD Q SH tD SH tW PST tW PR ES tW PRE tD S tD H tD Q SL DQ, DM Case 2: tD Q SS = m ax DQS tD Q SS DI n tD Q SH tD SS tD SS tW PST tW PR ES tW PRE DQ, DM tD S tD H tD Q SL DI n D o n 't C a re 1) D I n: D ata in for colum n n 2) 3 subseq uent elem ents of D ata in are ap p lied in the p rog ram m ed ord er follow ing D I n 3) tD Q SS : each rising edg e of D Q S m ust fall w ithin the + /-25 (p ercentage) w ind ow of the corresp onding positive clock edg e Basic Write Timing Parameters During Write bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and the subsequent data elements will be registered on successive edges of DQS. The Low state of DQS between the WRITE command and the first rising edge is called the write preamble, and the Low state on DQS following the last data-in element is called the write postamble. The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range - from 75% to 125% of a clock cycle. Next fig. shows the two extremes of tDQSS for a burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain high-Z and any additional input data will be ignored. Rev 1.3 / Apr. 2009 38 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series /CLK CLK Com m and W RITE NOP NO P NO P NO P NOP Address BA, Col b tD QSS min DQS DQ DM tDQSS m ax DQS DQ DM Don't Care 1) 2) 3) 4) DI b = Data In to colum n b 3 subsequent elem ents of Data In are applied in the program m ed order following DI b A non-interrupted burst of 4 is shown A10 is low with the W RITE com m and (Auto Precharge is disabled) Write Burst (min. and max. tDQSS) Rev 1.3 / Apr. 2009 39 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series WRITE to WRITE Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data, can be maintained. The new WRITE command can be issued on any positive edge of the clock following the previous WRITE command.The first data-in element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new WRITE command should be issued X cycles after the first WRITE command, where X equals the number of desired data-in element pairs. /CLK CLK Command WRITE NOP WRITE NOP NOP NOP Address BA, Col b tDQSS min BA, Col n DQS DQ DI DI b n DM tDQSS max DQS DQ DI DI b n DM Don't Care 1) DI b (n ) = Data In to column b (column n) 2) 3 subsequent elements of Data In are applied in the programmed order following DI b. 3 subsequent elements of Data In are applied in the programmed order following DI n. 3) Non-interrupted bursts of 4 are shown. 4) Each WRITE command may be to any active bank Concatenated Write Bursts Rev 1.3 / Apr. 2009 40 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series /C LK CLK C om m a n d W R IT E NOP NOP W R IT E NOP NOP A d d ress BA, Col b tD Q S S m a x BA, Col n DQS DQ DI b DI n DM D on 't C a re 1 ) D I b ( n ) = D a ta In to co lu m n b 2 ) 3 su b se q u e n t e le m e n ts o f D a ta 3 su b se q u e n t e le m e n ts o f D a ta 3 ) N o n -in te rru p te d b u rsts o f 4 a re 4 ) E a ch W R IT E co m m a n d m a y b e (o r co lu m n n ). In a re a p p lie d in th e p ro g ra m m e d o rd e r fo llo w in g D I b . In a re a p p lie d in th e p ro g ra m m e d o rd e r fo llo w in g D I n . sh o w n . to a n y a ctive b a n k a n d m a y b e to th e sa m e o r d iffe re n t d e v ice s . Non-Concatenated Write Bursts /C LK C LK C om m and W R IT E W R IT E W R IT E W R IT E W R IT E NOP A d d ress BA, C ol b BA, C ol x tD Q SS m ax BA, C ol n BA , C ol a BA, C ol g DQS DQ Di Di Di Di Di Di Di Di b b' x x' n n' a a' DM D on't C are 1 ) D I b etc. = D a ta In to colum n b, e tc. ; b', etc. = th e next D ata In fo llo w in g D I b, etc. a cco rding to the program m ed burst order 2 ) Pro gram m ed burst length = 2, 4 or 8 in cases show n. If burst of 4 or 8, burst w ould be truncate d. 3 ) Each W R IT E co m m and m ay be to an y active ban k an d m ay be to the sam e o r diffe rent devices. Random Write Cycles Rev 1.3 / Apr. 2009 41 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series WRITE to READ Data for any Write burst may be followed by a subsequent READ command. To follow a Write without truncating the write burst, tWTR should be met as shown in Figure. /CLK CLK Command WRITE NOP NOP NOP READ NOP NOP Address BA, Col b tDQSSmax tWTR BA, Col n CL=3 DQS DQ Di b DM Don't Care 1) DI b = Data In to column b . 3 subsequent elements of Data In are applied in the programmed order following DI b. 2) A non-interrupted burst of 4 is shown. 3) tWTR is referenced from the positive clock edge after the last Data In pair. 4) A10 is LOW with the WRITE command (Auto Precharge is disabled) 5) The READ and WRITE commands are to the same device but not necessarily to the same bank. Data for any Write burst may be truncated by a subsequent READ command as shown in Figure. Note that the only data-in pairs that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in must be masked with DM. Rev 1.3 / Apr. 2009 42 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series /CLK CLK Command WRITE NOP NOP READ NOP NOP NOP Address BA, Col b tDQSSmax tWTR BA, Col n CL=3 DQS DQ DI b Don DM Don't Care 1) DI b = Data In to column b. DO n = Data Out from column n. 2) An interrupted burst of 4 is shown, 2 data elements are written. 3 subsequent elements of Data In are applied in the programmed order following DI b. 3) tWTR is referenced from the positive clock edge after the last Data In pair. 4) A10 is LOW with the WRITE command (Auto Precharge is disabled) 5) The READ and WRITE commands are to the same device but not necessarily to the same bank. Interrupting Write to Read Rev 1.3 / Apr. 2009 43 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series WRITE to PRECHARGE Data for any WRITE burst may be followed by a subsequent PRECHARGE command to the same bank (provided Auto Precharge was not activated). To follow a WRITE without truncating the WRITE burst, tWR should be met as shown in Fig. /CLK CLK Command WRITE NOP NOP NOP NOP PRE Address BA, Col b tDQSS max tWR BA (A or All) DQS DQ DI b DM Don't Care 1) DI b (n) = Data In to column b (column n) 3 subsequent elements of Data In are applied in the programmed order following DI b. 2) A non-interrupted bursts of 4 are shown. 3) tWR is referenced from the positive clock edge after the last Data In pair. 4) A10 is LOW with the WRITE command (Auto Precharge is disabled) Non-Interrupting Write to Precharge Rev 1.3 / Apr. 2009 44 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series Data for any WRITE burst may be truncated by a subsequent PRECHARGE command as shown in Figure. Note that only data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data-in should be masked with DM, as shown in next Fig. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. /CLK CLK Command WRITE NOP NOP NOP PRE NOP Address BA, Col b tDQSSmax tWR 2 BA (A or All) DQS DQ DI b DM 1) 2) 3) 4) 5) 6) DI b = Data In to column b . An interrupted burst of 4 or 8 is shown, 2 data elements are written. tWR is referenced from the positive clock edge after the last desired Data In pair. A10 is LOW with the WRITE command (Auto Precharge is disabled) *1 = can be Don't Care for programmed burst length of 4 *2 = for programmed burst length of 4, DQS becomes Don't Care at this point Interrupting Write to Precharge Rev 1.3 / Apr. 2009 * * * * * 1 1 1 1 Don't Care 45 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series BURST TERMINATE The BURST TERMINATE command is used to truncate read bursts (with auto precharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this datasheet. Note the BURST TERMINATE command is not bank specific. This command should not be used to terminate write bursts. CLK CLK CKE (High) CS RAS CAS WE A0~A12 BA0,BA1 Don't Care BURST TERMINATE COMMAND Rev 1.3 / Apr. 2009 46 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. Another command to the same bank (or banks) being precharged must not be issued until the precharge time (tRP) is completed. If one bank is to be precharged, the particular bank address needs to be specified. If all banks are to be precharged, A10 should be set high along with the PRECHARGE command. If A10 is high, BA0 and BA1 are ignored. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging. CLK CLK CKE (High) A10 defines the precharge m when a precharge ode com and, a read com and m m or a write com and is m issued. If A10 = High when a precharge com and is m issued, all banks are precharged. If A10 = Low when a precharge com and is m issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = High when read or write com and, autom precharge function is enabled. W A10 = Low, autohile precharge function is disabled. Don't Care CS RAS CAS W E A0~A9, A11, A12 A10 BA0,BA1 Bank Address BA PRECHARGE command AUTO PRECHARGE Auto Precharge is a feature which performs the same individual bank precharge function as described above, but without requiring an explicit command. This is accomplished by using A10 (A10=high), to enable auto precharge in conjunction with a specific Read or Write command. This precharges the bank/row after the Read or Write burst is complete. Auto precharge is non persistent, so it should be enabled with a Read or Write command each time auto precharge is desired. Auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. Rev 1.3 / Apr. 2009 47 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series AUTO REFRESH AND SELF REFRESH Mobile DDR devices require a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of two ways: by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode: AUTO REFRESH. This command is used during normal operation of the Mobile DDR. It is non persistent, so must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller.The Mobile DDR requires AUTO REFRESH commands at an average periodic interval of tREFI. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given Mobile DDR, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8*tREFI. Rev 1.3 / Apr. 2009 - -SELF REFRESH. This state retains data in the Mobile DDR, even if the rest of the system is powered down (even without external clocking). Note refresh interval timing while in Self Refresh mode is scheduled internally in the Mobile DDR and may vary and may not meet tREFI time. ''Don't Care'' except CKE, which must remain low. An internal refresh cycle is scheduled on Self Refresh entry. The procedure for exiting Self Refresh mode requires a series of commands. First clock must be stable before CKE going high. NOP commands should be issued for the duration of the refresh exit time (tXSR), because time is required for the completion of any internal refresh in progress. The use of SELF REFRESH mode introduces the possibility that an internally timed event can be missed when CKE is raised for exit from self refresh mode. Upon exit from SELF REFRESH an extra AUTO REFRESH command is recommended. In the self refresh mode, two additional power-saving options exist. They are Temperature Compensated Self Refresh and Partial Array Self Refresh and are described in the Extended Mode Register section. The Self Refresh command is used to retain cell data in the Mobile SDRAM. In the Self Refresh mode, the Mobile SDRAM operates refresh cycle asynchronously. The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled (Low). The Mobile DDR can accomplish an special Self Refresh operation by the specific modes (PASR) programmed in extended mode registers. The Mobile DDR can control the refresh rate automatically by the temperature value of Auto TCSR (Temperature Compensated Self Refresh) to reduce self refresh current and select the memory array to be refreshed by the value of PASR (Partial Array Self Refresh). The Mobile DDR can reduce the self refresh current(IDD6) by using these two modes. 48 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series CLK CLK CKE (High) CLK CLK CKE CS CS RAS RAS CAS CAS WE WE A0~A12 A0~A12 BA0,BA1 BA0, BA1 Don't Care Auto Refresh Command Self Refresh Command Rev 1.3 / Apr. 2009 49 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series /CLK CLK tRP tRFC tXSR tRFC CKE Command PRE NOP ARF NOP NOP NOP ARF NOP ACT Address BA A Row n A10(AP) Pre All High-Z Row n DQ Enter Self Refresh Mode Exit Self Refresh Mode Any Command (Auto Refresh Recommended) Cont't Care SELF REFRESH ENTRY AND EXIT Rev 1.3 / Apr. 2009 50 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series MODE REGISTER SET The Mode Register and the Extended Mode Register are loaded via the address bits. BA0 and BA1 are used to select among the Mode Register, the Extended Mode Register and Status Register. See the Mode Register description in the register definition section. The MODE REGISTER SET command can only be issued when all banks are idle and no bursts are in progress, and a subsequent executable command cannot be issued until tMRD is met. CLK CLK CKE (H igh ) CS RAS CAS WE A 0 ~ A 12 C ode C ode D o n 't C a re B A 0 ,B A 1 MODE REGISTER SET COMMAND /CLK CLK Command MRS NOP tMRD Valid Address Code Valid Don't Care Code = Mode Register / Extended Mode Register selection (BA0, BA1) and op-code (A0 - An) tMRD DEFINITION Rev 1.3 / Apr. 2009 51 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series Mode Register The mode register contains the specific mode of operation of the Mobile DDR SDRAM. This register includes the selection of a burst length(2, 4 or 8), a cas latency(2 or 3), a burst type. The mode register set must be done before any activate command after the power up sequence. Any contents of the mode register be altered by re-programming the mode register through the execution of mode register set command. 0 1 2 3 4 5 6 CLK CLK CM D Precharge All Bank Mode Register Set Comm and (any) tCK tRP 2 CLK m in Mode Register Set BURST LENGTH Read and write accesses to the Mobile DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Page10. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. BURST TYPE Accesses within a given burst may be programmed to be either sequential or interleaved. CAS LATENCY The CAS latency is the delay between the registration of a READ command and the availability of the first piece of output data. If a READ command is registered at a clock edge n and the latency is 3 clocks, the first data element will be valid at n + 2tCK + tAC. If a READ command is registered at a clock edge n and the latency is 2 clocks, the first data element will be valid at n + tCK + tAC. Rev 1.3 / Apr. 2009 52 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series Extended Mode Register The Extended Mode Register contains the specific features of self refresh operation of the Mobile DDR SDRAM. The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA1=1 and BA0=0) and will retain the stored information until it is reprogrammed, the device is put in Deep Power-Down mode, or the device loses power. The Extended Mode Register should be loaded when all Banks are idle and no bursts are in progress, and subsequent operation should only be initiated after tMRD. Violating these requirements will result in unspecified operation. The Extended Mode Register is written by asserting low on CS, RAS, CAS, WE and high on BA0. The state of address pins A0 ~ A12 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation. This register includes the selection of partial array to be refreshed (full array, half array, quarter array, etc.). The extended mode register set must be done before any activate command after the power up sequence. Any contents of the mode register be altered by re-programming the mode register through the execution of extended mode register set command. PARTIAL ARRAY SELF REFRESH (PASR) With PASR, the self refresh may be restricted to a variable portion of the total array. The whole array (default), 1/2 array, 1/4 array, 1/8 array or 1/16 array could be selected. DRIVE STRENGTH (DS) The drive strength could be set to full or half via address bits A5, A6 and A7. The half drive strength is intended for lighter loads or point-to-point environments. Rev 1.3 / Apr. 2009 53 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series Status Register Read The Status Register contains the specific die information such as density, device type, data bus width, refresh rate, revision ID and manufacturers. The Status Register is only for READ. Below figure is Status Register Read Timing Diagram. To read out the Status Register values, BA[1:0] set to 01b and A[12:0] set to all 0 with MRS command followed by Read command with that BA[1:0] are Don’t care and A[12:0] set to all 0. tCK tRP tSRR tSRC CLK CLK CMD PRE All or PRE CMD NOP MRS NOP READ NOP NOP NOP CMD BA[1:0] 01 Add 0 0 CL = 3 DQS DQ[15:0] Register Value Out Don t care ’ ’ ’ ’ Note) 1. SRR can only be issued after power-up sequence is complete. 2. SRR can only be issued with all banks precharged. 3. SRR CL is unchanged from value in the mode register. 4. SRR BL is fixed at 2. 5. tSRR = 2 CLK (min) 6. tSRC = CL + 1. (min time between READ to next valid command) 7. No commands other than NOP and DESELECT are allowed between the SRR and the READ. Rev 1.3 / Apr. 2009 54 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series POWER DOWN Power down occurs if CKE is set low coincident with Device Deselect or NOP command and when no accesses are in progress. If power down occurs when all banks are idle, it is Precharge Power Down. If Power down occurs when one or more banks are Active, it is referred to as Active power down. The device cannot stay in this mode for longer than the refresh requirements of the device, without losing data. The power down state is exited by setting CKE high while issuing a Device Deselect or NOP command. A valid command can be issued after tXP. For Clock stop during power down mode, please refer to the Clock Stop subsection in Operation section of this datasheet. NOTE: This case shows CKE low coincident with NO OPERATION. Alternately POWER DOWN entry can be achieved with CKE low coincident with Device DESELECT. DEEP POWER DOWN The Deep Power Down (DPD) mode enables very low standby currents. All internal voltage generators inside the Mobile DDR SDRAM are stopped and all memory data is lost in this mode. All the information in the Mode Register and the Extended Mode Register is lost. Next Figure, DEEP POWER DOWN COMMAND shows the DEEP POWER DOWN command All banks must be in idle state with no activity on the data bus prior to entering the DPD mode. While in this state, CKE must be held in a constant low state. To exit the DPD mode, CKE is taken high after the clock is stable and NOP command must be maintained for at least 200 us. After 200 us a complete re-initialization routing is required following steps 4 through 11 as defined in POWERUP and INITIALIZATION SEQUENCES. CLK CLK CKE CLK CLK CKE CS CS RAS RAS CAS CAS WE WE A0~A12 A0~A12 BA0,BA1 Don't Care BA0, BA1 Don't Care POWER-DOWN ENTRY COMMAND DEEP POWER DOWN ENTRY COMMAND Rev 1.3 / Apr. 2009 55 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series Mobile DDR SDRAM Deep Power Down Entry and Exit Before entering deep power down the DRAM must be in an all banks idle state with no activity on the data bus. Upon entering deep power down all data will be lost. While in deep power down CKE must be held in a constant low state. Upon exiting deep power down NOP command must be maintained for 200us. After 200us a complete initialization routine is required following steps 4 through 11 as defined in POWER-UP and INITIALIZATION SEQUENCES. T0 CK CK CKE tIS tIS tCH tIH tIH tIS tCL T1 Ta01 Ta1 Tb1 tCK tIS COM NOP DPD4 NOP VALID5 tIS tIH ADD VALID DQS DQ DM tRP2 T=200us3 Deep Power Down Mode Exit Deep Power Down Mode DON'T CARE Mobile DDR SDRAM Deep Power-Down Entry and Exit Note: 1. Clock must be stable before exiting deep power down mode. That is, the clock must be cycling within specifications by Ta0. 2. Device must be in the all banks idle state prior to entering Deep Power Down mode. 3. 200us is required before any command can be applied upon exiting DPD. 4. DPD = Deep Power Down command. 5. Upon exiting Deep Power Down a precharge all command must be issued followed by two auto refresh commands and a load mode register sequence. Rev 1.3 / Apr. 2009 56 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series CAS LATENCY DEFINITION CAS latency definition of Mobile DDR SDRAM must be must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. CAS latency definition: with CL = 3 the first data element is valid at (2 * tCK + tAC) after the clock at which the READ command was registered (See Figure 2) T0 T1 T2 T2n T3 T3n T4 T4n T5 T5n T6 CK CK CMD Read NOP NOP NOP NOP NOP NOP CL = 3 tDQSCK tLZ tDQSCK tRPST tRPRE tDQSQ DQS All DQ values, collectively2 tAC tLZ T2 T2n T3 T3n T4 T4n T5 T5n CAS LATENCY DEFINITION NOTE 1. DQ transitioning after DQS transition define tDQSQ window. 2. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC. 3. tAC is the DQ output window relative to CK, and is the long term component of DQ skew. Rev 1.3 / Apr. 2009 57 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series Clock Stop Mode Clock stop mode is a feature supported by Mobile DDR SDRAM devices. It reduces clock-related power consumption during idle periods of the device. Conditions: the Mobile DDR SDRAM supports clock stop in case: The last access command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has executed to completion, including any data-out during read bursts; the number of required clock pulses per access command depends on the device's AC timing parameters and the clock frequency; The related timing condition (tRCD, tWR, tRP, tRFC, tMRD) has been met; CKE is held HIGH. When all conditions have been met, the device is either in ''idle'' or ''row active'' state, and clock stop mode may be entered with CK held LOW and CK held HIGH. Clock stop mode is exited when the clock is restarted. NOPs command have to be issued for at least one clock cycle before the next access command may be applied. Additional clock pulses might be required depending on the system characteristics. Figure1 illustrates the clock stop mode: Initially the device is in clock stop mode; The clock is restarted with the rising edge of T0 and a NOP on the command inputs; With T1 a valid access command is latched; this command is followed by NOP commands in order to allow for clock stop as soon as this access command has completed; Tn is the last clock pulse required by the access command latched with T1. The timing condition of this access command is met with the completion of Tn; therefore Tn is the last clock pulse required by this command and the clock is then stopped. ● ● ● ● ● ● ● ● CK T0 T1 T2 Tn CK CKE Timing Condition CM D NOP CMD NOP NOP NOP ADD Valid (High-Z) Clock Stopped Exit Clock Stop Mode Valid Command Enter Clock Stop Mode Don't Care DQ, DQS Clock Stop Mode Rev 1.3 / Apr. 2009 58 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series Data mask1,2) Mobile DDR SDRAM uses a DQ write mask enable signal (DM) which masks write data. Data masking is only available in the write cycle for Mobile DDR SDRAM. Data masking is available during write, but data masking during read is not available. DM command masks burst write data with reference to data strobe signal and it is not related with read data. DM command can be initiated at both the rising edge and the falling edge of the DQS. DM latency for write operation is zero. For x16 data I/O, Mobile DDR SDRAM is equipped with LDM and UDM which control DQ0~DQ7 and DQ8~DQ15 respectively. Note: 1) Mobile SDR SDRAM can mask both read and write data, but the read mask is not supported by Mobile DDR SDRAM. 2) Differences in Functions and Specifications (next table) Item Data mask Mobile DDR SDRAM Write mask only Mobile SDR SDRAM Write mask/Read mask CK CK CMD WRITE tDQSS tDS tDH WRITE DM DQS Hi-Z tDQSL tDQSH Hi-Z DQ D0 D1 Data Masking D3 D0 D1 Data Masking D3 Data Masking (Write cycle: BL=4) Rev 1.3 / Apr. 2009 59 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series POWER-UP AND INITIALIZATION SEQUENCES Mobile DDR SDRAM must be powered up and initialized in a predefined manner. Operations procedures other thank those specified may result in undefined operation. If there is any interruption to the device power, the initialization routine should be followed. The steps to be followed for device initialization are listed below. Step1: Provide power, the device core power (VDD) and the device I/O power (VDDQ) must be brought up simultaneously to prevent device latch-up. Although not required, it is recommended that VDD and VDDQ are from the same power source. Also assert and hold CLOCK ENABLE (CKE) to a LVCMOS logic high level. Step 2: Once the system has established consistent device power and CKE is driven high, it is safe to apply stable clock. Step 3: There must be at least 200us of valid clocks before any command may be given to the DRAM. During this time NOP or DESELECT commands must be issued on the command bus. Step 4: Issue a PRECHARGE ALL command. Step 5: Provide NOPs or DESELECT commands for at least tRP time. Step 6: Issue an AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time. Issue the second AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time. Note as part of the initialization sequence there must be two auto refresh commands issued. The typical flow is to issue them at Step 6, but they may also be issued between steps 10 and 11. Step 7: Using the MRS command, load the base mode register. Set the desired operating modes. Step 8: Provide NOPs or DESELECT commands for at least tMRD time. Step 9: Using the MRS command, program the extended mode register for the desired operating modes. Note the order of the base and extended mode register programming is not important. Step 10: Provide NOP or DESELCT commands for at least tMRD time. Step 11: The DRAM has been properly initialized and is ready for any valid command. Rev 1.3 / Apr. 2009 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● 60 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series The Initialization flow sequence is below. VDD VDDQ T=200usec tCK tRP tRFC tRFC tMRD tMRD /CLK CLK tCH tCL CKE CMD NOP PRE ARF ARF MRS tIS tIH MRS ACT ADDR ALL BANKS CODE tIS tIH CODE RA A10 tIS tIH CODE tIS tIH CODE RA BA0, BA1 DM DQ, DQS VDD/VDDQ Powered up CLOCK stable High-Z BA0=L BA1=L BA0=L BA1=H BA Precharge All Auto Refresh Auto Refresh Load Mode Register Load Extended Mode Register DON'T CARE Initialization Waveform Sequence Rev 1.3 / Apr. 2009 61 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series PACKAGE INFORMATION 60 Ball 0.8mm pitch 8mm FBGA [8.0 x 10.0 mm2, t=1.0mm max] 8.00Typ. 3.20 1.60 0.8 A1 INDEX MARK Unit [mm] 0.80 Typ. 10.00 Typ. Bottom VIEW 0.40 0.450 +/- 0.05 1.40 1.375 0.80 Typ. 0.350 +/-0.05 1.00 max Rev 1.3 / Apr. 2009 62