H5PS5162FFR-20L

H5PS5162FFR 512Mb(32Mx16) DDR2 SDRAM H5PS5162FFR This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.4/Aug. 2008 1 1H5PS5162FFR Revision History Revision 0.1 0.2 0.3 67 58 56 56 56 56 Page History Initial Graphics Version Release divided IDD Table into 4 columns inserted part numbering code ‘C’ at the end of Part number in order to divide the product, which is the same speed but low power, into the normar power one. Added IDD Values Corrected the definition of rising & falling slew rate Insert the thermal characteristics table. Corrected the thermal characteristics value. Input/Output leakage current rating inserted. Operating temperature condition changed. Date Nov. 2007 Nov. 2007 Nov. 2007 Remark Preliminary Preliminary Preliminary 1.0 1.1 1.2 1.3 1.4 Jan. 2008 Feb. 2008 Mar. 2008 Aug. 2008 Aug. 2008 Note) The H5PS5162FFR data sheet follows all of JEDEC DDR2 standard. Rev. 1.4/Aug. 2008 2 1H5PS5162FFR Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Key Feaures 1.1.2 Ordering Information 1.2 32Mx16 DDR2 Pin Configuration 1.3 Pin Description 2. Functioanal Description 2.1 Simplified State Diagram 2.2 Functional Block Diagram(32M X16) 2.3 Basic Function & Operation of DDR2 SDRAM 2.3.1 Power up and Initialization 2.3.2 Programming the Mode and Extended Mode Registers 2.3.2.1 DDR2 SDRAM Mode Register Set(MRS) 2.3.2.2 DDR2 SDRAM Extended Mode Register Set 2.3.2.3 Off-Chip Driver(OCD) Impedance Adjustment 2.3.2.4 ODT(On Die Termination) 2.4 Bank Activate Command 2.5 Read and Write Command 2.5.1 Posted CAS 2.5.2 Burst Mode Operation 2.5.3 Burst Read Command 2.5.4 Burst Write Operation 2.5.5 Write Data Mask 2.6 Precharge Operation 2.7 Auto Precharge Operation 2.8 Refresh Commands 2.8.1 Auto Refresh Command 2.8.2 Self Refresh Command 2.9 Power Down 2.10 Asynchronous CKE Low Event 2.11 No Operation Command 2.12 Deselect Command 3.1 Command Truth Table 3.2 Clock Enable(CKE) Truth Table for Synchronous Transistors 3.3 Data Mask Truth Table 4.1 Absolute Maximum DC Ratings 4.2 Operating Temperature Condition 4.3 Thermal Characteristics 3. Truth Tables 4. Operating Conditions Rev. 1.4/Aug. 2008 3 1H5PS5162FFR 5. AC & DC Operating Conditions 5.1 DC Operation Conditions 5.1.1 Recommended DC Operating Conditions(SSTL_1.8) 5.1.2 ODT DC Electrical Characteristics 5.2 DC & AC Logic Input Levels 5.2.1 Input DC Logic Level 5.2.2 Input AC Logic Level 5.2.3 AC Input Test Conditions 5.2.4 Differential Input AC Logic Level 5.2.5 Differential AC output parameters 5.2.6 Overshoot / Undershoot Specification 5.3 Output Buffer Levels 5.3.1 Output AC Test Conditions 5.3.2 Output DC Current Drive 5.3.3 OCD default chracteristics 5.4 Default Output V-I Characteristics 5.4.1 Full Strength Default Pulldown Driver Characteristics 5.4.2 Full Strength Default Pullup Driver Chracteristics 5.4.3 Calibrated Output Driver V-I Characteristics 5.5 Input/Output Capacitance 6. IDD Specifications & Measurement Conditions 7. AC Timing Specifications 7.1 Timing Parameters by Speed Grade 7.2 General Notes for all AC Parameters 7.3 Specific Notes for dedicated AC parameters. 8. Package Dimension(x16) Rev. 1.4/Aug. 2008 4 1H5PS5162FFR 1. Description 1.1 Device Features & Ordering Information 1.1.1 Key Features • • • • • • • • • • • • • • • • • • • • • • • • • • VDD/VDDQ= 2.0V +/- 0.1V(600/500 MHz) VDD/VDDQ= 1.8V +/- 0.1V(500/400 MHz) All inputs and outputs are compatible with SSTL_18 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) Differential Data Strobe (DQS, DQS) Data outputs on DQS, DQS edges when read (edged DQ) Data inputs on DQS centers when write(centered DQ) On chip DLL align DQ, DQS and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable CAS latency from 3 to 7 supported Programmable additive latency 0, 1, 2, 3, 4, 5 and 6 supported Programmable burst length 4/8 with both nibble sequential and interleave mode Internal four bank operations with single pulsed RAS Auto refresh and self refresh supported tRAS lockout supported 8K refresh cycles /64ms JEDEC standard 84ball FBGA(x16) Full strength driver option controlled by EMRS On Die Termination supported Off Chip Driver Impedance Adjustment supported Self-Refresh High Temperature Entry High Temperature Self Refresh rate supported Average Refresh Period 7.8us at lower than Tcase 85°C, 3.9us at 85°C