H5PS5162FFR-C

H5PS5162FFR Series 512Mb DDR2 SDRAM H5PS5162FFR-xxC Series H5PS5162FFR-xxL Series H5PS5162FFR-xxI Series This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Jul. 2008 1 Release H5PS5162FFR series Revision History Rev. 0.1 1.0 History Preliminary Release Draft Date Jan. 2008 Jul. 2008 Rev. 1.0 / July. 2008 2 Release H5PS5162FFR series Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Key Features 1.1.2 Ordering Information 1.1.3 Ordering Frequency 1.2 Pin configuration 1.3 Pin Description 2. Maximum DC ratings 2.1 Absolute Maximum DC Ratings 2.2 Operating Temperature Condition 3. AC & DC Operating Conditions 3.1 DC Operating Conditions 5.1.1 Recommended DC Operating Conditions(SSTL_1.8) 5.1.2 ODT DC Electrical Characteristics 3.2 DC & AC Logic Input Levels 3.2.1 Input DC Logic Level 3.2.2 Input AC Logic Level 3.2.3 AC Input Test Conditions 3.2.4 Differential Input AC Logic Level 3.2.5 Differential AC output parameters 3.3 Output Buffer Levels 3.3.1 Output AC Test Conditions 3.3.2 Output DC Current Drive 3.3.3 OCD default characteristics 3.4 IDD Specifications & Measurement Conditions 3.5 Input/Output Capacitance 4. AC Timing Specifications 5. Package Dimensions Rev. 1.0 / July. 2008 3 Release H5PS5162FFR series 1. Description 1.1 Device Features & Ordering Information 1.1.1 Key Features • VDD ,VDDQ =1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) • Differential Data Strobe (DQS, DQS) • Data outputs on DQS, DQS edges when read (edged DQ) • Data inputs on DQS centers when write(centered DQ) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM mask write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 3, 4, 5 and 6 supported • Programmable additive latency 0, 1, 2, 3, 4 and 5 supported • Programmable burst length 4 / 8 with both nibble sequential and interleave mode • Internal four bank operations with single pulsed RAS • Auto refresh and self refresh supported • tRAS lockout supported • 8K refresh cycles /64ms • JEDEC standard 84ball FBGA(x16) : 8mm x 13mm • Full strength driver option controlled by EMRS • On Die Termination supported • Off Chip Driver Impedance Adjustment supported • Self-Refresh High Temperature Entry • Partial Array Self Refresh support Ordering Information Part No. Organization Package Operating Frequency Speed Bin E3 C4 Y5 S5 S6 tCK(ns) 5 3.75 3 2.5 2.5 CL 3 4 5 5 6 tRCD 3 4 5 5 6 tRP 3 4 5 5 6 Unit Clk Clk Clk Clk Clk H5PS5162FFR**-XX* 32Mx16 Lead & Halogen free** Note: 1. -XX* is the speed bin, refer to the Operation Frequency table for complete Part No. 2. Hynix Halogen-free products are compliant to RoHS. Hynix supports Lead & Halogen free parts for each speed grade with same specification, except Lead free materials. We'll add "R" character after "F" for Lead & Halogen free products. 3. H5PS5162FFR-XXC is commertial temp. and normal power 4. H5PS5162FFR-XXL is commertial temp. and low power 5. H5PS5162FFR-XXI is Industrial temp. and normal power Rev. 1.0 / July. 2008 4 Release H5PS5162FFR series 1.2 Pin Configuration & Address Table 32Mx16 DDR2 PIN CONFIGURATION(Top view: see balls through package) 3 VSS UDM VDDQ DQ11 VSS LDM VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC A B C D E F G H J K L M N P R 7 VSSQ UDQS VDDQ DQ10 VSSQ LDQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC 8 UDQS VSSQ DQ8 VSSQ LDQS VSSQ DQ0 VSSQ CK CK CS A0 A4 A8 NC VSS VDD 9 VDDQ DQ15 VDDQ DQ13 VDDQ DQ7 VDDQ DQ5 VDD ODT 1 VDD DQ14 VDDQ DQ12 VDD DQ6 VDDQ DQ4 VDDL 2 NC VSSQ DQ9 VSSQ NC VSSQ DQ1 VSSQ VREF CKE NC BA0 A10 VSS A3 A7 VDD A12 ROW AND COLUMN ADDRESS TABLE ITEMS # of Bank Bank Address Auto Precharge Flag Row Address Column Address Page size 32Mx16 4 BA0, BA1 A10/AP A0 - A12 A0-A9 2 KB Rev. 1.0 / July. 2008 5 Release H5PS5162FFR series 1.3 PIN DESCRIPTION PIN TYPE DESCRIPTION Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. Chip Select : All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. On Die Termination Control : ODT(registered HIGH) enables on die termination resistance internal to the DDR2 SDRAM. For x16 configuration ODT is applied to each DQ, UDQS/UDQS.LDQS/LDQS, UDM and LDM signal. The ODT pin will be ignored if the Extended Mode Register(EMRS(1)) is programmed to disable ODT. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask : DM is an input mask signal for write data. Input Data is masked when DM is sampled High coincident with that input data during a WRITE access. DM is sampled on both edges of DQS, Although DM pins are input only, the DM loading matches the DQ and DQS loading. Bank Address Inputs: BA0 - BA1 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0BA1. The address inputs also provide the op code during MODE REGISTER SET commands. Data input / output : Bi-directional data bus CK, CK Input CKE Input CS Input ODT Input RAS, CAS, WE Input DM (LDM, UDM) Input BA0 - BA1 Input A0 -A12 Input DQ Input/ Output Rev. 1.0 / July. 2008 6 Release H5PS5162FFR series -ContinuePIN TYPE DESCRIPTION Data Strobe : Output with read data, input with write data. Edge aligned with read data, centered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS corresponds to the data on DQ8~DQ15. The data strobes DQS, LDQS and UDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS and UDQS to provide differential pair signaling to the system during both reads and wirtes. An EMRS(1) control bit enables or disables all complementary data strobe signals. UDQS, UDQS LDQS, LDQS Input/ Output In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1) x16 LDQS/LDQS and UDQS/UDQS "single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1) x16 LDQS and UDQS NC VDDQ VSSQ VDDL VSSDL VDD VSS VREF Supply Supply Supply Supply Supply Supply Supply No Connect : No internal electrical connection is present. DQ Power Supply: 1.8V +/- 0.1V DQ Ground DLL Power Supply : 1.8V +/- 0.1V DLL Ground Power Supply : 1.8V +/- 0.1V Ground Reference voltage for inputs for SSTL interface. Rev. 1.0 / July. 2008 7 Release H5PS5162FFR series 2. Maximum DC Ratings 2.1 Absolute Maximum DC Ratings Symbol VDD VDDQ VDDL VIN, VOUT TSTG II Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on VDDL pin relative to Vss Voltage on any pin relative to Vss Storage Temperature Input leakage current; any input 0V VIN VDD; all other balls not under test = 0V) Output leakage current; 0V VOUT VDDQ; DQ and ODT disabled Rating - 1.0 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V -55 to +100 -2 uA ~ 2 uA Units V V V V ℃ uA Notes 1 1 1 1 1, 2 IOZ -5 uA ~ 5 uA uA 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions. Please refer to JESD51-2 standard. 2.2 Operating Temperature Condition Symbol tOPER Parameter Normal Temp Operating Temperature Industrial Temp -40 to 85 Rating 0 to 95 Units °C °C Notes 1,2 1,2 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 2. At tOPER 85~95℃, Double refresh rate(tREFI: 3.9us) is required, and to enter the self refresh mode at this temperature range it must be required an EMRS command to change itself refresh rate. Rev. 1.0 / July. 2008 8 Release H5PS5162FFR series 3. AC & DC Operating Conditons 3.1 DC Operating Conditions 3.1.1 Recommended DC Operating Conditions (SSTL_1.8) Symbol VDD VDDL VDDQ VREF VTT Parameter Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage Rating Min. 1.7 1.7 1.7 0.49*VDDQ VREF-0.04 Typ. 1.8 1.8 1.8 0.50*VDDQ VREF Max. 1.9 1.9 1.9 0.51*VDDQ VREF+0.04 Units V V V mV V Notes 1 1,2 1,2 3,4 5 1. Min. Typ. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option. 2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD. 3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ 4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc). 5. VTT of transmitting device must track VREF of receiving device. 3.1.2 ODT DC electrical characteristics PARAMETER/CONDITION Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 ohm Deviation of VM with respect to VDDQ/2 Note: 1. Test condition for Rtt measurements Measurement Definition for Rtt(eff): Apply VIH (ac) and VIL (ac) to test pin separately, then measure current I(VIH (ac)) and I(VIL(ac)) respectively. VIH (ac), VIL (ac), and VDDQ values defined in SSTL_18 VIH (ac) - VIL (ac) SYMBOL Rtt1(eff) Rtt2(eff) Rtt3(eff) delta VM MIN 60 120 40 -6 NOM 75 150 50 MAX 90 180 60 +6 UNITS NOTES ohm ohm ohm % 1 1 1 1 Rtt(eff) = I(VIH (ac)) - I(VIL (ac)) Measurement Definition for VM : Measurement Voltage at test pin(mid point) with no load. 2 x Vm delta VM = VDDQ - 1 x 100% Rev. 1.0 / July. 2008 9 Release H5PS5162FFR series 3.2 DC & AC Logic Input Levels 3.2.1 Input DC Logic Level Symbol VIH(dc) VIL(dc) Parameter dc input logic high dc input logic low Min. VREF + 0.125 - 0.3 Max. VDDQ + 0.3 VREF - 0.125 Units V V Notes 3.2.2 Input AC Logic Level Symbol VIH (ac) VIL (ac) Parameter ac input logic high ac input logic low DDR2 400,533 Min. VREF + 0.250 Max. VREF - 0.250 DDR2 667,800 Min. VREF + 0.200 Max. VREF - 0.200 Units V V Notes 3.2.3 AC Input Test Conditions Symbol VREF VSWING(MAX) SLEW Note: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. Condition Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate Value 0.5 * VDDQ 1.0 1.0 Units V V V/ns Notes 1 1 2, 3 VDDQ VIH(ac) min VSWING(MAX) VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS delta TF Falling Slew = VREF - VIL(ac) max delta TF delta TR Rising Slew = VIH(ac) min - VREF delta TR < Figure : AC Input Test Signal Waveform> Rev. 1.0 / July. 2008 10 Release H5PS5162FFR series 3.2.4 Differential Input AC logic Level Symbol VID (ac) VIX (ac) Parameter ac differential input voltage ac differential cross point voltage Min. 0.5 0.5 * VDDQ - 0.175 Max. VDDQ + 0.6 0.5 * VDDQ + 0.175 Units V V Notes 1 2 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - V IL(DC). VDDQ VTR VID VCP VSSQ < Differential signal levels > Crossing point VIX or VOX Note: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC) - V IL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross. 3.2.5 Differential AC output parameters Symbol VOX (ac) Note: 1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross. Parameter ac differential cross point voltage Min. 0.5 * VDDQ - 0.125 Max. 0.5 * VDDQ + 0.125 Units V Notes 1 Rev. 1.0 / July. 2008 11 Release H5PS5162FFR series 3.3 Output Buffer Characteristics 3.3.1 Output AC Test Conditions Symbol VOTR Parameter Output Timing Measurement Reference Level SSTL_18 Class II 0.5 * VDDQ Units V Notes 1 1. The VDDQ of the device under test is referenced. 3.3.2 Output DC Current Drive Symbol IOH(dc) IOL(dc) 1. Parameter Output Minimum Source DC Current Output Minimum Sink DC Current SSTl_18 - 13.4 13.4 Units mA mA Notes 1, 3, 4 2, 3, 4 VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. The dc value of VREF applied to the receiving device is set to VTT The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm load line to define a convenient driver current for measurement. 3. 4. Rev. 1.0 / July. 2008 12 Release H5PS5162FFR series 3.3.3 OCD default characteristics Description Output impedance Output impedance step size for OCD calibration Pull-up and pull-down mismatch Output slew rate Note 1. Absolute Specifications ( Toper; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V). DRAM I/O specifications for timing,voltage, and slew rate are no longer applicable if OCD is changed from default settings. Please refer to the Device Operation & Timing Diagram of DDR2 for the Full Strength Default Driver Characteristics. 2. Impedance measurement condition for output source dc current: VDDQ=1.7V; VOUT=1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV. 3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage. 4. Slew rate measured from vil(ac) to vih(ac). 5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization. 6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process corners/ variations and represents only the DRAM uncertainty. A 0 ohm value(no calibration) can only be achieved if the OCD impedance is 18 ohms +/- 0.75 ohms under nominal conditions. Output Slew rate load: Sout Parameter Min Nom Max Unit ohms ohms ohms V/ns Notes 1 6 1,2,3 1,4,5,6,7,8 See full strength default driver characteristics 0 0 1.5 1.5 4 5 VTT 25 ohms point (Vout) 7. DRAM output slew rate specification applies to 400 , 533 and 667 MT/s speed bins. Output Reference 8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification. Rev. 1.0 / July. 2008 13 Release H5PS5162FFR series 3.4 IDD Specifications & Test Conditions IDD Specifications(max) DDR2 800 Symbol x16 IDD0 IDD1 IDD2P IDD2Q IDD2N F IDD3P S IDD3N IDD4W IDD4R IDD5B Normal Power Low Power* IDD7 12 60 240 200 165 12 50 200 170 160 12 50 170 150 150 12 40 130 110 150 mA mA mA mA mA 120 130 8 40 50 35 x16 110 120 8 40 40 30 x16 100 110 8 30 40 30 x16 100 110 8 30 30 30 mA mA mA mA mA mA DDR2 667 DDR2 533 DDR2 400 Units 8 8 8 8 mA IDD6 4 340 4 320 4 320 4 320 mA mA Note: 1. Low power parts have an extra suffix "L" in part number ; ex) H5PS5162FFR-xxL series Rev. 1.0 / July. 2008 14 Release H5PS5162FFR series IDD Test Conditions (IDD values are for full operating range of Voltage and Temperature, Notes 1-5) Symbol Conditions Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS min(IDD) ; CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are SWITCHING Operating one bank active-read-precharge current ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current ; All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); Fast PDN Exit MRS(12) = 0 CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Slow PDN Exit MRS(12) = 1 Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK at 0V; CKE £ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Units IDD0 mA IDD1 mA IDD2P mA IDD2Q mA IDD2N mA mA mA IDD3P IDD3N mA IDD4W mA IDD4R mA IDD5B mA IDD6 mA Rev. 1.0 / July. 2008 15 Release H5PS5162FFR series IDD7 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions mA Note: 1. VDDQ = 1.8 +/- 0.1V ; VDD = 1.8 +/- 0.1V (exclusively VDDQ = 1.9 +/- 0.1V ; VDD = 1.9 +/- 0.1V for C3 speed grade) 2. IDD specifications are tested after the device is properly initialized 3. Input slew rate is specified by AC Parametric Test Condition 4. IDD parameters are specified with ODT disabled. 5. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 6. Definitions for IDD LOW is defined as Vin £ VILAC(max) HIGH is defined as Vin Š VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. Rev. 1.0 / July. 2008 16 Release H5PS5162FFR series For purposes of IDD testing, the following parameters are to be utilized Speed Bin (CL-tRCD-tRP) CL(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD) tCK(IDD) tRASmin(IDD) tRASmax(IDD) tRP(IDD) tRFC(IDD)-512Mb DDR2-800 5-5-5 5 12.5 57.25 10 2.5 45 70000 12.5 105 6-6-6 6 15 60 10 2.5 45 70000 15 105 DDR2-667 5-5-5 5 15 60 10 3 45 70000 15 105 DDR2-533 4-4-4 4 15 60 10 3.75 45 70000 15 105 DDR2-400 Units 3-3-3 3 15 55 10 5 40 70000 15 105 tCK ns ns ns ns ns ns ns ns Detailed IDD7 The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification. Legend: A = Active; RA = Read with Autoprecharge; D = Deselect IDD7: Operating Current: All Bank Interleave Read operation All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) using a burst length of 4. Control and address bus inputs are STABLE during DESELECTs. IOUT = 0mA Timing Patterns for 4 bank devices -DDR2-400 3/3/3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks) -DDR2-533 3/3/3: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks) -DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D (16 clocks) -DDR2-667 4/4/4: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks) -DDR2-667 5/5/5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks) -DDR2-800 5/5/5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D (23 clocks) -DDR2-800 6/6/6: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D (24 clocks) Rev. 1.0 / July. 2008 17 Release H5PS5162FFR series 3.5. Input/Output Capacitance DDR2- 400 DDR2- 533 Min Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS CCK CDCK CI CDI CIO CDIO 1.0 x 1.0 x 2.5 x Max 2.0 0.25 2.0 0.25 4.0 0.5 DDR2 667 Min 1.0 x 1.0 x 2.5 x Max 2.0 0.25 2.0 0.25 3.5 0.5 DDR2 800 Min 1.0 x 1.0 x 2.5 x Max 2.0 0.25 1.75 0.25 3.5 0.5 pF pF pF pF pF pF Parameter Symbol Units 4. Electrical Characteristics & AC Timing Specification ( 0 ℃ ≤ TCASE ≤ 95℃; VDDQ = 1.8 V +/- 0.1V; VDD = 1.8V +/- 0.1V) Refresh Parameters by Device Density Parameter Refresh to Active /Refresh command time Average periodic refresh interval tREFI Symbol tRFC 0 ℃ ≤ TCASE ≤ 85℃ 85℃ < TCASE ≤ 95℃ 256Mb 512Mb 75 7.8 3.9 105 7.8 3.9 1Gb 127.5 7.8 3.9 2Gb 195 7.8 3.9 4Gb 327.5 7.8 3.9 Units ns us us DDR2 SDRAM speed bins and tRCD, tRP and tRC for corresponding bin Speed Bin(CL-tRCD-tRP) Parameter CAS Latency tRCD tRP tRAS tRC DDR2-800D 5-5-5 min 5 12.5 12.5 45 57.25 DDR2-800E 6-6-6 min 6 15 15 45 60 DDR2-667D 5-5-5 min 5 15 15 45 60 DDR2-533C 4-4-4 min 4 15 15 45 60 DDR2-400B 3-3-3 min 5 15 15 40 55 tCK ns ns ns ns Units Rev. 1.0 / July. 2008 18 Release H5PS5162FFR series Timing Parameters by Speed Grade (Refer to notes for information related to this table at the following pages of this table) Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input setup time (differential strobe) DQ and DM input hold time (differential strobe) DQ and DM input setup time (single ended strobe) DQ and DM input hold time (single ended strobe) Control & Address input pulse width for each input DQ and DM input pulse width for each input DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS First DQS latching transition to associated clock edge DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Write preamble Address and control input setup time Address and control input hold time Symbol tAC tDQSCK tCH tCL tHP tCK tDS (base) tDH (base) tDS tDH tIPW tDIPW DDR2-400 min -600 -500 0.45 0.45 min (tCL,tCH) 5000 150 275 25 25 0.6 0.35 tAC min 2*tAC min tHP - tQHS -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 350 475 max +600 +500 0.55 0.55 8000 tAC max tAC max tAC max 350 450 + 0.25 0.6 DDR2-533 min -500 -450 0.45 0.45 min (tCL,tCH) 3750 100 225 -25 -25 0.6 0.35 tAC min 2*tAC min tHP - tQHS -0.25 0.35 0.35;; 0.2 0.2 2 0.4 0.35 250 375 max +500 +450 0.55 0.55 8000 tAC max tAC max tAC max 300 400 + 0.25 0.6 Unit ps ps tCK tCK ps ps ps ps ps ps tCK tCK ps ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK tCK ps ps 5,7,9, 23 5,7,9, 23 10 18 18 18 13 12 11,12 15 6,7,8, 20 6,7,8, 21 6,7,8, 20 6,7,8, 21 Note Data-out high-impedance time from CK/CK tHZ tLZ(DQS) tLZ(DQ) tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE tIS(base) tIH(base) Rev. 1.0 / July. 2008 19 Release H5PS5162FFR series -Continue(Refer to notes for information related to this table at the following pages of this table) Parameter Read preamble Read postamble Active to active command period for 1KB page size products Active to active command period for 2KB page size products Four Active Window for 1KB page size products Four Active Window for 2KB page size products CAS to CAS command delay Write recovery time Symbol tRPRE tRPST tRRD tRRD tFAW tFAW tCCD tWR DDR2-400 min 0.9 0.4 7.5 10 37.5 50 2 15 WR+tRP 10 7.5 tRFC + 10 200 2 2 6 - AL 3 2 max 1.1 0.6 DDR2-533 min 0.9 0.4 7.5 10 37.5 50 2 15 WR+tRP 7.5 7.5 tRFC + 10 200 2 2 6 - AL 3 max 1.1 0.6 Unit tCK tCK ns ns ns ns tCK ns tCK ns ns ns tCK tCK tCK tCK tCK tCK ns ns tCK ns ns tCK tCK ns ns 15 17 16 1 1, 2 27 14 24 3 4 4 Note Auto precharge write recovery + precharge tDAL time Internal write to read command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any nonread command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW tWTR tXSNR tXSRD tXP tXARD tXARDS t Internal read to precharge command delay tRTP CKE tAOND tAON tAONPD t t AOFD AOF AOFPD t tANPD tAXPD tOIT tDelay 2 2 2 tAC(max) tAC(max) tAC(min) tAC(min) +1 +1 2tCK+ 2tCK+ tAC(min)+ tAC(min)+ tAC(max) tAC(max) 2 2 +1 +1 2.5 2.5 2.5 2.5 tAC(max) tAC(max) tAC(min) tAC(min) + 0.6 + 0.6 2.5tCK+ 2.5tCK+ tAC(min)+ tAC(min)+ tAC(max) tAC(max) 2 2 +1 +1 3 3 8 8 0 12 0 12 tIS+tCK+t tIS+tCK+t IH IH Rev. 1.0 / July. 2008 20 Release H5PS5162FFR series Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input setup time DQ and DM input hold time Control & Address input pulse width for each input DQ and DM input pulse width for each input Symbol tAC tDQSCK tCH tCL tHP tCK tDS(base) tDH (base) tIPW tDIPW DDR2-667 min -450 -400 0.45 0.45 min(tCL, tCH) 3000 100 175 0.6 0.35 tAC min 2*tAC min tHP - tQHS - 0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 200 275 0.9 0.4 45 7.5 10 max +450 +400 0.55 0.55 8000 tAC max tAC max tAC max 240 340 + 0.25 0.6 1.1 0.6 70000 - DDR2-800 min -400 -350 0.45 0.45 min(tCL, tCH) 2500 50 125 0.6 0.35 tAC min 2*tAC min tHP - tQHS - 0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 175 250 0.9 0.4 45 7.5 10 tAC max tAC max tAC max 200 300 + 0.25 0.6 1.1 0.6 70000 max +400 +350 0.55 0.55 - Unit ps ps tCK tCK ps ps ps ps tCK tCK ps ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK tCK ps ps tCK tCK ns ns ns Note 11,12 15 6,7,8,2 0 6,7,8,2 1 Data-out high-impedance time from CK/ tHZ CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS First DQS latching transition to associated clock edge DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Write preamble Address and control input setup time Address and control input hold time Read preamble Read postamble Activate to precharge command tLZ(DQS) tLZ(DQ) tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE tIS(base) tIH(base) tRPRE tRPST tRAS 18 18 18 13 12 10 5,7,9,2 2 5,7,9,2 3 19 19 3 4 4 Active to active command period for 1KB tRRD page size products Active to active command period for 2KB tRRD page size products Rev. 1.0 / July. 2008 21 Release H5PS5162FFR series -ContinueParameter Four Active Window for 1KB page size products Four Active Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Symbol tFAW tFAW tCCD tWR tDAL tWTR tRTP DDR2-667 min 37.5 50 2 15 WR+tRP 7.5 7.5 tRFC + 10 200 2 2 7 - AL 3 2 tAC(max) tAC(min) +0.7 2tCK+ tAC(min)+2 tAC(max)+1 2.5 2.5 tAC(max)+ tAC(min) 0.6 tAC(min) 2.5tCK+ +2 tAC(max)+1 3 8 0 12 tIS+tCK+tI H 2 max DDR2-800 min 37.5 50 2 15 WR+tRP 7.5 7.5 tRFC + 10 200 2 2 8 - AL 3 2 tAC(min) tAC(min) +2 2.5 tAC(min) tAC(min) +2 3 8 0 tIS+tCK +tIH max Unit ns ns tCK ns tCK ns ns ns tCK tCK tCK tCK tCK 2 tCK tAC(max) ns +0.7 2tCK+ ns tAC(max)+1 2.5 tCK tAC(max) ns +0.6 2.5tCK+ ns tAC(max)+1 tCK tCK 12 ns ns 1 1, 2 3 14 Note Exit self refresh to a non-read command tXSNR Exit self refresh to a read command Exit precharge power down to any nonread command tXSRD tXP Exit active power down to read command tXARD Exit active power down to read command tXARDS (Slow exit, Lower power) CKE minimum pulse width t CKE (high and low pulse width) tAOND ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW t AON 6,16 tAONPD tAOFD tAOF t 17 AOFPD tANPD tAXPD tOIT tDelay 15 Rev. 1.0 / July. 2008 22 Release H5PS5162FFR series General notes, which may apply for all AC parameters 1. Slew Rate Measurement Levels a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS DQS = +500mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device. b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VIL(dc) to VIH(ac) for rising edges and from VIH(dc) and VIL(ac) for falling edges. For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK - CK = +500 mV(250mV to -500 mV for falling egdes). c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe. 2. DDR2 SDRAM AC timing reference load The following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). VDDQ DQ DQS DQS RDQS RDQS DUT Output Timing reference point 25Ω VTT = VDDQ/2 AC Timing Reference Load The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal. 3. DDR2 SDRAM output slew rate test load Output slew rate is characterized under the test conditions as shown below. VDDQ DUT DQ DQS, DQS RDQS, RDQS Output Test point 25Ω VTT = VDDQ/2 Slew Rate Test Load 4. Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single Rev. 1.0 / July. 2008 23 Release H5PS5162FFR series VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 K ohm resistor to insure proper operation. DQS tDQSH tDQSL DQS/ DQS DQS tWPRE VIH(ac) VIH(dc) D VIL(ac) tDS tDS VIH(ac) DMin VIL(ac) tDH DMin D D VIL(dc) tDH DMin VIL(dc) VIH(dc) D tWPST DQ DM DMin Figure -- Data input (write) timing tCH CK tCL CK/CK CK DQS DQS/DQS DQS tRPRE tRPST Q tDQSQmax tQH Q Q tDQSQmax tQH Q DQ Figure -- Data output (read) timing 5. AC timings are for linear signal transitions. See System Derating for other signal transitions. 6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 7. All voltages referenced to VSS. 8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/ supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. Rev. 1.0 / July. 2008 24 Release H5PS5162FFR series Specific Notes for dedicated AC parameters 1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing where a lower power value is defined by each vendor data sheet. 2. AL = Additive Latency 3. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min) have been satisfied. 4. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency 5. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. See System Derating for other slew rate values. 6. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0 V/ns. See System Derating for other slew rate values. tDS, tDH Derating Values(ALL units in 'ps', Note 1 applies to entire Table) DQS, DQS Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns △ tD △ tD △ tD △ tD △ tD △ tD △ tD △ tD △ tD △ tD △ tD △ tD △ tD △ tD △ tD △ tD △ tD △ tD S H S H S H S H S H S H S H S H S H 125 45 125 45 +125 +45 83 0 21 0 83 0 -11 21 0 -14 +83 0 -11 -25 +21 0 -14 -31 95 12 1 -13 -31 33 12 -2 -19 -42 24 13 -1 -42 -43 24 10 -7 -19 -59 25 11 -7 -31 -74 22 5 -8 -47 -89 23 5 -19 -62 17 -6 -35 -77 17 -7 -50 6 -23 -65 5 -38 -11 -53 2.0 1.5 DQ Slew rate V/ns 1.0 0.9 0.8 0.7 0.6 0.5 0.4 -127 -140 -115 -128 -103 -116 7. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differen tial slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single ended mode. See System Derating for other slew rate values. 8. tDS and tDH derating table (for DDR2- 400 / 533) 1) For all input signals the total tDS(setup time) and tDH(hold time) required is calculated by adding the datasheet value to the derating value listed in above Table. Setup(tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vih(ac)min. Setup(tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘ VREF(dc) to ac region’, use nominal slew rate for derating value(see Fig a.) If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value(see Fig b.) Hold(tDH) nominal slew rate for a rising signal is defined as the slew rate rate between the last crossing of Vil(dc) max and the first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc) min and the first crossing of VREF(dc). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig d.) Rev. 1.0 / July. 2008 25 Release H5PS5162FFR series Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/ IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. Hold(tDH) nominal slew rate for a rising signal is defined as the slew rate rate between the last crossing of Vil(dc) max and the first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc) min and the first crossing of VREF(dc). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig d.) Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/ IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. Rev. 1.0 / July. 2008 26 Release H5PS5162FFR series Fig. a Illustration of nominal slew rate for tIS,tDS CK,DQS CK, DQS tIS, tDS tIH, tDH tIS, tDS tIH, tDH VDDQ VIH(ac)min VIH(dc)min nominal slew rate VREF(dc) nominal slew rate VREF to ac region VIL(dc)max VIL(ac)max Vss Delta TF Setup Slew Rate = Falling Signal VREF(dc)-VIL(ac)max Delta TF Delta TR Setup Slew Rate = Rising Signal VIH(ac)min-VREF(dc) Delta TR Rev. 1.0 / July. 2008 27 Release H5PS5162FFR series Fig. -b Illustration of tangent line for tIS,tDS CK, DQS CK, DQS tIS, tDS VDDQ tIH, tDH nominal line tIS, tDS tIH, tDH VIH(ac)min VIH(dc)min tangent line VREF(dc) Tangent line VIL(dc)max VREF to ac region VIL(ac)max Nomial line Vss Delta TF Delta TR Setup Slew Rate Tangent line[VIH(ac)min-VREF(dc)] = Rising Signal Delta TR Setup Slew Rate Tangent line[VREF(dc)-VIL(ac)max] = Falling Signal Delta TF Rev. 1.0 / July. 2008 28 Release H5PS5162FFR series Fig. -c Illustration of nominal line for tIH, tDH CK, DQS CK, DQS tIS, tDS VDDQ tIH, tDH tIS, tDS tIH, tDH VIH(ac)min VIH(dc)min dc to VREF region VREF(dc) nominal slew rate nominal slew rate VIL(dc)max VIL(ac)max Vss Delta TR Delta TF Hold Slew Rate = Rising Signal VREF(dc)-VIL(dc)max Delta TR VIH(dc)min - VREF(dc) Hold Slew Rate = Falling Signal Delta TF Rev. 1.0 / July. 2008 29 Release H5PS5162FFR series Fig. -d Illustration of tangent line for tIH , tDH CK, DQS CK, DQS tIS, tDS VDDQ tIH, tDH tIS, tDS tIH, tDH VIH(ac)min nominal line VIH(dc)min tangent line VREF(dc) dc to VREF region VIL(dc)max Tangent line nominal line VIL(ac)max Vss Delta TR Delta TF Hold Slew Rate Tangent line[VREF(dc)-VIL(ac)max] = Rising Signal Delta TR Tangent line[VIH(ac)min-VREF(dc)] Hold Slew Rate = Falling Signal Delta TF Rev. 1.0 / July. 2008 30 Release H5PS5162FFR series 9. tIS and tIH (input setup and hold) derating tIS, tIH Derating Values for DDR2 400, DDR2 533 CK, CK Differential Slew Rate 2.0 V/ns △tIS 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 +187 +179 +167 +150 +125 +83 +0 -11 -25 -43 -67 -100 -150 -223 -250 -500 -750 -1250 1.5 V/ns △tIS +217 +209 +197 +180 +155 +113 +30 +19 +5 -37 -37 -80 -145 -255 -320 -495 -770 -1420 1.0 V/ns △tIS +247 +239 +227 +210 +185 +143 +60 +49 +35 -7 -7 -50 -115 -225 -290 -465 -740 -1065 △tIH +94 +89 +83 +75 +45 +21 0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 -1125 △tIH +124 +119 +113 +105 +75 +51 +30 +16 -1 -53 -53 -95 -158 -262 -345 -470 -678 -1095 △tIH +124 +149 +143 +135 +105 +81 60 +46 +29 +6 -23 -65 -128 -232 -315 -440 -648 TBD Units Notes ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Command / Address Slew rate(V/ns) 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 0.1 tIS, tIH Derating Values for DDR2 667, DDR2 800 CK, CK Differential Slew Rate 2.0 V/ns △tIS 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 +150 +143 +133 +120 +100 +67 0 -5 -13 -22 -34 -60 -100 -168 -200 -325 -517 -1000 1.5 V/ns △tIS +180 +173 +163 +150 +130 +97 +30 +25 +17 +8 -4 -30 -70 -138 -170 -295 -487 -970 1.0 V/ns △tIS +210 +203 +193 +180 +160 +127 +60 +55 +47 +38 -26 0 -40 -108 -140 -265 -457 -940 △tIH +94 +89 +83 +75 +45 +21 0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 -1125 △tIH +124 +119 +113 +105 +75 +51 +30 +16 -1 -24 -53 -95 -158 -262 -345 -470 -678 -1095 △tIH +154 +149 +143 +135 +105 +81 60 +46 +29 +6 -23 -65 -128 -232 -315 -440 -648 -1065 Units Notes ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Command / Address Slew rate(V/ns) 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 0.1 Rev. 1.0 / July. 2008 31 Release H5PS5162FFR series 1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the datasheet value to the derating value listed in above Table. Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min. Setup(tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate for line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value(see fig a.) If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value(see Fig b.) Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of VREF(dc). Hold(tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded ‘dc to VREF(dc) region’, use nominal slew rate for derating value(see Fig.c) If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig d.) Although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in between the values listed in table, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. 10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 11. MIN ( t CL, t CH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as provided to the device (i.e. this value can be greater than the minimum specification limits for t CL and t CH). For example, t CL and t CH are = 50% of the period, less the half period jitter ( t JIT(HP)) of the clock source, and less the half period jitter due to crosstalk ( t JIT(crosstalk)) into the clock traces. 12. t QH = t HP – t QHS, where: tHP = minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (tCH,tCL). tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS/ DQS and associated DQ in any given cycle. 14. t DAL = (nWR) + ( tRP/tCK): For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period. nWR refers to the t WR parameter stored in the MR. Example: For DDR533 at t CK = 3.75 ns with t WR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks =4 +(4)clocks=8clocks. Rev. 1.0 / July. 2008 32 Release H5PS5162FFR series 15. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of clock frequency change during precharge power-down, a specific procedure is required as described in section 2.9. 16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND. 17. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. 18. tHZ and tLZ transitions occur in the same access time as valid data transitions. Thesed parameters are referenced to a specific voltage level which specifies when the device output is no longer driving(tHZ), or begins driving (tLZ). Below figure shows a method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistenet. 19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Below figure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE). Below Figure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. VOH + xmV VOH + 2xmV tHZ tRPST end point VTT + 2xmV VTT + xmV tLZ tRPRE begin point T2 T1 VOL + 1xmV VOL + 2xmV T1 VTT -xmV VTT - 2xmV T2 tHZ , tRPST end point = 2*T1-T2 tLZ , tRPRE begin point = 2*T1-T2 20. Input waveform timing with differential data strobe enabled MR[bit10] =0, is referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. 21. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(dc) level to the differential data strobe crosspoint for a rising signal and VIL(dc) to the differential data strobe crosspoint for a falling signal applied to the device under test. Rev. 1.0 / July. 2008 33 Release H5PS5162FFR series Differential Input waveform timing DQS DQS tDS tDH tDS tDH VDDQ VIH(ac)min VIH(dc)min VREF(dc) VIL(dc)max VIL(ac)max VSS 22. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the device under test. 23. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the device under test. 24. tWTR is at least two clocks (2 x tCK or 2 x nCK) independent of operation frequency. 25. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic between Vil(dc)max and Vih(dc)min. 26. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic between Vil(dc)max and Vih(dc)min. 27. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. Rev. 1.0 / July. 2008 34 Release H5PS5162FFR series 28. If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 29. These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 30. These parameters are measured from a data strobe signal ((L/U/R)DQS/DQS) crossing to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 31. These parameters are measured from a data signal ((L/U) DM, (L/U) DQ0, (L/U) DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS/DQS) crossing. 32. For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK(avg)}, which is in clock cycles, assuming all input clock jitter specificationsare satisfied. For example, the device will support tnRP = RU {tRP / tCK(avg)}, which is in clock cycles, if all input clock jitterspecifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15ns, the device will support tnRP =RU{tRP / tCK(avg)} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm+5 is valid even if (Tm+5 - Tm) is less than 15ns due to input clock jitter. 33. tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [ps] / tCK(avg) [ps] }, where WR is the value programmed in the mode register set. 34. New units, ‘tCK(avg)’ and ‘nCK’, are introduced in DDR2-667 and DDR2-800. Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ‘nCK’, represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, ‘tCK’, is used for both concepts. ex) tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+2, even if (Tm+2 - Tm) is 2 x tCK(avg) + tERR(2per),min. 35. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution. Rev. 1.0 / July. 2008 35 Release H5PS5162FFR series DDR2-667 Parameter Clock period jitter Clock period jitter during DLL locking period Cycle to cycle clock period jitter Cycle to cycle clock period jitter during DLL locking period Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across n cycles, n=6...10, inclusive Cumulative error across n cycles, n=11...50, inclusive Duty cycle jitter DDR2-800 Units Notes 35 35 35 35 35 35 35 35 35 35 35 Symbol min tJIT(per) tJIT(per,lck) tJIT(cc) tJIT(cc,lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6~10per) tERR(11~50per) tJIT(duty) -125 -100 -250 -200 -175 -225 -250 -250 -350 -450 -125 max 125 100 250 200 175 225 250 250 350 450 125 min -100 -80 -200 -160 -150 -175 -200 -200 -300 -450 -100 max 100 80 200 160 150 175 200 200 300 450 100 ps ps ps ps ps ps ps ps ps ps ps 36. These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (Min and max of SPEC values are to be used for calculations in the table below.) Parameter Absolute clock period Absolute clock HIGH pulse width Absolute clock LOW pulse width Symbol tCK(abs) tCH(abs) tCL(abs) min tCK(avg),min+tJIT(per),min max tCK(avg),max+tJIT(per),max Units ps ps ps tCH(avg),min*tCK(avg),min+tJIT( tCH(avg),max*tCK(avg),max+tJI per),min T(per),max tCL(avg),min*tCK(avg),min+tJIT( tCL(avg),max*tCK(avg),max+tJIT per),min (per),max Example: For DDR2-667, tCH(abs),min = ( 0.48 x 3000 ps ) - 125 ps = 1315 ps 37. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = Min ( tCH(abs), tCL(abs) ), where, tCH(abs) is the minimum of the actual instantaneous clock HIGH time; tCL(abs) is the minimum of the actual instantaneous clock LOW time; Rev. 1.0 / July. 2008 36 Release H5PS5162FFR series 38. tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p-channel to n-channel variation of the output drivers 39. tQH = tHP ? tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum. 40. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 ps and tERR(6-10per), max = + 293 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(6-10per),max = - 400 ps - 293 ps = - 693 ps and tDQSCK,max(derated) = tDQSCK,max - tERR(6-10per),min = 400 ps + 272 ps = + 672 ps. Similarly, tLZ(DQ) for DDR2-667 derates to tLZ(DQ),min(derated) = - 900 ps - 293 ps = 1193 ps and tLZ(DQ),max(derated) = 450 ps + 272 ps = + 722 ps. (Caution on the min/max usage!) 41. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(per),min = - 72 ps and tJIT(per),max = + 93 ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),min = 0.9 x tCK(avg) - 72 ps = + 2178 ps and tRPRE,max(derated) = tRPRE,max + tJIT(per),max = 1.1 x tCK(avg) + 93 ps = + 2843 ps. (Caution on the min/max usage!) 42. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(duty) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(duty),min = - 72 ps and tJIT(duty),max = + 93 ps, then tRPST,min(derated) = tRPST,min + tJIT(duty),min = 0.4 x tCK(avg) - 72 ps = + 928 ps and tRPST,max(derated) = tRPST,max + tJIT(duty),max = 0.6 x tCK(avg) + 93 ps = + 1592 ps. (Caution on the min/max usage!) Rev. 1.0 / July. 2008 37 Release H5PS5162FFR series 43. When the device is operated with input clock jitter, this parameter needs to be derated by { tJIT(duty),max - tERR(6-10per),max } and { - tJIT(duty),min - tERR(6-10per),min } of the actual input clock.(output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 ps, tERR(610per), max = + 293 ps, tJIT(duty),min = - 106 ps and tJIT(duty),max = + 94 ps, then tAOF,min(derated) = tAOF,min + { - tJIT(duty),max - tERR(6-10per),max } = - 450 ps + { - 94 ps - 293 ps} = - 837 ps and tAOF,max(derated) = tAOF,max + { - tJIT(duty),min - tERR(6-10per),min } = 1050 ps + { 106 ps + 272 ps } = + 1428 ps. (Caution on the min/max usage!) 44. For tAOFD of DDR2-400/533, the 1/2 clock of tCK in the 2.5 x tCK assumes a tCH, input clock HIGH pulse width of 0.5 relative to tCK. tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of tCH offset present at the DRAM input with respect to 0.5. For example, if an input clock has a worst case tCH of 0.45, the tAOF,min should be derated by subtracting 0.05 x tCK from it, whereas if an input clock has a worst case tCH of 0.55, the tAOF,max should be derated by adding 0.05 x tCK to it. Therefore, we have; tAOF,min(derated) = tAC,min - [0.5 - Min(0.5, tCH,min)] x tCK tAOF,max(derated) = tAC,max + 0.6 + [Max(0.5, tCH,max) - 0.5] x tCK or tAOF,min(derated) = Min(tAC,min, tAC,min - [0.5 - tCH,min] x tCK) tAOF,max(derated) = 0.6 + Max(tAC,max, tAC,max + [tCH,max - 0.5] x tCK) where tCH,min and tCH,max are the minimum and maximum of tCH actually measured at the DRAM input balls. 45. For tAOFD of DDR2-667/800, the 1/2 clock of nCK in the 2.5 x nCK assumes a tCH(avg), average input clock HIGH pulse width of 0.5 relative to tCK(avg). tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of tCH(avg) offset present at the DRAM input with respect to 0.5. For example, if an input clock has a worst case tCH(avg) of 0.48, the tAOF,min should be derated by subtracting 0.02 x tCK(avg) from it, whereas if an input clock has a worst case tCH(avg) of 0.52, the tAOF,max should be derated by adding 0.02 x tCK(avg) to it. Therefore, we have; tAOF,min(derated) = tAC,min - [0.5 - Min(0.5, tCH(avg),min)] x tCK(avg) tAOF,max(derated) = tAC,max + 0.6 + [Max(0.5, tCH(avg),max) - 0.5] x tCK(avg) or tAOF,min(derated) = Min(tAC,min, tAC,min - [0.5 - tCH(avg),min] x tCK(avg)) tAOF,max(derated) = 0.6 + Max(tAC,max, tAC,max + [tCH(avg),max - 0.5] x tCK(avg)) where tCH(avg),min and tCH(avg),max are the minimum and maximum of tCH(avg) actually measured at the DRAM input balls. Note that these deratings are in addition to the tAOF derating per input clock jitter, i.e. tJIT(duty) and tERR(6-10per). However tAC values used in the equations shown above are from the timing parameter table and are not derated. Thus the final derated values for tAOF are; tAOF,min(derated_final) = tAOF,min(derated) + { - tJIT(duty),max - tERR(6-10per),max } tAOF,max(derated_final) = tAOF,max(derated) + { - tJIT(duty),min - tERR(6-10per),min } Rev. 1.0 / July. 2008 38 Release H5PS5162FFR series Package Dimension(x16) 84Ball Fine Pitch Ball Grid Array Outline 8.0 +/- 0.10 A1 Ball Mark 13.00 +/- 0.10 1.20 Max. 0.34 +/- 0.05 0.8 x 14 = 11.2 0.80 A1 Ball Mark 0.80 1 2 3 7 8 9 84 - φ0.45 ± 0.05 0.80 x 8 = 6.40 note: all dimension units are Millimeters. Rev. 1.0 / July. 2008 ABCD EFG H J K LMNP R 39