H5RS5223CFR-11C

H5RS5223CFR 512Mbit (16Mx32) GDDR3 SDRAM H5RS5223CFR This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.5 /Jul. 2008 1 H5RS5223CFR Revision History Revision 0.1 0.2 0.3 Page Defined target spec. Changed tCK_max to 2ns at (-N0) & PKG drawing value 1. Revised the slew rate from 6V/ns to 3V/ns on page 54. 2. Inserted the code ‘C’ in Part number, that means ‘normal power and commercial temperature’. Inserted 1.2Ghz speed bin Added IDD Values 47 43 44 44 3 48 51-52 55 Changed IDDO/IDD1/IDD5A Values Inserted the thermal characteristics table (Table 12) Inserted the note for IO reference voltage (VREF) Inserted the note (VDD/VDDQ) 1. 2. 3. 4. Inserted Inserted Inserted Inserted 1.3Ghz speed bin (-N3C) IDD Values for 1.3Ghz AC Parameter Values for 1.3Ghz Eletrical Characteristics Usage Values for 1.3Ghz History Date Oct. 2007 Oct. 2007 Nov. 2007 Remark Preliminary Preliminary Preliminary 0.4 1.0 1.1 1.2 1.3 1.4 1.5 Dec. 2007 Jan. 2008 Jan. 2008 Mar. 2008 May. 2008 Jun. 2008 Jul. 2008 Preliminary Rev.1.5 / Jul. 2008 2 H5RS5223CFR DESCRIPTION The Hynix H5RS5223 is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The Hynix H5RS5223 is internally configured as a eight-bank DRAM. The Hynix H5RS5223 uses a double data rate architecture to achieve high-speed opreration. The double date rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the Hynix H5RS5223 consists of a 4n-bit wide, every two-clock-cycles data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the Hynix H5RS5223 is burst oriented; accesses start at a selected locations and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ of WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0,BA1, BA2 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the Hynix H5RS5223 must be initialized. FEATURES • 2.05V/ 1.8V/ 1.5V power supply supports (For more detail, Please see the Table 12 on page 43) • • • Single ended READ Strobe (RDQS) per byte Single ended WRITE Strobe (WDQS) per byte Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle • • • • • • On Die Termination Output Driver Strength adjustment by EMRS Calibrated output driver Differential clock inputs (CK and CK#) Commands entered on each positive CK edge RDQS edge-aligned with data for READ; with WDQS center-aligned with data for WRITE • 8 internal banks for concurrent operation • • • • • • • • • • • • • CAS Latency: 4~11 (clock) Data mask (DM) for masking WRITE data 4n prefetch Programmable burst lengths: 4, 8 32ms, 8K-cycle auto refresh Auto precharge option Auto Refresh and Self Refresh Modes 1.8V Pseudo Open Drain I/O Concurrent Auto Precharge support tRAS lockout support, Active Termination support Programmable Write latency(1, 2, 3, 4, 5, 6) Boundary Scan Function with SEN pin Mirror Function with MF pin ORDERING INFORMATION Part No. H5RS5223CFR-N3C H5RS5223CFR-N2C H5RS5223CFR-N0C H5RS5223CFR-11C H5RS5223CFR-14C H5RS5223CFR-20C H5RS5223CFR-14L H5RS5223CFR-18C VDD/VDDQ=1.5V VDD/VDDQ=1.8V VDD/VDDQ=2.05V Power Supply Clock Frequency 1300MHz 1200MHz 1000MHz 900MHz 700MHz 500MHz 700MHz 550MHz Max Data Rate 2600Mbps/pin 2400Mbps/pin 2000Mbps/pin 1800Mbps/pin 1400Mbps/pin 1000Mbps/pin 1400Mbps/pin 1100Mbps/pin POD_15 POD_18 10mmx14mm 136Ball FBGA Interface Package Note) Above Hynix P/N’s and their homogeneous Subcomponents are RoHS (& Lead free) compliant Rev.1.5 / Jul. 2008 3 H5RS5223CFR BALLOUT CONFIGURATION 1 A B C D E F G H J K L M N P R T U VDDQ VSSQ VDDQ 2 VDD DQ0 DQ2 3 VSS DQ1 DQ3 4 ZQ VSSQ VDDQ 5 6 7 8 9 MF VSSQ VDDQ 10 VSS DQ9 DQ11 11 VDD DQ8 DQ10 12 VDDQ VSSQ VDDQ VSSQ W DQS0 RDQS0 VSSQ VDDQ VDD VSS VREF VSS VDD VSS VDD VDDQ DQ4 DQ6 VSSQ A1 NC A10 VSSQ DQ24 DQ26 DM0 DQ5 DQ7 RAS# RFU A2 DQ25 DQ27 DM3 VDDQ CAS# BA0 CKE VDDQ A0 A11 A3 VDDQ VSSQ RDQS1 W DQS1 VSSQ VDDQ CS# BA1 W E# VDDQ A4 A7 A9 VDDQ DM1 DQ13 DQ15 BA2 CK# A6 DQ17 DQ19 DM2 DQ12 DQ14 VSSQ A5 CK A8/AP VSSQ DQ16 DQ18 VDDQ VDD VSS VREF VSS VDD VSS VDD VDDQ VSSQ W DQS3 RDQS3 VSSQ VDDQ VSSQ VDDQ DQ28 DQ30 VDD DQ29 VDDQ DQ31 VSSQ VSS SEN VSSQ RDQS2 W DQS2 VSSQ VDDQ VSSQ RES DQ21 DQ23 VSS DQ20 DQ22 VDD VDDQ VSSQ VDDQ 16M x 32 Configuration Refresh Count Bank Address Row Address Column Address AP Flag 2M x 32 x 8 banks 8k BA0 - BA2 A0~A11 A0~A7, A9 A8 Rev.1.5 / Jul. 2008 4 H5RS5223CFR FUNCTIONAL BLOCK DIAGRAM 8Banks x 2Mbit x 32 I/O double Data Rate Synchronous DRAM CKE CK CK# COMMAND DECODE CS# RAS# CAS# W E# CONTROL LOGIC BANK7 BANK6 BANK5 BANK4 BANK3 BANK0 BANK2 BANK1ROW ADDRESS LATCH BANK0 & ROW DECODER ADDRESS 40% LATCH & DECODER MODE REGISTERS 15 12 REFRESH COUNTER 12 ROW ADDRESS MUX 12 BANK7 BANK6 BANK5 BANK4 BANK3 BANK2 BANK1 BANK0 MEMORY ARRAY (4096x512x128) BANK0 MEMORY ARRAY (4096x512x128) SENSE AMPLIFIERS CCL0, CCL1 32 128 READ LATCH 32 32 32 MUX 32 DATA CK/ CK# DLL DRVRS DQ0~DQ31 SENSE AMPLIFIERS 66,536 3 INPUT REGISTERS I/O GATING DM MASK LOGIC BANK CONTROL LOGIC 128 4 4 16 512 (x128) CK/CK# 4 4 4 4 4 32 32 32 32 32 RCVRS W DQS(0~3) A0~A11 BA0- BA2 15 ADDRESS REGISTER 3 128 COLUMN DECODER CK/CK# 9 COLUMN ADDRESS COUNTER LATCH 7 2 W RITE FIFO & DRIVERS MASK 4 4 32 DM(0~3) CK OUT CK IN 32 128 DATA 32 32 COL0, COL1 4 Rev.1.5 / Jul. 2008 5 H5RS5223CFR BALLOUT DESCRIPTIONS FBGA BALLOUT J10, J11 SYMBOL CK, CK# TYPE Input DESCRIPTION Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations(all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. Chip Select: CS# enables (registered LOW)and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command Inputs: RAS#, CAS# and WE#(along with CS#) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on rising and falling edges of WDQS. Bank Address Inputs: BA0 and BA2 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit(A8) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A8 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A8 LOW, bank selected by BA0 - BA2 ) or all banks (A8 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. H4 CKE Input F9 CS# Input H3, F4, H9 RAS#, CAS#, WE# Input E(3, 10), N(3, 10) DM0-DM3 Input G(4, 9), H10 BA0 - BA2 Input H(2, 11), K(2-4, 9-11), L(4, 9), M(4, 9) A0-A11 Input B(2, 3), C(2, 3), E2, F(2, 3), G3,B(10, 11), C(10, 11), E11, F(10, 11), G10, L10, M(10, 11), N11, R(10, 11), T(10,11), L3, M(2, 3), N2,R(2, 3), T(2, 3) D(3, 10), P(3, 10) D(2, 11), P(2, 11) U4 J(2, 3) DQ0-31 I/O Data Input/Output: RDQS0-3 WDQS0-3 SEN NC/RFU Output Input Input READ Data Strobe: Output with read data. RDQS is edge-aligned with read data. WRITE Data strobe: Input with write data. WDQS is center aligned to the input data. Scan Enable Pin. Logic High would enable Scan Mode. Should be tied to GND when not in use. This pin is a CMOS input. No Connect Rev.1.5 / Jul. 2008 6 H5RS5223CFR BALLOUT DESCRIPTIONS FBGA Ball Out A(1, 12), C(1, 4, 9, 12), J(4, 9), N(1, 4, 9, 12), R(1, 4, 9, 12), U(1, 12) B(1, 4, 9, 12), D(1, 4, 9, 12), G(2, 11), L(2, 11), P(1, 4, 9, 12), T(1, 4, 9, 12) A(2, 11), F(1, 12), M(1, 12), U(2, 11) K(1, 12) A(3, 10), G(1, 12), L(1, 12), U(3, 10) J(1, 12) H(1, 12) A9 A4 U9 SYMBOL VDDQ TYPE Supply DESCRIPTION DQ Power Supply: +1.8V. Isolated on the die for improved noise immunity. DQ Ground: Isolated on the die for improved noise immunity. Power Supply: +1.8V. Ground Reference voltage. Mirror Function for clamshell mounting of DRAMs External Reference Pin for autocalibration. It should be connected to RQ(=240Ω) Reset Pin. The RES pin is a VDD CMOS input. -CONTINUE VSSQ VDD VSS VREF MF ZQ RES Supply Supply Supply Supply Reference Reference Reference Mirror Function The GDDR3 SDRAM provides a mirror function(MF) ball to change the physical location of the control lines and all address lines, assisting in routing devices back to back. The MF ball will affect RAS#, CAS#, WE#, CS# and CKE on balls H3, F4, H9, F9 and H4 respectively and A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, BA0, BA1 and BA2 on balls K4, H2, K3, M4, K9, H11, K10, L9, K11, M9, K2, L4, G4, G9 and H10 respectively and only detects a DC input. The MF ball should be tied directly to VSS of VDD depending on the control line orientation desired. When MF ball is tied low the ball orientation is as follows. RAS#-H3, CAS#-F4, WE#-H9, CS#-F9, CKE-H4, A0-K4, A1-H2, A2-K3, A3M4, A4-K9, A5-H11, A6-K10, A7-L9, A8-K11, A9-M9, A10-K2, A11-L4, BA0-G4, BA1-G9 and BA2-H10. The high condition on the MF ball will change the location of the control balls as follows; CS#-F4, cas#-F9, ras#-H10, WE#-H4, CKE-H9, A0-K9, A1-H11, A2-K10, A3-M9, A4-K4, A5-H2, A6-K3, A7-L4, A8-K2, A9-M4, A10-K11, A11-L9, BA0-G9, BA1-G4 and BA2-H3. This Mirror Fuction does not work under Boundary Scan Test condition. Mirror Function Signal Mapping PIN RAS# CAS# WE# CS# CKE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 BA2 MF LOGIC STATE HIGH H10 F9 H4 F4 H9 K9 H11 K10 M9 K4 H2 K3 L4 K2 M4 K11 L9 G9 G4 H3 LOW H3 F4 H9 F9 H4 K4 H2 K3 M4 K9 H11 K10 L9 K11 M9 K2 L4 G4 G9 H10 Rev.1.5 / Jul. 2008 7 H5RS5223CFR GDDR3 Initialization and Power Up GDDR3 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must be first applied to VDD and VDDQ simultaneously or VDD first and VDDQ later, and then to VREF. VREF can be applied any time after VDDQ. Once power has been applied and the clocks are stable the GDDR3 device requires 200us before the RES pin transitions to high. Upon power-up and after the clock is stable, the on-die termination value for the address and control pins will be set, based on the state of CKE when the RES pin transitions from LOW to HIGH. On the rising edge of RES, the CKE pin is latched to determine the on die termination value for the address and control lines. If CKE is sampled at a logic LOW then the on die termination will be set to 1/2 of ZQ and, if CKE is sampled logic HIGH then the on die termination will be set to the same value as ZQ. CKE must meet tATS and tATH on the rising of RES to set the on die termination for address and control lines. Once tATH is met, set CKE to HIGH. An additional 200us is required for the address and command on die terminations to calibrate and update. RES must be maintained at a logic LOW-level value and CS# must be maintained HIGH, during the first stage of power-up to ensure that the DQ outputs will be in a High-Z state(un-terminated). After the RES pin transitions from LOW to HIGH, wait until a 200us delay is satisfied. Issue DESELECT on the command bus during this time. Issue a PRECHARGE ALL command. Next a LOAD MODE REGISTER command must be issued for the extended mode register (BA1 LOW and BA0 HIGH) to activate the DLL and set operating parameters, followed by the LOAD MODE REGISTER command (BA0/BA1 both LOW) to reset the DLL and to program the rest of the operating parameters. 5k clock cycles are required between the DLL reset and any READ command to allow the DLL to lock. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be issued. Following these requirements, the GDDR3 SDRAM is ready for normal operation. VDD VDDQ VREF CK# CK RESET ATS ATH tCH tCL T0 T1 Ta0 Tb0 Tc0 Td0 Te0 Tfo CKE COMMAND NOP PRE LMR LMR PRE AR AR ACT DM tIS tIH CODE A0A7,A9A11,A8 BA0,BA 1 ALL BANKS tIS tIH CODE ALL BANKS RA CODE tIS tIH tIS tIH CODE tIS tIH RA RA RDQS WDQS DQ T=100us T=10us T=200us Power-up:VDD and Clock stable HIGH HIGH HIGH BAO=H, BA1=L BAO=L, BA1=H Precharge All Banks tRP tMRD tMRD tRP tRFC tRFC Load Extended Mode Resistor Load Mode Resistor Precharge All Banks DLL Reset 1st Auto Refresh 2nd Auto Refresh Rev.1.5 / Jul. 2008 8 H5RS5223CFR ODT Updating The GDDR3 SDRAM uses programmable impedance output buffers. This allows a user to match the driver impedance to the system. To adjust the impedance, an external precision resistor (RQ) is connected between the ZQ pin and VSSQ. The value of the resistor must be six times the desired driver impedance. For example, a 240Ω. resistor is required for an output impedance of 40Ω. To ensure that output impedance is one-sixth the value of RQ (within 10 percent), RQ should be in the range of 210Ω. to 270Ω. (30Ω. - 50Ω. output impedance). CK and CK# are not internally terminated. CK and CK# will be terminated on the system module using external 1% resistors. The output impedance and on die termination is updated during every AUTO REFRRESH commands to compensate for variations in supply voltage and temperature. The output impedance updates are transparent to the system. Impedance updates do not affect device operation, and all datasheet timings and current specifications are met during an update. A maximum of eight AUTO REFRESH commands can be posted to any given GDDR3 SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 x 3.9us (31.2us). This maximum absolute interval guarantees that the output drivers and the on die terminations of GDDR3 SDRAMs are recalibrated often enough to keep the impedance characteristics of those within the specified boundaries. ODT Control Bus snooping for READ commands other than CS# is used to control the on die termination in the dual load configuration. The GDDR3 SGRAM will disable the DQ and RDQS on die termination when a READ command is detected regardless of the state of CS#. The on die termination is disabled x clocks after the READ command where x equals CL-1 and stay off for a duration of BL/2+2CK. In a two-rank system, both DRAM devices snoop the bus for READ commands to either device and both will disable the on die termination, for the DQ and DQS pins if a READ command is detected. The on die termination for all other pins on the device is always turned-on for both a single-rank system and a dual-rank system unless it is turned off in the EMRS. Only DQ,WDQS and DM pins can turn off through the EMRS. Rev.1.5 / Jul. 2008 9 H5RS5223CFR Mode Register Definition The mode register is used to define the specific mode of operation of the GDDR3 SDRAM. This definition includes the selection of a burst length, CAS latency, WRITE latency, and operating mode, as shown in Figure 3, Mode Register Definition, on page 11. The mode register is programmed via the MODE REGISTER SET command (with BA0=0, BA1=0 and BA2=0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Re-programming the mode register will not alter the contents of the memory. The mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A2-A0 specify the burst length; A3 specifies the type of burst (sequential); A4-A6 specify the CAS latency; A7 is a test mode; A8 specifies the operating mode; and A9-A11 specifiy the WRITE latency. Rev.1.5 / Jul. 2008 10 H5RS5223CFR Figure 3: Mode Register Definition BA1 0 BA0 0 A11 A10 WL A9 A8 DR A7 TM A6 A5 A4 A3 BT A2 CL A1 A0 CAS Latency Burst Length A8 0 1 DLL Reset No Yes A3 0 1 Burst Type Sequential Reserved A1 A7 0 1 Test Mode Normal Yes 0 0 1 1 A0 0 1 0 1 Burst Length Reserved Reserved 4 8 A11 0 0 0 0 1 1 1 1 A10 0 0 1 1 0 0 1 1 A9 0 1 0 1 0 1 0 1 WRITE Latency Reserved 1 2 3 4 5 6 Reserved A2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 A6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CAS Latency 8 9 10 11 4 5 6 7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Note: 1) The DLL reset command is self-clearing. 1 Rev.1.5 / Jul. 2008 11 H5RS5223CFR Burst Length Read and write accesses to the GDDR3 SDRAM are burst-oriented, with the burst length being programmable, as shown in Figure3, Mode Register Definition. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 4 or 8 locations are available for the sequential burst type. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2. Ai when the burst length is set to four and by A3. Ai when the burst length is set to eight(where Ai is the most significant column address bit for a given configuration). The remaining(least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both read and write bursts. Burst Type Accesses within a given burst must be programmed to be sequential; this is referred to as the burst type and is selected via bit A3. This device does not support the interleaved burst mode found in DDR SDRAM devices. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table3. Table 3: Burst Definition Burst1, 2 Length Starting Column Address Order of Accesses Within a Burst Type=Sequential A1 0 A2 8 0 1 A1 0 0 A0 0 A0 0 0 0-1-2-3-4-5-6-7 4-5-6-7-0-1-2-3 0-1-2-3 4 NOTE: 1. For a burst length of four, A2-A7 select the block of four burst; A0-A1 select the starting column within the block and must be set to zero. 2. For a burst length of eight, A3-A7 select the of eight burst; A0-A2 select the starting column within the block. Rev.1.5 / Jul. 2008 12 H5RS5223CFR CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 7-11 clocks, as shown in Figure 4, CAS Latency, on page 13. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table4 indicates the operating frequencies at which each CAS latency setting can be used. For the proper operation, do not change the CL without DLL reset. Or proper CL should be set with DLL reset code Reserved states should not be used as unknown operation or incompatibility with future versions may result. Table 4: CAS Latency ALLOWABLE OPERATING FREQUENCY (MHz) SPEED -N3 -N2 -N0 -11 -14(L) -18 -20 CL=11