H5TQ1G83AFP

H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 1Gb DDR3 SDRAM H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC ** Contents are subject to change at any time without notice. Rev. 0.4 / January 2009 This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. 1 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Revision History Revision No. 0.01 0.02 0.1 0.2 0.3 0.4 History Preliminary Initial Release IDD Added Revision 0.1 specification Release Added Halogen free products Applied New IDD definition Notation change of package outline Draft Date Nov. 2007 March 2008 April 2008 April 2008 Sep 2008 Jan 2009 Remark Preliminary Preliminary Rev. 0.4 /January 2009 2 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Table of Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.1.3 Operating Frequency 1.2 Package Ballout / Mechanical Dimension 1.2.1 x4 Package Ball out 1.2.2 x8 Package Ball out 1.2.3 x16 Package Ball out 1.3 Row and Column Address Table: 1G/2G/4G/8G 1.4 Pin Functional Description 2. Command Description 2.1 Command Truth Table 2.2 Clock Enable (CKE) Truth Table for Synchronous Transitions 3. Absolute Maximum Ratings 4. Operating Conditions 4.1 Operating Temperature Condition 4.2 DC Operating Conditions 5. AC and DC Input Measurement Levels 5.1 AC and DC Logic Input Levels for Single-Ended Signals 5.2 AC and DC Logic Input Levels for Differential Signals 5.3 Differential Input Cross Point Voltage 5.4 Slew Rate Definitions for Single Ended Input Signals 5.4.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS) 5.4.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH) 5.5 Slew Rate Definitions for Differential Input Signals Rev. 0.4 /January 2009 3 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 6. AC and DC Output Measurement Levels 6.1 Single Ended AC and DC Output Levels 6.1.1 Differential AC and DC Output Levels 6.2 Single Ended Output Slew Rate 6.3 Differential Output Slew Rate 6.4 Reference Load for AC Timing and Output Slew Rate 7. Overshoot and Undershoot Specifications 7.1 Address and Control Overshoot and Undershoot Specifications 7.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications 7.3 34 ohm Output Driver DC Electrical Characteristics 7.4 Output Driver Temperature and Voltage sensitivity 7.5 On-Die Termination (ODT) Levels and I-V Characteristics 7.5.1 On-Die Termination (ODT) Levels and I-V Characteristics 7.5.2 ODT DC Electrical Characteristics 7.5.3 ODT Temperature and Voltage sensitivity 7.6 ODT Timing Definitions 7.6.1 Test Load for ODT Timings 7.6.2 ODT Timing Reference Load 8. IDD Specification Parameters and Test Conditions 8.1 IDD Measurement Conditions 8.2 IDD Specifications 8.2.1 IDD6 Current Definition 8.2.2 IDD6TC Specification (see notes 1~2) 9. Input/Output Capacitance 10. Standard Speed Bins 11. Electrical Characteristics and AC Timing 12. Package Dimensions Rev. 0.4 /January 2009 4 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 1. DESCRIPTION The H5TQ1G43AFP-xxC, H5TQ1G83AFP-xxC and H5TQ1G63AFP-xxC are a 1,073,741,824-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. Hynix 1Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. 1.1 Device Features and Ordering Information 1.1.1 FEATURES • VDD=VDDQ=1.5V +/- 0.075V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 6, 7, 8, 9, and (10) supported • Programmable additive latency 0, CL-1, and CL-2 supported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8banks • 8K refresh cycles /64ms • JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16) • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • TDQS (Termination Data Strobe) supported (x8 only) • Write Levelization supported • Auto Self Refresh supported • On Die Thermal Sensor supported • 8 bit pre-fetch 1.1.2 ORDERING INFORMATION Part No. H5TQ1G43AFP*(R)-**xxC H5TQ1G83AFP*(R)-**xxC H5TQ1G63AFP*(R)-**xxC Configuration 256M x 4 128M x 8 64M x 16 Package 78ball FBGA 96ball FBGA 1.1.3 OPERATING FREQUENCY Grade -S6 -G7 -H9 Frequency [MHz] CL5 CL6 O O O O O O O O O O CL7 CL8 CL9 CL10 Remark (CL-tRCD-tRP) DDR3-800 6-6-6 DDR3-1066 7-7-7 DDR3-1333 9-9-9 * (R) means Halogen Free Products ** XX means Speed Bin Grade Rev. 0.4 /January 2009 5 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 1.2 Package Ballout/Mechanical Dimension 1.2.1 x4 Package Ball out (Top view): 78ball FBGA Package (no support balls) 1 A B C D E F G H J K L M N VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 1 2 VDD VSSQ DQ2 NC VDDQ VSS VDD CS BA0 A3 A5 A7 RESET 2 3 NC DQ0 DQS DQS NC RAS CAS WE BA2 A0 A2 A9 A13 3 4 5 6 4 5 6 7 NC DM DQ1 VDD NC CK CK A10/AP A15 A12/BC A1 A11 NC 7 8 VSS VSSQ DQ3 VSS NC VSS VDD ZQ VREFCA BA1 A4 A6 A8 8 9 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS 9 A B C D E F G H J K L M N Note: Green NC balls indicate mechanical support balls with no internal connection 123 A B C D E F G H J K L M N 789 (Top View: See the balls through the Package) Populated ball Ball not populated 1.4 Pin Functional Description Rev. 0.4 /January 2009 6 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 1.2 Package Ballout/Mechanical Dimension 1.2.2 x8 Package Ball out (Top view): 78ball FBGA Package (no support balls) 1 A B C D E F G H J K L M N VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 1 2 VDD VSSQ DQ2 DQ6 VDDQ VSS VDD CS BA0 A3 A5 A7 RESET 2 3 NC DQ0 DQS DQS DQ4 RAS CAS WE BA2 A0 A2 A9 A13 3 4 5 6 4 5 6 7 NU/TDQS DM/TDQS DQ1 VDD DQ7 CK CK A10/AP NC A12/BC A1 A11 NC 7 8 VSS VSSQ DQ3 VSS DQ5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 8 9 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS 9 A B C D E F G H J K L M N Note: Green NC balls indicate mechanical support balls with no internal connection 123 A B C D E F G H J K L M N 789 (Top View: See the balls through the Package) Populated ball Ball not populated Rev. 0.4 /January 2009 7 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 1.2 Package Ballout/Mechanical Dimension 1.2.3 x16 Package Ball out (Top view): 96ball FBGA Package (no support balls) 1 A B C D E F G H J K L M N P R T VDDQ VSSQ VDDQ VSSQ VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 1 2 DQU5 VDD DQU3 VDDQ VSSQ DQL2 DQL6 VDDQ VSS VDD CS BA0 A3 A5 A7 RESET 2 3 DQU7 VSS DQU1 DMU DQL0 DQSL DQSL DQL4 RAS CAS WE BA2 A0 A2 A9 A13 3 4 5 6 4 5 6 7 DQU4 DQSU DQSU DQU0 DML DQL1 VDD DQL7 CK CK A10/AP A15 A12/BC A1 A11 NC 7 8 VDDQ DQU6 DQU2 VSSQ VSSQ DQL3 VSS DQL5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 8 9 VSS VSSQ VDDQ VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS 9 A B C D E F G H J K L M N P R T Note: Green NC balls indicate mechanical support balls with no internal connection 1 A B C D E F G H J K L M N P R T 2 3 7 8 9 (Top View: See the balls through the Package) Populated ball Ball not populated Rev. 0.4 /January 2009 8 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 1.3 ROW AND COLUMN ADDRESS TABLE 1Gb Configuration # of Banks Bank Address Auto precharge BL switch on the fly Row Address Column Address Page size 1 256Mb x 4 8 BA0 - BA2 A10/AP A12/BC A0 - A13 A0 - A9,A11 1 KB 128Mb x 8 8 BA0 - BA2 A10/AP A12/BC A0 - A13 A0 - A9 1 KB 64Mb x 16 8 BA0 - BA2 A10/AP A12/BC A0 - A12 A0 - A9 2 KB 2Gb Configuration # of Banks Bank Address Auto precharge BL switch on the fly Row Address Column Address Page size 1 512Mb x 4 8 BA0 - BA2 A10/AP A12/BC A0 - A14 A0 - A9,A11 1 KB 256Mb x 8 8 BA0 - BA2 A10/AP A12/BC A0 - A14 A0 - A9 1 KB 128Mb x 16 8 BA0 - BA2 A10/AP A12/BC A0 - A13 A0 - A9 2 KB 4Gb Configuration # of Banks Bank Address Auto precharge BL switch on the fly Row Address Column Address Page size 1 1Gb x 4 8 BA0 - BA2 A10/AP A12/BC A0 - A15 A0 - A9,A11 1 KB 512Mb x 8 8 BA0 - BA2 A10/AP A12/BC A0 - A15 A0 - A9 1 KB 256Mb x 16 8 BA0 - BA2 A10/AP A12/BC A0 - A14 A0 - A9 2 KB 8Gb Configuration # of Banks Bank Address Auto precharge BL switch on the fly Row Address Column Address Page size 1 2Gb x 4 8 BA0 - BA2 A10/AP A12/BC A0 - A15 A0 - A9, A11, A13 2 KB 1Gb x 8 8 BA0 - BA2 A10/AP A12/BC A0 - A15 A0 - A9, A11 2 KB 512Mb x 16 8 BA0 - BA2 A10/AP A12/BC A0 - A15 A0 - A9 2 KB Note1: Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: page size = 2 COLBITS * ORG ÷ 8 where COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits Rev. 0.4 /January 2009 9 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 1.4 Pin Functional Description Symbol CK, CK Type Input Function Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and SelfRefresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self-Refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/ TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x4/x8 configurations. For x16 configuration ODT is applied to each DQ, DQSU, DQSU, DQSL, DQSL, DMU, and DML signal. The ODT pin will be ignored if MR1 is programmed to disable ODT. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1. Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS cycle. Address Inputs: Provide the row address for Active commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions, see below). The address inputs also provide the op-code during Mode Register Set commands. Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. Burst Chop: A12 / BC is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details. Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH. RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low. CKE Input CS Input ODT Input RAS. CAS. WE DM, (DMU), (DML) Input Input BA0 - BA2 Input A0 - A15 Input A10 / AP Input A12 / BC Input RESET Input Rev. 0.4 /January 2009 10 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Symbol DQ Type Input / Output Function Data Input/ Output: Bi-directional data bus. Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data strobe DQS, DQSL, and DQSU are paired with differential signals DQS, DQSL, and DQSU, respectively, to provide differential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and does not support single-ended. Termination Data Strobe: TDQS/TDQS is applicable for x8 DRAMs only. When enabled via Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11 = 0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/x16 DRAMs must disable the TDQS function via mode register A11 = 0 in MR1. No Connect: No internal electrical connection is present. DQU, DQL, DQS, DQS, DQSU, DQSU, DQSL, DQSL Input / Output TDQS, TDQS Output NC VDDQ VSSQ VDD VSS VREFDQ VREFCA ZQ Supply Supply Supply Supply Supply Supply Supply DQ Power Supply: 1.5 V +/- 0.075 V DQ Ground Power Supply: 1.5 V +/- 0.075 V Ground Reference voltage for DQ Reference voltage Reference Pin for ZQ calibration Note: Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT, DM, and RESET) do not supply termination. Rev. 0.4 /January 2009 11 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 2. Command Description 2.1 Command Truth Table (a) note 1,2,3,4 apply to the entire Command Truth Table (b) Note 5 applies to all Read/Write command [BA = Bank Address, RA = Rank Address, CA = Column Address, BC = Burst Chop, X = Don’t Care, V = Valid] CKE Abbrev Previ Curre iation ous nt Cycle Cycle MRS REF SRE SRX PRE PREA ACT WR WRS4 WRS8 WRA WRAS 4 WRAS 8 RD RDS4 RDS8 RDA H H H L H H H H H H H H H L H H H H H H H H Function CS RAS CAS WE BA0- A13- A12- A10- A0A9, BA3 A15 BC AP A11 BA V V V BA V BA BA BA BA BA V V V V V RFU RFU RFU RFU OP Code V V V V V V L H V V V V L H L L L H V V V V V CA CA CA CA Notes Mode Register Set Refresh Self Refresh Entry Self Refresh Exit Single Bank Precharge Precharge all Banks Bank Activate Write (Fixed BL8 or BC4) Write (BC4, on the Fly) Write (BL8, on the Fly) Write with Auto Precharge (Fixed BL8 or BC4) Write with Auto Precharge (BC4, on the Fly) Write with Auto Precharge (BL8, on the Fly) Read (Fixed BL8 or BC4) Read (BC4, on the Fly) Read (BL8, on the Fly) Read with Auto Precharge (Fixed BL8 or BC4) Read with Auto Precharge (BC4, on the Fly) Read with Auto Precharge (BL8, on the Fly) No Operation Device Deselected Power Down Entry L L L H L L L L L L L L L L L V H L L L H H H H L L L V H H H H L L L L L H H V H L L H L L L L 7,9,12 7,8,9,1 2 Row Address (RA) H H L H L L BA RFU L H CA H H H H H H H H H H L L L L L H H H H H L L L L L L H H H H BA BA BA BA BA RFU RFU RFU RFU RFU H V L H V H L L L H CA CA CA CA CA RDAS4 H H L H L H BA RFU L H CA RDAS8 NOP DES PDE H H H H H H H L L L H L H H H X H V L H X H V H H X H V BA V X V RFU V X V H V X V H V X V CA V X V 10 11 6,12 Rev. 0.4 /January 2009 12 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC CKE Function Abbrev Previ Curre iation ous nt Cycle Cycle PDX ZQCL ZQCS L H H H H H CS RAS CAS WE BA0- A13- A12- A10- A0A9, BA3 A15 BC AP A11 Notes Power Down Exit ZQ Calibration Long ZQ Calibration Short Notes: L H L L H V H H H V H H H V L L V X X V X X V X X V H L V X X 6,12 1. All DDR3 SDRAM commands are defined by states of CS, RAS, CAS, WE and CKE at the rising edge of the clock. The MSB of BA, RA and CA are device density and configuration dependant. 2. RESET is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any function. 3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register. 4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”. 5. Burst reads or writes cannot be terminated or interrupted and Fixed/on the Fly BL will be defined by MRS. 6. The Power Down Mode does not perform any refresh operation. 7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 8. Self Refresh Exit is asynchronous. 9. VREF (Both VrefDQ and VrefCA) must be maintained during Self Refresh operation. 10. The No Operation command should be used in cases when the DDR3 SDRAM is in an idle or wait state. The purpose of the No Operation command (NOP) is to prevent the DDR3 SDRAM from registering any unwanted commands between operations. A No Operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 11. The Deselect command performs the same function as No Operation command. 12. Refer to the CKE Truth Table for more detail with CKE transition. Rev. 0.4 /January 2009 13 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 2.2 CKE Truth Table a) Notes 1-7 apply to the entire CKE Truth Table. b) CKE low is allowed only if tMRD and tMOD are satisfied. CKE Current State 2 Previous Cycle1 (N-1) L L L L H H H H H H H Current Cycle1 (N) L H L H L L L L L L L Command (N)3 RAS, CAS, WE, CS X DESELECT or NOP X DESELECT or NOP DESELECT or NOP DESELECT or NOP DESELECT or NOP DESELECT or NOP DESELECT or NOP DESELECT or NOP REFRESH Action (N)3 Notes Power-Down Self-Refresh Bank(s) Active Reading Writing Precharging Refreshing All Banks Idle Maintain Power-Down Power-Down Exit Maintain Self-Refresh Self-Refresh Exit Active Power-Down Entry Power-Down Entry Power-Down Entry Power-Down Entry Precharge Power-Down Entry Precharge Power-Down Entry Self-Refresh 14, 15 11,14 15,16 8,12,16 11,13,14 11,13,14,17 11,13,14,17 11,13,14,17 11 11,13,14,18 9,13,18 10 For more details with all signals See “2.1 Command Truth Table” on page 12.. Notes: 1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. 2. Current state is defined as the state of the DDR3 SDRAM immediately prior to clock edge N. 3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is not included here. 4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self-Refresh. 6. tCKEmin of [TBD] clocks means CKE must be registered on [TBD] consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the [TBD] clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + [TBD] + tIH. 7. DESELECT and NOP are defined in the Command Truth Table. 8. On Self-Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS period. Read or ODT commands may be issued only after tXSDLL is satisfied. 9. Self-Refresh mode can only be entered from the All Banks Idle state. 10. Must be a legal command as defined in the Command Truth Table. 11. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only. 12. Valid commands for Self-Refresh Exit are NOP and DESELECT only. 13. Self-Refresh can not be entered during Read or Write operations. For a detailed list of restrictions see 8.1 on page 41. 14. The Power-Down does not perform any refresh operations. 15. “X” means “don’t care” (including floating around VREF) in Self-Refresh and Power-Down. It also applies to Address pins. 16. VREF (Both Vref_DQ and Vref_CA) must be maintained during Self-Refresh operation. 17. If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power-Down is entered, otherwise Active Power-Down is entered. 18. ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high, and all timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as all Self-Refresh exit and Power-Down Exit parameters are satisfied (tXS, tXP, tXPDLL, etc). Rev. 0.4 /January 2009 14 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 3. ABSOLUTE MAXIMUM RATINGS Symbol VDD VDDQ Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Rating - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V -55 to +100 Units V V V ,2 Notes ,3 ,3 VIN, VOUT Voltage on any pin relative to Vss TSTG Notes: Storage Temperature 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than 0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. Rev. 0.4 /January 2009 15 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 4. Operating Conditions 4.1 OPERATING TEMPERATURE CONDITION Symbol TOPER Notes: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. (This double refresh requirement may not apply for some devices.) It is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to supplier data sheet and/or the DIMM SPD for option availability. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Parameter Operating Temperature (Tcase) Extended Temperature Range Rating 0 to 85 85 to 95 Units o o Notes 2 1,3 C C 4.2 RECOMMENDED DC OPERATING CONDITIONS Rating Symbol VDD VDDQ Notes: 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. Parameter Min. Supply Voltage Supply Voltage for Output 1.425 1.425 Typ. 1.500 1.500 Max. 1.575 1.575 V V 1,2 1,2 Units Notes Rev. 0.4 /January 2009 16 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 5. AC and DC Input Measurement Levels 5.1 AC and DC Logic Input Levels for Single-Ended Signals Single Ended AC and DC Input Levels DDR3-800, DDR3-1066, DDR3-1333 Min VIH(DC) VIL(DC) VIH(AC) VIL(AC) DC input logic high DC input logic low AC input logic high AC input logic low 0.49 * VDD 0.49 * VDD VDDQ/2 - TBD Vref + 0.100 TBD Vref + 0.175 Max TBD Vref - 0.100 Vref - 0.175 0.51 * VDD 0.51 * VDD VDDQ/2 + TBD V V V V V V 1 1 1, 2 1, 2 3, 4 3, 4 Symbol Parameter Unit Notes VRefDQ(DC) Reference Voltage for DQ, DM inputs VRefCA(DC) Reference Voltage for ADD, CMD inputs VTT Termination voltage for DQ, DQS outputs Notes: 1. For DQ and DM, Vref = VrefDQ. For input any pins except RESET, Vref = VrefCA. 2. The “t.b.d.” entries might change based on overshoot and undershoot specification. 3. The ac peak noise on VRef may not allow VRef to deviate from VRef(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). 4. For reference: approx. VDD/2 +/- 15 mV. The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in below Figure. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise). VRef (DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in Table. Furthermore VRef (t) may temporarily deviate from VRef (DC) by no more than +/- 1% VDD. voltage VDD VRef ac-noise VRef(DC) VRef(t) VRef(DC)max VDD/2 VRef(DC)min VSS time Illustration of Vref (DC) tolerance and Vref ac-noise limits Rev. 0.4 /January 2009 17 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 5.2 AC and DC Logic Input Levels for Differential Signals DDR3-800, DDR3-1066, DDR3-1333 Min Symbol Parameter Unit V V Notes 1 1 Max - 0.200 VIHdiff VILdiff Differential input logic high Differential input logic low + 0.200 Note1. Refer to “Overshoot and Undershoot Specification on page 25” 5.3 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements below table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the midlevel between of VDD and VSS. VDD CK, DQS VIX VDD/2 VIX VIX CK, DQS VSS Vix Definition Cross point voltage for differential input signals (CK, DQS) DDR3-800, DDR3-1066, DDR3-1333 Min Symbol Parameter Unit Notes Max 150 mV VIX Differential Input Cross Point Voltage relative to VDD/2 - 150 Rev. 0.4 /January 2009 18 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 5.4 Slew Rate Definitions for Single Ended Input Signals 5.4.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS) Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VRef and the first crossing of VIH (AC) min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VRef and the first crossing of VIL (AC) max. 5.4.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH) Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (DC) max and the first crossing of VRef. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH (DC) min and the first crossing of VRef. Single-Ended Input Slew Rate Definition Measured Description Min Max VIH (AC) min VIL (AC) max Vref Vref Defined by VIH (AC) min-Vref Delta TRS Vref-VIL (AC) max Delta TFS Vref-VIL (DC) max Delta TFH VIH (DC) min-Vref Delta TRH Applicable for Input slew rate for rising edge Input slew rate for falling edge Input slew rate for rising edge Vref Vref VIL (DC) max Setup (tIS, tDS) Hold (tIH, tDH) Input slew rate for falling edge VIH (DC) min Input Nominal Slew Rate Definition for Single-Ended Signals P a rt A : S e t u p D e lt a T R S Single Ended input Voltage(DQ,ADD, CMD) v I H ( A C ) m in v I H ( D C ) m in v R e fD Q o r v R e fC A v IH (D C )m a x v IH (A C )m a x D e lt a T F S P a r t B : H o ld D e lt a T R H Single Ended input Voltage(DQ,ADD, CMD) v I H ( A C ) m in v I H ( D C ) m in v R e fD Q o r v R e fC A v IH (D C )m a x v IH (A C )m a x D e lt a T F H F ig u r e 8 2 ? I n p u t N o m in a l S le w R a t e D e f in it io n f o r S in g le - E n d e d S ig n a ls Rev. 0.4 /January 2009 19 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 5.5 Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in Table and Figure . Measured Description Min Max VIHdiffmin VILdiffmax Defined by VIHdiffmin-VILdiffmax DeltaTRdiff VIHdiffmin-VILdiffmax DeltaTFdiff Differential input slew rate for rising edge (CK-CK and DQS-DQS) Differential input slew rate for falling edge (CK-CK and DQS-DQS) VILdiffmax VIHdiffmin Note: The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds. Differential Input Voltage (i.e. DQS-DQS; CK-CK) Delta TRdiff vIHdiffmin 0 vILdiffmax Delta TFdiff Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# Rev. 0.4 /January 2009 20 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 6. AC and DC Output Measurement Levels 6.1 Single Ended AC and DC Output Levels Table shows the output levels used for measurements of single ended signals. Symbol VOH(DC) VOM(DC) VOL(DC) VOH(AC) VOL(AC) Parameter DC output high measurement level (for IV curve linearity) DC output mid measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) AC output high measurement level (for output SR) DDR3-800, 1066, 1333 0.8 x VDDQ 0.5 x VDDQ 0.2 x VDDQ VTT + 0.1 x VDDQ Unit V V V V 1 Notes VTT - 0.1 x VDDQ V 1 AC output low measurement level (for output SR) 1. The swing of ± 0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ / 2. 6.1.1 Differential AC and DC Output Levels Below table shows the output levels used for measurements of differential signals. Symbol VOHdiff (AC) Parameter AC differential output high measurement level (for output SR) DDR3-800, 1066, 1333 + 0.2 x VDDQ Unit Notes V 1 VOLdiff (AC) AC differential output low measurement level (for output SR) - 0.2 x VDDQ V 1 1. The swing of ± 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ/2 at each of the differential outputs. 6.2 Single Ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table and Figure. Measured Description From Single ended output slew rate for rising edge VOL(AC) To VOH(AC)-VOL(AC) VOH(AC) DeltaTRse VOH(AC)-VOL(AC) Single ended output slew rate for falling edge VOH(AC) VOL(AC) DeltaTFse Defined by Note: Output slew rate is verified by design and characterisation, and may not be subject to production test. Rev. 0.4 /January 2009 21 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Fig. Single Ended Output Slew Rate Definition Delta TRse Single Ended Output Voltage(l.e.DQ) vOH(AC) V∏ vOl(AC) Delta TFse Single Ended Output Slew Rate Definition Table. Output Slew Rate (single-ended) DDR3-800 Parameter Symbol Min DDR3-1066 Min DDR3-1333 Units Max 5 Max 5 Min Max 5 V/ns Single-ended Output Slew Rate *** For Ron = RZQ/7 setting SRQse 2.5 2.5 2.5 Rev. 0.4 /January 2009 22 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 6.3 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in Table and Figure . Differential Output Slew Rate Definition Measured Description From Differential output slew rate for rising edge Differential output slew rate for falling edge VOLdiff (AC) VOHdiff (AC) To VOHdiff (AC) VOLdiff (AC) VOHdiff (AC)-VOLdiff (AC) DeltaTRdiff VOHdiff (AC)-VOLdiff (AC) DeltaTFdiff Defined by Note: Output slew rate is verified by design and characterization, and may not be subject to production test. Delta TRdiff vOHdiff(AC) Differential Output Voltage(i.e. DQS-DQS) O vOLdiff(AC) Delta TFdiff Differential Output Slew Rate Definition Fig. Differential Output Slew Rate Definition Table. Differential Output Slew Rate DDR3-800 Parameter Symbol Min DDR3-1066 Min DDR3-1333 Units Max 10 Max 10 Min Max 10 V/ns Differential Output Slew Rate ***For Ron = RZQ/7 setting SRQdiff 5 5 5 Rev. 0.4 /January 2009 23 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 6.4 Reference Load for AC Timing and Output Slew Rate Figure represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. VDDQ CK, CK DUT DQ DQS DQS 25 Ohm VTT = VDDQ/2 Reference Load for AC Timing and Output Slew Rate Rev. 0.4 /January 2009 24 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 7. Overshoot and Undershoot Specifications 7.1 Address and Control Overshoot and Undershoot Specifications Table. AC Overshoot/Undershoot Specification for Address and Control Pins Specification DDR3-800 0.4V 0.4V 0.67 V-ns 0.67 V-ns DDR3-1066 0.4V 0.4V 0.5 V-ns 0.5 V-ns DDR3-1333 0.4V 0.4V 0.4 V-ns 0.4 V-ns Description Maximum peak amplitude allowed for overshoot area (see Figure) Maximum peak amplitude allowed for undershoot area (see Figure) Maximum overshoot area above VDD (See Figure) Maximum undershoot area below VSS (See Figure) M a x im u m A m p litu d e O v e rs h o o t A re a VDD VSS U n d e rs h o o t A re a M a x im u m A m p litu d e T im e (n s ) A d d re s s a n d C o n tro l O v e rs h o o t a n d U n d e rs h o o t D e fin itio n Rev. 0.4 /January 2009 25 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 7.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications Table. AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask Specification DDR3-800 0.4V 0.4V 0.25 V-ns 0.25 V-ns DDR3-1066 0.4V 0.4V 0.19 V-ns 0.19 V-ns DDR3-1333 0.4V 0.4V 0.15 V-ns 0.15 V-ns Description Maximum peak amplitude allowed for overshoot area (see Figure) Maximum peak amplitude allowed for undershoot area (see Figure) Maximum overshoot area above VDDQ (See Figure) Maximum undershoot area below VSSQ (See Figure) M a x im u m A m p litu d e O v e rsh o o t A re a V o lts (V ) VDDQ VSSQ U n d e rsh o o t A re a M a x im u m A m p litu d e T im e (n s) C lo c k , D a ta S tro b e a n d M a sk O v e rsh o o t a n d U n d e rsh o o t D e fin itio n Rev. 0.4 /January 2009 26 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 7.3 34 ohm Output Driver DC Electrical Characteristics A functional representation of the output buffer is shown in Figure . Output driver impedance RON is defined by the value of the external reference resistor RZQ as follows: RON34 = RZQ / 7 (nominal 34.3 W ±10% with nominal RZQ = 240 W ± 1%) The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows: V DDQ – V Out RON Pu = -------------------------------------I Out V Out RON Pd = -------------I Out under the condition that RONPd is turned off under the condition that RONPu is turned off Chip in Drive Mode Output Driver VDDQ Ipu To other Circuitry Like RCV, ... RONpu DQ RONpd Ipd Iout Vout VSSQ Output Driver: Definition of Voltages and Currents Rev. 0.4 /January 2009 27 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Output Driver DC Electrical Characteristics, assuming RZQ = 240 Ω ; entire operating temperature range; after proper ZQ calibration RONNom Resistor VOut VOLdc = 0.2 × VDDQ VOMdc = 0.5 × VDDQ VOHdc = 0.8 × VDDQ VOLdc = 0.2 × VDDQ VOMdc = 0.5 × VDDQ VOHdc = 0.8 × VDDQ VOMdc 0.5 × VDDQ min 0.6 0.9 0.9 0.9 0.9 0.6 -10 nom 1.0 1.0 1.0 1.0 1.0 1.0 max 1.1 1.1 1.4 1.4 1.1 1.1 +10 Unit Notes 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 4 RON34Pd 34 Ω RON34Pu Mismatch between pull-up and pull-down, RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 % MMPuPd Notes: 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS. 3. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 x VDDQ and 0.8 x VDDQ. 4. Measurement definition for mismatch between pull-up and pull-down, MMPuPd: Measure RONPu and RONPd, both at 0.5 x VDDQ: RON Pu – RON Pd MM PuPd = ------------------------------------------------- x 100 RON Nom 7.4 Output Driver Temperature and Voltage sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to Table and Table . DT = T - T (@calibration); DV= VDDQ - VDDQ (@calibration); VDD = VDDQ dRONdT and dRONdV are not subject to production test but are verified by design and characterization. Output Driver Sensitivity Definition min RONPU@ VOHdc RON@ VOMdc RONPD@ VOLdc 0.6 - dRONdTH*|∆T| - dRONdVH*|∆V| 0.9 - dRONdTM*|∆T| - dRONdVM*|∆V| 0.6 - dRONdTL*|∆T| - dRONdVL*|∆V| max 1.1 + dRONdTH*|∆T| + dRONdVH*|∆V| 1.1 + dRONdTM*|∆T| + dRONdVM*|∆V| 1.1 + dRONdTL*|∆T| + dRONdVL*|∆V| unit RZQ/7 RZQ/7 RZQ/7 Output Driver Voltage and Temperature Sensitivity min dRONdTM dRONdVM dRONdTL dRONdVL Rev. 0.4 /January 2009 max 1.5 0.15 1.5 TBD unit %/oC %/mV %/oC %/mV 28 0 0 0 0 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Output Driver Voltage and Temperature Sensitivity min dRONdTH dRONdVH 0 0 max 1.5 TBD unit %/oC %/mV These parameters may not be subject to production test. They are verified by design and characterization. 7.5 On-Die Termination (ODT) Levels and I-V Characteristics 7.5.1 On-Die Termination (ODT) Levels and I-V Characteristics On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of the MR1 Register. ODT is applied to the DQ, DM, DQS/DQS and TDQS/TDQS (x8 devices only) pins. A functional representation of the on-die termination is shown in Figure . The individual pull-up and pull-down resistors (RTTPu and RTTPd) are defined as follows: V DDQ – V Out RTT Pu = --------------------------------I Out V Out RTT Pd = -----------I Out under the condition that RTTPd is turned off under the condition that RTTPu is turned off C h ip in T e r m in a t io n M o d e ODT VDDQ Ip u To o th e r C ir c u it r y L ik e RCV, . .. RTTpu Io u t = Ip d -Ip u DQ RTTpd Ip d Io u t Vout VSSQ IO _ C T T _ D E F IN IT IO N _ 0 1 O n - D ie T e r m in a t io n : D e f in it io n o f V o lt a g e s a n d C u r r e n t s Rev. 0.4 /January 2009 29 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 7.5.2 ODT DC Electrical Characteristics A below table provides an overview of the ODT DC electrical characteristics. The values for RTT60Pd120, RTT60Pu120, RTT120Pd240, RTT120Pu240, RTT40Pd80, RTT40Pu80, RTT30Pd60, RTT30Pu60, RTT20Pd40, RTT20Pu40 are not specification requirements, but can be used as design guide lines: ODT DC Electrical Characteristics, assuming RZQ = 240 Ω +/- 1% entire operating temperature range; after proper ZQ calibration MR1 A9, A6, A2 RTT Resistor VOut VOLdc 0.2 × VDDQ RTT120Pd240 0.5 × VDDQ VOHdc 0.8 × VDDQ 0, 1, 0 120 Ω RTT120Pu240 VOLdc 0.2 × VDDQ 0.5 × VDDQ VOHdc 0.8 × VDDQ RTT120 VIL(ac) to VIH(ac) VOLdc 0.2 × VDDQ RTT60Pd120 0.5 × VDDQ VOHdc 0.8 × VDDQ 0, 0, 1 60 Ω RTT60Pu120 VOLdc 0.2 × VDDQ 0.5 × VDDQ VOHdc 0.8 × VDDQ RTT60 VIL(ac) to VIH(ac) min 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 nom 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 max 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 Unit RZQ RZQ RZQ RZQ RZQ RZQ RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/4 Notes 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 5) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 5) Rev. 0.4 /January 2009 30 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC ODT DC Electrical Characteristics, assuming RZQ = 240 Ω +/- 1% entire operating temperature range; after proper ZQ calibration MR1 A9, A6, A2 RTT Resistor VOut VOLdc 0.2 × VDDQ RTT40Pd80 0.5 × VDDQ VOHdc 0.8 × VDDQ 0, 1, 1 40 Ω RTT40Pu80 VOLdc 0.2 × VDDQ 0.5 × VDDQ VOHdc 0.8 × VDDQ RTT40 VIL(ac) to VIH(ac) VOLdc 0.2 × VDDQ RTT30Pd60 0.5 × VDDQ VOHdc 0.8 × VDDQ 1, 0, 1 30 Ω RTT30Pu60 VOLdc 0.2 × VDDQ 0.5 × VDDQ VOHdc 0.8 × VDDQ RTT30 VIL(ac) to VIH(ac) VOLdc 0.2 × VDDQ RTT20Pd40 0.5 × VDDQ VOHdc 0.8 × VDDQ 1, 0, 0 20 Ω RTT20Pu40 VOLdc 0.2 × VDDQ 0.5 × VDDQ VOHdc 0.8 × VDDQ RTT20 Deviation of VM w.r.t. VDDQ/2, DVM VIL(ac) to VIH(ac) min 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 -5 nom 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 max 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 +5 Unit RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/6 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/8 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/12 % Notes 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 5) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 5) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 3) 4) 1) 2) 5) 1) 2) 5) 6) The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5 x VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 x VDDQ and 0.8 x VDDQ. Not a specification requirement, but a design guide line. Measurement definition for RTT: Rev. 0.4 /January 2009 31 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Apply VIH (ac) to pin under test and measure current I(VIH (ac)), then apply VIL (ac) to pin under test and measure current I(VIL (ac)) respectively. V IH(ac) – V IL(ac) RTT = -------------------------------------------------------I (VIH(ac)) – I (VIL(ac)) Measurement definition for VM and DVM: Measure voltage (VM) at test pin (midpoint) with no load: 2 • VM ∆V M = ⎛ ----------------- – 1⎞ • 100 ⎝V ⎠ DDQ 7.5.3 ODT Temperature and Voltage sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to Table and Table . DT = T - T (@calibration); DV= VDDQ - VDDQ (@calibration); VDD = VDDQ ODT Sensitivity Definition min RTT 0.9 - dRTTdT*|∆T| - dRTTdV*|∆V| max 1.6 + dRTTdT*|∆T| + dRTTdV*|∆V| unit RZQ/2,4,6,8,12 ODT Voltage and Temperature Sensitivity min dRTTdT dRTTdV 0 0 max 1.5 0.15 unit %/oC %/mV These parameters may not be subject to production test. They are verified by design and characterization Rev. 0.4 /January 2009 32 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 7.6 ODT Timing Definitions 7.6.1 Test Load for ODT Timings Different than for timing measurements, the reference load for ODT timings is defined in Figure . VDDQ DUT CK, CK DQ, DM DQS, DQS TDQS, TDQS RTT = 25 Ω VTT = VSSQ VSSQ Timing Reference Points BD_REFLOAD_ODT 7.6.2 ODT Timing Reference Load ODT Timing Definitions Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in the table and subsequent figures. Measurement reference settings are provided in the table. ODT Timing Definitions Symbol tAON tAONPD tAOF tAOFPD tADC Begin Point Definition Rising edge of CK - CK defined by the end point of ODTLon Rising edge of CK - CK with ODT being first registered high Rising edge of CK - CK defined by the end point of ODTLoff Rising edge of CK - CK with ODT being first registered low Rising edge of CK - CK defined by the end point of ODTLcnw, ODTLcwn4 or ODTLcwn8 End Point Definition Extrapolated point at VSSQ Extrapolated point at VSSQ End point: Extrapolated point at VRTT_Nom End point: Extrapolated point at VRTT_Nom End point: Extrapolated point at VRTT_Wr and VRTT_Nom respectively Figure Figure Figure Figure Figure Figure Reference Settings for ODT Timing Measurements Measured Parameter tAON tAONPD tAOF tAOFPD tADC RTT_Nom Setting RZQ/4 RZQ/12 RZQ/4 RZQ/12 RZQ/4 RZQ/12 RZQ/4 RZQ/12 RZQ/12 RTT_Wr Setting NA NA NA NA NA NA NA NA RZQ/2 VSW1 [V] 0.05 0.10 0.05 0.10 0.05 0.10 0.05 0.10 0.20 VSW2 [V] 0.10 0.20 0.10 0.20 0.10 0.20 0.10 0.20 0.30 Note Rev. 0.4 /January 2009 33 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Begin point: Rising edge of CK - CK defined by the end point of ODTLon CK VTT CK t AON TSW2 DQ, DM DQS, DQS TDQS, TDQS T SW1 VSW2 VSW1 VSSQ VSSQ End point: Extrapolated point at VSSQ TD_TAON_DEF Definition of tAON Begin point: Rising edge of CK - CK with ODT being first registered high CK VTT CK t AONPD T SW2 DQ, DM DQS, DQS TDQS, TDQS T SW1 VSW2 VSSQ VSW1 VSSQ End point: Extrapolated point at VSSQ TD_TAONPD_DEF Definition of tAONPD Rev. 0.4 /January 2009 34 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Begin point: Rising edge of CK - CK defined by the end point of ODTLoff CK VTT CK t AOF VRTT_Nom End point: Extrapolated point at VRTT_Nom T SW2 DQ, DM DQS, DQS TDQS, TDQS T SW1 VSW2 VSW1 VSSQ TD_TAOF_DEF Definition of tAOF Begin point: Rising edge of CK - CK with ODT being first registered low CK VTT CK t AOFPD VRTT_Nom End point: Extrapolated point at VRTT_Nom T SW2 DQ, DM DQS, DQS TDQS, TDQS T SW1 VSW2 VSW1 VSSQ TD_TAOFPD_DEF Definition of tAOFPD Rev. 0.4 /January 2009 35 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Begin point: Rising edge of CK - CK defined by the end point of ODTLcnw Begin point: Rising edge of CK - CK defined by the end point of ODTLcwn4 or ODTLcwn8 CK VTT CK t ADC VRTT_Nom End point: DQ, DM Extrapolated DQS, DQS point at VRTT_Nom TDQS, TDQS tADC VRTT_Nom VSW2 T SW22 T SW12 T SW21 TSW11 VSW1 VRTT_Wr End point: Extrapolated point at VRTT_Wr VSSQ TD_TADC_DEF Definition of tADC Rev. 0.4 /January 2009 36 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 8. IDD and IDDQ Specification Parameters and Test Conditions 8.1 IDD and IDDQ Measurement Conditions In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 1. shows the setup and test load for IDD and IDDQ measurements. • IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents. IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB. • For IDD and IDDQ measurements, the following definitions apply: • • • • • • • ”0” and “LOW” is defined as VIN = VIHAC(max). “FLOATING” is defined as inputs are VREF - VDD/2. Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1 on Page 39. Basic IDD and IDDQ Measurement Conditions are described in Table 2 on page 42. Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 on page 42 through Table 10 on page 47. IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting RON = RZQ/7 (34 Ohm in MR1); Qoff = 0B (Output Buffer enabled in MR1); RTT_Nom = RZQ/6 (40 Ohm in MR1); RTT_Wr = RZQ/2 (120 Ohm in MR2); TDQS Feature disabled in MR1 Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started. Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW} Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH} • • • Rev. 0.4 /January 2009 37 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC IDD IDDQ (optional) VDD RESET CK/CK CKE CS RAS, CAS, WE A, BA ODT ZQ VDDQ DDR3 SDRAM DQS, DQS DQ, DM, TDQS, TDQS RTT = 25 Ohm VDDQ/2 VSS VSSQ Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements [Note: DIMM level Output test load condition may be different from above] Application specific memory channel environment IDDQ Test Load Channel IO Power Simulation IDDQ Simulation IDDQ Simulation Correction Channel IO Power Number Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement Rev. 0.4 /January 2009 38 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns Symbol tCK CL nRCD nRC nRAS nRP nFAW nRRD x4/x8 x16 x4/x8 x16 DDR3-800 5-5-5 2.5 5 5 20 15 5 16 20 4 4 36 44 64 120 140 DDR3-1066 7-7-7 1.875 7 7 27 20 7 20 27 4 6 48 59 86 160 187 DDR3-1333 9-9-9 1.5 9 9 33 24 9 20 30 4 5 60 74 107 200 234 Unit ns nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nRFC -512Mb nRFC-1 Gb nRFC- 2 Gb nRFC- 4 Gb nRFC- 8 Gb Table 2 -Basic IDD and IDDQ Measurement Conditions Symbol Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1 on page 39; BL: 8a); AL: 0; CS: High between IDD0 ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3 on page 42; Data IO: FLOATING; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3 on page 42); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3 on page 42 Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1 on page 39; BL: 8a); AL: 0; CS: High IDD1 between ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4 on page 43; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4 on page 43); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4 page 43 Precharge Standby Current CKE: High; External clock: On; tCK, CL: see Table 1 on page 39; BL: 8a); AL: 0; CS: stable at 1; Command, IDD2N Address, Bank Address Inputs: partially toggling according to Table 5 on page 44; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5 on page 44 Rev. 0.4 /January 2009 39 Description H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Precharge Standby ODT Current CKE: High; External clock: On; tCK, CL: see Table 1 on page 39; BL: 8a); AL: 0; CS: stable at 1; Command, IDD2NT Address, Bank Address Inputs: partially toggling according to Table 6 on page 44; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6 on page 44; Pattern Details: see Table 6 on page 44 IDDQ2NT Precharge Standby ODT IDDQ Current (optional) Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current Precharge Power-Down Current Slow Exit CKE: Low; External clock: On; tCK, CL: see Table 1 on page 39; BL: 8a); AL: 0; CS: stable at 1; Command, IDD2P0 Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc) Precharge Power-Down Current Fast Exit CKE: Low; External clock: On; tCK, CL: see Table 1 on page 39; BL: 8a); AL: 0; CS: stable at 1; Command, IDD2P1 Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc) Precharge Quiet Standby Current IDD2Q CKE: High; External clock: On; tCK, CL: see Table 1 on page 39; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 Active Standby Current CKE: High; External clock: On; tCK, CL: see Table 1 on page 39; BL: 8a); AL: 0; CS: stable at 1; Command, IDD3N Address, Bank Address Inputs: partially toggling according to Table 5 on page 44; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5 on page 44 Active Power-Down Current IDD3P CKE: Low; External clock: On; tCK, CL: see Table 1 on page 39; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 IDDQ4R Operating Burst Read IDDQ Current (optional) Same definition like for IDD4R, however measuring IDDQ current instead of IDD current Rev. 0.4 /January 2009 40 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 1 on page 39; BL: 8a); AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: partially toggling according to Table 7 on page 45; Data IO: seamless IDD4R read data burst with different data between one burst and the next one according to Table 7 on page 45; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7 on page 45); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7 on page 45 Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see Table 1 on page 39; BL: 8a); AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: partially toggling according to Table 8 on page 45; Data IO: seamless IDD4W read data burst with different data between one burst and the next one according to Table 8 on page 45; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8 on page 45); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8 on page 45 Burst Refresh Current CKE: High; External clock: On; tCK, CL, nRFC: see Table 1 on page 38; BL: 8a); AL: 0; CS: High between REF; IDD5B Command, Address, Bank Address Inputs: partially toggling according to Table 9 on page 45; Data IO: FLOATING; DM: stable at 0; Bank Activity: REF command every nREF (see Table 9 on page 45); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9 on page 45 Self-Refresh Current: Normal Temperature Range TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); IDD6 CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 4; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING Self-Refresh Current: Extended Temperature Range (optional)f) TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede); IDD6ET CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 4; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING Auto Self-Refresh Current (optional)f) TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Enabledd);Self-Refresh Temperature Range (SRT): Normale); CKE: IDD6TC Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 39; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING Rev. 0.4 /January 2009 41 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1 on page 39; BL: 8a); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling IDD7 according to Table 10 on page 47; Data IO: read data burst with different data between one burst and the next one according to Table 10 on page 47; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee Table 10 on page 47; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 10 on page 47 a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device Table 3 - IDD0 Measurement-Loop Patterna) Command Sub-Loop Cycle Number BA[2:0] A[15:11] CK, CK A[9:7] A[6:3] A[2:0] 0 0 0 0 0 0 A[10] ODT RAS CKE CAS WE CS Datab) 0 0 1,2 3,4 ... nRAS ... 1*nRC+0 ACT D, D D, D PRE ACT PRE 0 1 1 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 00 0 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F F - repeat pattern 1...4 until nRAS - 1, truncate if necessary repeat pattern 1...4 until nRC - 1, truncate if necessary repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary repeat pattern 1...4 until 2*nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead Static High toggling ... 1*nRC+nRAS ... 1 2 3 4 5 6 7 2*nRC 4*nRC 6*nRC 8*nRC 10*nRC 12*nRC 14*nRC a) DM must be driven LOW all the time. DQS, DQS are FLOATING. b) DQ signals are FLOATING. Rev. 0.4 /January 2009 42 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Table 4 - IDD1 Measurement-Loop Patterna) Command Sub-Loop Cycle Number BA[2:0] A[15:11] CK, CK A[9:7] A[6:3] A[2:0] 0 0 0 0 0 0 0 0 0 0 A[10] RAS ODT CKE CAS WE CS Datab) 0 0 1,2 3,4 ... nRCD ... nRAS ... 1*nRC+0 1*nRC+1,2 ACT D, D D, D RD PRE ACT D, D D, D RD PRE 0 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F F F F F 00000000 00110011 - repeat pattern 1...4 until nRCD - 1, truncate if necessary repeat pattern 1...4 until nRAS - 1, truncate if necessary repeat pattern 1...4 until nRC - 1, truncate if necessary Static High toggling 1*nRC+3,4 ... 1*nRC+nRCD ... 1*nRC+nRAS ... 1 2 3 4 5 6 7 2*nRC 4*nRC 6*nRC 8*nRC 10*nRC 12*nRC 14*nRC repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING. Rev. 0.4 /January 2009 43 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Table 5 - IDD2N and IDD3N Measurement-Loop Patterna) Command Sub-Loop Cycle Number BA[2:0] A[15:11] CK, CK A[9:7] A[6:3] A[2:0] 0 0 0 0 A[10] RAS ODT CKE CAS WE CS Datab) 0 0 1 2 3 D D D D 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F F - Static High toggling 1 2 3 4 5 6 7 4-7 8-11 12-15 16-19 20-23 24-17 28-31 repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead a) DM must be driven LOW all the time. DQS, DQS are FLOATING. b) DQ signals are FLOATING. Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna) Command Sub-Loop Cycle Number BA[2:0] A[15:11] CK, CK A[9:7] A[6:3] A[2:0] 0 0 0 0 A[10] RAS ODT CKE CAS WE CS Datab) 0 0 1 2 3 D D D D 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F F 00000000 Static High toggling 1 2 3 4 5 6 7 4-7 8-11 12-15 16-19 20-23 24-17 28-31 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7 a) DM must be driven LOW all the time. DQS, DQS are FLOATING. b) DQ signals are FLOATING. Rev. 0.4 /January 2009 44 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Table 7 - IDD4R and IDDQ24RMeasurement-Loop Patterna) Command Sub-Loop Cycle Number BA[2:0] A[15:11] CK, CK A[9:7] A[6:3] A[2:0] 0 0 0 0 0 0 A[10] RAS ODT CKE CAS WE CS Datab) 0 0 1 2,3 4 5 RD D D,D RD D D,D 0 1 1 0 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F F F 00000000 00110011 - Static High toggling 6,7 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7 a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING. Table 8 - IDD4W Measurement-Loop Patterna) Command Sub-Loop Cycle Number BA[2:0] A[15:11] CK, CK A[9:7] A[6:3] A[2:0] 0 0 0 0 0 0 A[10] ODT RAS CKE CAS WE CS Datab) 0 0 1 2,3 4 5 WR D D,D WR D D,D 0 1 1 0 1 1 1 0 1 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F F F 00000000 00110011 - Static High toggling 6,7 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7 a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise FLOATING. b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are FLOATING. Rev. 0.4 /January 2009 45 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Table 9 - IDD5B Measurement-Loop Patterna) Command Sub-Loop Cycle Number BA[2:0] A[15:11] CK, CK A[9:7] A[6:3] A[2:0] 0 0 0 A[10] RAS ODT CKE CAS WE CS Datab) 0 1 0 1.2 3,4 5...8 REF D, D D, D 0 1 1 0 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 F - repeat cycles 1...4, but BA[2:0] = 1 repeat cycles 1...4, but BA[2:0] = 2 repeat cycles 1...4, but BA[2:0] = 3 repeat cycles 1...4, but BA[2:0] = 4 repeat cycles 1...4, but BA[2:0] = 5 repeat cycles 1...4, but BA[2:0] = 6 repeat cycles 1...4, but BA[2:0] = 7 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary. Static High toggling 9...12 13...16 17...20 21...24 25...28 29...32 2 33...nRFC-1 a) DM must be driven LOW all the time. DQS, DQS are FLOATING. b) DQ signals are FLOATING. Rev. 0.4 /January 2009 46 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC Table 10 - IDD7 Measurement-Loop Patterna) ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9 Command Sub-Loop Cycle Number BA[2:0] A[15:11] CK, CK A[9:7] A[6:3] A[2:0] 0 0 0 0 0 0 A[10] ODT RAS CKE CAS WE CS Datab) 0 0 1 2 ... nRRD nRRD+1 nRRD+2 ... 2*nRRD 3*nRRD 4*nRRD ... nFAW nFAW+nRRD nFAW+2*nRRD nFAW+3*nRRD nFAW+4*nRRD ... 2*nFAW+0 2*nFAW+1 2&nFAW+2 2*nFAW+nRRD ACT RDA D ACT RDA D 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 00 00 00 00 00 00 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 F F F 00000000 00110011 - repeat above D Command until nRRD - 1 1 repeat above D Command until 2* nRRD - 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 1, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 F 0 Assert and repeat above D Command until nFAW - 1, if necessary repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 1, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 1, but BA[2:0] = 7 D ACT RDA D ACT RDA D 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 7 0 0 0 1 1 1 00 00 00 00 00 00 00 0 0 1 0 0 1 0 0 0 0 0 0 0 0 F F F F 0 0 0 0 0 0 0 0 0 0 00110011 00000000 Assert and repeat above D Command until 2* nFAW - 1, if necessary 2 3 4 5 6 7 8 Static High toggling 9 10 Repeat above D Command until 2* nFAW + nRRD - 1 11 2*nFAW+nRRD+1 2&nFAW+nRRD+2 Repeat above D Command until 2* nFAW + 2* nRRD - 1 repeat Sub-Loop 10, but BA[2:0] = 2 repeat Sub-Loop 11, but BA[2:0] = 3 D 1 0 0 0 0 0 00 0 0 0 0 Assert and repeat above D Command until 3* nFAW - 1, if necessary repeat Sub-Loop 10, but BA[2:0] = 4 repeat Sub-Loop 11, but BA[2:0] = 5 repeat Sub-Loop 10, but BA[2:0] = 6 repeat Sub-Loop 11, but BA[2:0] = 7 D 1 0 0 0 0 0 00 0 0 0 0 Assert and repeat above D Command until 4* nFAW - 1, if necessary 12 13 14 15 16 17 18 14 2*nFAW+2*nRRD 2*nFAW+3*nRRD 2*nFAW+4*nRRD 3*nFAW 3*nFAW+nRRD 3*nFAW+2*nRRD 3*nFAW+3*nRRD 3*nFAW+4*nRRD a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING. Rev. 0.4 /January 2009 47 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 8.2 IDD Specifications IDD values are for full operating range of voltage and temperature unless otherwise noted. IDD Specification Speed Grade Bin Symbol DDR3 - 800 6-6-6 Max. 80 100 100 130 55 55 60 60 82 150 10 26 26 55 55 65 60 30 35 140 200 60 130 160 210 190 200 10 12 12 210 250 DDR3 - 1066 7-7-7 Max. 92 110 115 140 65 70 70 72 82 150 10 28 28 65 70 75 75 40 45 170 230 60 130 200 260 200 210 10 12 12 250 280 DDR3 - 1333 9-9-9 Max. 100 125 125 160 75 82 80 85 82 150 10 30 35 75 85 85 90 45 55 210 280 60 130 230 300 210 230 10 12 12 300 370 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA x4/x8 x16 x4/x8 x16 x4/x8 x16 x4/x8 x16 x4/x8 x16 x4/x8/x16 x4/x8 x16 x4/x8 x16 x4/x8 x16 x4/x8 x16 x4/x8 x16 x4/x8 x16 x4/x8 x16 x4/x8 x16 x4/x8/x16 x4/x8/x16 x4/x8/x16 x4/x8 x16 Unit Notes IDD0 IDD1 IDD2N IDD2NT IDDQ2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDDQ4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7 Rev. 0.4 /January 2009 48 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 9. Input/Output Capacitance DDR3-800 Parameter Input/output capacitance (DQ, DM, DQS, DQS, TDQS, TDQS) Input capacitance, CK and CK Symbol CIO CCK Min 1.5 0.8 0 0.75 0 -0.5 -0.5 -0.5 Max 3.0 1.6 0.15 1.5 0.20 0.3 0.5 0.3 DDR3-1066 Min 1.5 0.8 0 0.75 0 -0.5 -0.5 -0.5 Max 3.0 1.6 0.15 1.5 0.20 0.3 0.5 0.3 DDR3-1333 Min 1.5 0.8 0 0.75 0 -0.4 -0.4 -0.5 Max 2.5 1.4 0.15 1.3 0.15 0.2 0.4 0.3 Units pF pF pF pF pF pF pF pF Notes 1,2,3 2,3 2,3,4 2,3,6 2,3,5 2,3,7,8 2,3,9,10 2,3,11 Input capacitance delta CDCK CK and CK Input capacitance CI (All other input-only pins) Input capacitance delta, DQS CDDQS and DQS Input capacitance delta CDI_CTRL (All CTRL input-only pins) Input capacitance delta CDI_ADD_ (All ADD/CMD input-only pins) CMD Input/output capacitance delta CDIO (DQ, DM, DQS, DQS) Notes: 1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS. 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK. 5. The minimum CCK will be equal to the minimum CI. 6. Input only pins include: ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE. 7. CTRL pins defined as ODT, CS and CKE. 8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK)) 9. ADD pins defined as A0-A15, BA0-BA2 and CMD pins are defined as RAS, CAS and WE. 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK)) 11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS)) Rev. 0.4 /January 2009 49 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC 10. Standard Speed Bins DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. DDR3-800 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 53.. Speed Bin CL - nRCD - nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CL = 6 CWL = 5 CWL = 5 Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) 2.5 6 5 min 15 15 15 52.5 37.5 DDR3-800E 6-6-6 max 20 — — — 9 * tREFI Reserved 3.3 ns ns ns ns ns ns ns nCK nCK 1)2)3)4) 1)2)3) Unit Notes Supported CL Settings Supported CWL Settings Rev. 0.4 /January 2009 50 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC DDR3-1066 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 53. Speed Bin CL - nRCD - nRP Parameter Symbol Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 1.875 6, 7, 8 5, 6 1.875 Reserved < 2.5 2.5 Reserved Reserved < 2.5 DDR3-1066F 7-7-7 min 13.125 13.125 13.125 50.625 37.5 Reserved Reserved 3.3 max 20 — — — 9 * tREFI ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK 1)2)3)4)6) 4) 1)2)3)6) 1)2)3)4) 4) 1)2)3)4) 4) 1)2)3) Unit Note CL = 6 CL = 7 CL = 8 Supported CL Settings Supported CWL Settings Rev. 0.4 /January 2009 51 H5TQ1G43AFP(R)-xxC H5TQ1G83AFP(R)-xxC H5TQ1G63AFP(R)-xxC DDR3-1333 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 53. Speed Bin CL - nRCD - nRP Parameter Symbol Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 6, 7 CWL = 5 CL = 6 CWL = 6 CWL = 7 CWL = 5 CL = 7 CWL = 6 CWL = 7 CWL = 5 CL = 8 CWL = 6 CWL = 7 CL = 9 CWL = 5, 6 CWL = 7 CWL = 5, 6 CL = 10 CWL = 7 tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 1.875 tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 1.5 (Optional) 6,(7), 8, 9 5, 6, 7 1.5 Reserved