H5TQ4G63EFR-TEC

4Gb DDR3 SDRAM 4Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ4G83EFR-xxC H5TQ4G83EFR-xxI H5TQ4G83EFR-xxL H5TQ4G83EFR-xxJ H5TQ4G63EFR-xxC H5TQ4G63EFR-xxI H5TQ4G63EFR-xxL H5TQ4G63EFR-xxJ * SK Hynix reserves the right to change products or specifications without notice. Rev. 0.1/ Mar 2016 1 Revision History Revision No. History Draft Date 0.1 Initial Version Mar. 2016 Rev. 0.1/ Mar 2016 Remark 2 Description The H5TQ4G83EFR-xxC,H5TQ4G63EFR-xxC, H5TQ4G83EFR-xxI, H5TQ4G63EFR-xxI, H5TQ4G83EFR-xxL, H5TQ4G63EFR-xxL,H5TQ4G83EFR-xxJ and H5TQ4G63EFR-xxJ are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK Hynix 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information FEATURES • VDD=VDDQ=1.5V +/- 0.075V • 8banks • Fully differential clock inputs (CK, CK) operation • Average Refresh Cycle (Tcase of 0 oC~ 95 oC) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC Commercial Temperature( 0oC ~ 95 oC) Industrial Temperature( -40oC ~ 95 oC) • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • JEDEC standard 78ball FBGA(x8), 96ball FBGA (x16) • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Driver strength selected by EMRS • Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13 and 14 supported • Asynchronous RESET pin supported • Programmable additive latency 0, CL-1, and CL-2 supported • TDQS (Termination Data Strobe) supported (x8 only) • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 9 and 10 • 8 bit pre-fetch • Dynamic On Die Termination supported • ZQ calibration supported • Write Levelization supported • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly * This product in compliance with the RoHS directive. Rev. 0.1/ Mar 2016 3 ORDERING INFORMATION Part No. Configuration H5TQ4G83EFR-*xxC Power Consumption Normal Consumption H5TQ4G83EFR-*xxI 512M x 8 H5TQ4G83EFR-*xxL H5TQ4G63EFR-*xxI (IDD6 Only) Industrial 256M x 16 H5TQ4G63EFR-*xxL Industrial Commercial Normal Consumption 78ball FBGA Commercial Industrial Low Power Consumption Commercial (IDD6 Only) Industrial H5TQ4G63EFR-*xxJ Package Commercial Low Power Consumption H5TQ4G83EFR-*xxJ H5TQ4G63EFR-*xxC Temperature 96ball FBGA * xx means Speed Bin Grade OPERATING FREQUENCY Frequency [Mbps] Speed Grade (Marking) CL5 CL6 CL7 CL8 CL9 CL10 -H9 667 800 1066 1066 1333 1333 -PB 667 800 1066 1066 1333 1333 1600 -RD* 800 1066 1066 1333 1333 1600 1866 -TE 800 1066 1066 1333 1333 1600 1866 CL11 CL12 CL13 CL14 Remark (CL-tRCD-tRP) DDR3-1333 9-9-9 DDR3-1600 11-11-11 DDR3-1866 13-13-13 2133 DDR3-2133 14-14-14 *Note1: In case of 1.5V P/N (H5TQ4G8(6)3EFR), -RDC covers Lower speed of -PBC and -H9C Rev. 0.1/ Mar 2016 4 x8 Package Ball out (Top view): 78ball FBGA Package 1 2 3 4 5 6 7 8 9 A VSS VDD NC NF/TDQS VSS VDD A B VSS VSSQ DQ0 DM/TDQS VSSQ VDDQ B C VDDQ DQ2 DQS DQ1 DQ3 VSSQ C D VSSQ DQ6 DQS VDD VSS VSSQ D E VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ E F NC VSS RAS CK VSS NC F G ODT VDD CAS CK VDD CKE G H NC CS WE A10/AP ZQ NC H J VSS BA0 BA2 A15 VREFCA VSS J K VDD A3 A0 A12/BC BA1 VDD K L VSS A5 A2 A1 A4 VSS L M VDD A7 A9 A11 A6 VDD M N VSS RESET A13 A14 A8 VSS N 1 2 3 7 8 9 1 2 3 4 5 6 7 8 9 A B C D E F G H J K (Top View: See the balls through the Package) Populated ball Ball not populated L M N Rev. 0.1/ Mar 2016 5 x16 Package Ball out (Top view): 96ball FBGA Package 1 2 3 A VDDQ DQU5 B VSSQ VDD C VDDQ D 4 5 6 7 8 9 DQU7 DQU4 VDDQ VSS A VSS DQSU DQU6 VSSQ B DQU3 DQU1 DQSU DQU2 VDDQ C VSSQ VDDQ DMU DQU0 VSSQ VDD D E VSS VSSQ DQL0 DML VSSQ VDDQ E F VDDQ DQL2 DQSL DQL1 DQL3 VSSQ F G VSSQ DQL6 DQSL VDD VSS VSSQ G H VREFDQ VDDQ DQL4 DQL7 DQL5 VDDQ H J NC VSS RAS CK VSS NC J K ODT VDD CAS CK VDD CKE K L NC CS WE A10/AP ZQ NC L M VSS BA0 BA2 NC VREFCA VSS M N VDD A3 A0 A12/BC BA1 VDD N P VSS A5 A2 A1 A4 VSS P R VDD A7 A9 A11 A6 VDD R T VSS RESET A13 A14 A8 VSS T 1 2 3 7 8 9 1 2 3 4 5 6 7 8 9 A B C D E F G (Top View: See the balls through the Package) H J K Populated ball Ball not populated L M N P R T Rev. 0.1/ Mar 2016 6 Pin Functional Description Symbol Type Function CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. CKE, (CKE0), (CKE1) Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE, are disabled during powerdown. Input buffers, excluding CKE, are disabled during Self-Refresh. CS, (CS0), (CS1), (CS2), (CS3) Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. ODT, (ODT0), (ODT1) Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x4/x8 configurations. For x16 configuration, ODT is applied to each DQ, DQSU, DQSU, DQSL, DQSL, DMU, and DML signal. The ODT pin will be ignored if MR1 is programmed to disable ODT. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM, (DMU), (DML) Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1. BA0 - BA2 Input Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS cycle. Input Address Inputs: Provide the row address for Active commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions, see below). The address inputs also provide the op-code during Mode Register Set commands. A10 / AP Input Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. A12 / BC Input Burst Chop: A12 / BC is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details. A0 - A15 Rev. 0.1/ Mar 2016 7 Symbol Type Function Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH. RESET must be HIGH during normal operation. RESET is a CMOS rail-to-rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low. RESET Input DQ Input / Output Data Input/ Output: Bi-directional data bus. Input / Output Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobe DQS, DQSL, and DQSU are paired with differential signals DQS, DQSL, and DQSU, respectively, to provide differential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and does not support single-ended. Output Termination Data Strobe: TDQS/TDQS is applicable for x8 DRAMs only. When enabled via Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11 = 0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/x16 DRAMs must disable the TDQS function via mode register A11 = 0 in MR1. DQU, DQL, DQS, DQS, DQSU, DQSU, DQSL, DQSL TDQS, TDQS NC No Connect: No internal electrical connection is present. NF No Function VDDQ Supply DQ Power Supply: 1.5 V +/- 0.075 V VSSQ Supply DQ Ground VDD Supply Power Supply: 1.5 V +/- 0.075 V VSS Supply Ground VREFDQ Supply Reference voltage for DQ VREFCA Supply Reference voltage for CA ZQ Supply Reference Pin for ZQ calibration Note: Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT, DM, and RESET) do not supply termination. Rev. 0.1/ Mar 2016 8 ROW AND COLUMN ADDRESS TABLE 4Gb Configuration # of Banks Bank Address Auto precharge BL switch on the fly Row Address Column Address Page size 1 512Mb x 8 256Mb x 16 8 BA0 - BA2 A10/AP A12/BC A0 - A15 A0 - A9 1 KB 8 BA0 - BA2 A10/AP A12/BC A0 - A14 A0 - A9 2 KB Note1: Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: page size = 2 COLBITS * ORG  8 where COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits Rev. 0.1/ Mar 2016 9 Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol VDD VDDQ Parameter Rating Units Notes Voltage on VDD pin relative to Vss - 0.4 V ~ 1.80 V V 1,3 Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.80 V V 1,3 - 0.4 V ~ 1.80 V V 1 -55 to +100 oC 1, 2 VIN, VOUT Voltage on any pin relative to Vss TSTG Storage Temperature Notes: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than 0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. DRAM Component Operating Temperature Range Temperature Range Symbol Parameter Normal Operating Temperature Range Rating 0 to 85 Units oC Notes 1,2 TOPER Extended Temperature Range 85 to 95 oC 1,4 -40 to 95 oC 1,3,4 Industrial Temperature Range Notes: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions. 3. The Industrial Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between -40 - 85oC under all operating conditions. 4. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b). Rev. 0.1/ Mar 2016 10 AC & DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions Symbol VDD VDDQ Parameter Rating Units Notes 1.575 V 1,2 1.575 V 1,2 Min. Typ. Max. Supply Voltage 1.425 1.500 Supply Voltage for Output 1.425 1.500 Notes: 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. Rev. 0.1/ Mar 2016 11 IDD and IDDQ Specification Parameters and Test Conditions IDD and IDDQ Measurement Conditions In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 1. shows the setup and test load for IDD and IDDQ measurements. • IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents. • IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB. For IDD and IDDQ measurements, the following definitions apply: • ”0” and “LOW” is defined as VIN = VIHAC(max). • “MID_LEVEL” is defined as inputs are VREF = VDD/2. • Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1. • Basic IDD and IDDQ Measurement Conditions are described in Table 2. • Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10. • IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting RON = RZQ/7 (34 Ohm in MR1); Qoff = 0B (Output Buffer enabled in MR1); RTT_Nom = RZQ/6 (40 Ohm in MR1); RTT_Wr = RZQ/2 (120 Ohm in MR2); TDQS Feature disabled in MR1 • Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started. • Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW} • Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH} Rev. 0.1/ Mar 2016 12 IDDQ (optional) IDD VDD VDDQ RESET CK/CK DDR3 SDRAM CKE CS RAS, CAS, WE DQS, DQS DQ, DM, TDQS, TDQS A, BA ODT ZQ VSS RTT = 25 Ohm VDDQ/2 VSSQ Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements [Note: DIMM level Output test load condition may be different from above] Application specific memory channel environment IDDQ Test Load Channel IO Power Simulation IDDQ Simulation IDDQ Simulation Correction Channel IO Power Number Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement Rev. 0.1/ Mar 2016 13 Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns Symbol DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 7-7-7 9-9-9 11-11-11 13-13-13 14-14-14 1.875 1.5 1.25 1.07 0.935 tCK Unit ns CL 7 9 11 13 14 nCK nRCD 7 9 11 13 14 nCK nRC 27 33 39 45 50 nCK nRAS 20 24 28 32 36 nCK nRP 7 9 11 13 14 nCK 1KB page size 20 20 24 26 27 nCK 2KB page size 27 30 32 33 38 nCK 1KB page size 4 4 5 5 6 nCK 2KB page size 6 5 6 6 7 nCK nRFC -512Mb 48 60 72 85 97 nCK nRFC-1 Gb 59 74 88 103 118 nCK nFAW nRRD nRFC- 2 Gb 86 107 128 150 172 nCK nRFC- 4 Gb 139 174 208 243 279 nCK nRFC- 8 Gb 187 234 280 328 375 nCK Table 2 -Basic IDD and IDDQ Measurement Conditions Symbol Description Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT IDD0 and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3. Rev. 0.1/ Mar 2016 14 Symbol Description Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between IDD1 ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4. Precharge Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, IDD2N Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5. Precharge Standby ODT Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, IDD2NT Bank Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6; Pattern Details: see Table 6. Precharge Power-Down Current Slow Exit CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, IDD2P0 Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc) Precharge Power-Down Current Fast Exit CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, IDD2P1 Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc) Precharge Quiet Standby Current IDD2Q CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 Rev. 0.1/ Mar 2016 15 Symbol Description Active Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, IDD3N Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5. Active Power-Down Current IDD3P CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, IDD4R Address, Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7. Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, IDD4W Address, Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8. Burst Refresh Current CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Com- IDD5B mand, Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9. Self-Refresh Current: Normal Temperature Range TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); IDD6 CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL Rev. 0.1/ Mar 2016 16 Symbol Description Self-Refresh Current: Extended Temperature Range TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): ExtendIDD6ET ede); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a), f); AL: CL1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling accord- IDD7 ing to Table 10; Data IO: read data burst with different data between one burst and the next one according to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 10. a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B Rev. 0.1/ Mar 2016 17 Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 ACT 0 0 1 1 0 0 00 0 0 0 0 - 1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 0 0 - 0 0 0 - 0 F 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 3 - IDD0 Measurement-Loop Patterna) 0 3,4 ... nRAS Static High toggling ... repeat pattern 1...4 until nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 00 0 repeat pattern 1...4 until nRC - 1, truncate if necessary 1*nRC+0 ACT 1*nRC+1, 2 D, D 1 0 0 0 0 0 00 0 0 F 0 - 1*nRC+3, 4 D, D 1 1 1 1 0 0 00 0 0 F 0 - 0 - ... 1*nRC+nRAS 0 0 1 1 0 0 00 0 repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 00 0 0 ... repeat pattern 1...4 until 2*nRC - 1, truncate if necessary 1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead F a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. Rev. 0.1/ Mar 2016 18 Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 ACT 0 0 1 1 0 0 00 0 0 0 0 - 1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 0 0 - 0 0 00000000 0 0 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 4 - IDD1 Measurement-Loop Patterna) 0 3,4 ... nRCD ... nRAS Static High toggling ... repeat pattern 1...4 until nRCD - 1, truncate if necessary RD 0 1 0 1 0 0 00 0 0 repeat pattern 1...4 until nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 00 0 repeat pattern 1...4 until nRC - 1, truncate if necessary 1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 - 1*nRC+1,2 D, D 1 0 0 0 0 0 00 0 0 F 0 - D, D 1 1 1 1 0 0 00 0 0 F 0 - 1*nRC+3,4 ... 1*nRC+nRCD ... 1*nRC+nRAS repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary RD 0 1 0 1 0 0 00 0 0 F 0 00110011 repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 00 0 0 F ... repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary 1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead 0 - a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL. Rev. 0.1/ Mar 2016 19 Static High CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 D 1 0 0 0 0 0 0 0 0 0 0 - 1 D 1 0 0 0 0 0 0 0 0 0 0 - 2 D 1 1 1 1 0 0 0 0 0 F 0 - 3 D 1 1 1 1 0 0 0 0 0 F 0 - Cycle Number Command 0 toggling Datab) Sub-Loop CKE CK, CK Table 5 - IDD2N and IDD3N Measurement-Loop Patterna) 1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 8-11 repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 12-15 repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 16-19 repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 20-23 repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 24-17 repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 28-31 repeat Sub-Loop 0, use BA[2:0] = 7 instead a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. Static High CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 D 1 0 0 0 0 0 0 0 0 0 0 - 1 D 1 0 0 0 0 0 0 0 0 0 0 - 2 D 1 1 1 1 0 0 0 0 0 F 0 - 3 D 1 1 1 1 0 0 0 0 0 F 0 - Cycle Number Command 0 toggling Datab) Sub-Loop CKE CK, CK Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna) 1 4-7 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1 2 8-11 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2 3 12-15 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3 4 16-19 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4 5 20-23 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5 6 24-17 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6 7 28-31 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7 a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. Rev. 0.1/ Mar 2016 20 Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000 1 D 1 0 0 0 0 0 00 0 0 0 0 - 2,3 D,D 1 1 1 1 0 0 00 0 0 0 0 - 4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011 D 1 0 0 0 0 0 00 0 0 F 0 - D,D 1 1 1 1 0 0 00 0 0 F 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna) 0 Static High toggling 5 6,7 1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1 2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2 3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3 4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4 5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5 6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6 7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7 a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL. Rev. 0.1/ Mar 2016 21 Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 WR 0 1 0 0 1 0 00 0 0 0 0 00000000 1 D 1 0 0 0 1 0 00 0 0 0 0 - 2,3 D,D 1 1 1 1 1 0 00 0 0 0 0 - 4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011 D 1 0 0 0 1 0 00 0 0 F 0 - D,D 1 1 1 1 1 0 00 0 0 F 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 8 - IDD4W Measurement-Loop Patterna) 0 Static High toggling 5 6,7 1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1 2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2 3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3 4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4 5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5 6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6 7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7 a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL. Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 REF 0 0 0 1 0 0 0 0 0 0 0 - 1 1.2 D, D 1 0 0 0 0 0 00 0 0 0 0 - 3,4 D, D 1 1 1 1 0 0 00 0 0 F 0 - Cycle Number 0 Sub-Loop CKE Datab) Static High toggling CK, CK Table 9 - IDD5B Measurement-Loop Patterna) 2 5...8 repeat cycles 1...4, but BA[2:0] = 1 9...12 repeat cycles 1...4, but BA[2:0] = 2 13...16 repeat cycles 1...4, but BA[2:0] = 3 17...20 repeat cycles 1...4, but BA[2:0] = 4 21...24 repeat cycles 1...4, but BA[2:0] = 5 25...28 repeat cycles 1...4, but BA[2:0] = 6 29...32 repeat cycles 1...4, but BA[2:0] = 7 33...nRFC-1 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary. a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. Rev. 0.1/ Mar 2016 22 Table 10 - IDD7 Measurement-Loop Patterna) 0 1 2 3 4 Static High 5 6 7 8 toggling 9 10 0 1 2 ... nRRD nRRD+1 nRRD+2 ... 2*nRRD 3*nRRD 4*nRRD nFAW nFAW+nRRD nFAW+2*nRRD nFAW+3*nRRD nFAW+4*nRRD 2*nFAW+0 2*nFAW+1 2&nFAW+2 11 2*nFAW+nRRD 2*nFAW+nRRD+1 2&nFAW+nRRD+ 2 12 13 2*nFAW+2*nRRD 2*nFAW+3*nRRD 14 2*nFAW+4*nRRD 15 16 17 18 3*nFAW 3*nFAW+nRRD 3*nFAW+2*nRRD 3*nFAW+3*nRRD 19 3*nFAW+4*nRRD A[2:0] A[6:3] A[9:7] A[10] A[15:11] BA[2:0] ODT WE CAS RAS CS Command Cycle Number Sub-Loop CKE CK, CK ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9 ACT 0 0 1 1 0 0 00 0 0 0 0 RDA 0 1 0 1 0 0 00 1 0 0 0 D 1 0 0 0 0 0 00 0 0 0 0 repeat above D Command until nRRD - 1 ACT 0 0 1 1 0 1 00 0 0 F 0 RDA 0 1 0 1 0 1 00 1 0 F 0 D 1 0 0 0 0 1 00 0 0 F 0 repeat above D Command until 2* nRRD - 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 1, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 F 0 Assert and repeat above D Command until nFAW - 1, if necessary repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 1, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 1, but BA[2:0] = 7 D 1 0 0 0 0 7 00 0 0 F 0 Assert and repeat above D Command until 2* nFAW - 1, if necessary ACT 0 0 1 1 0 0 00 0 0 F 0 RDA 0 1 0 1 0 0 00 1 0 F 0 D 1 0 0 0 0 0 00 0 0 F 0 Repeat above D Command until 2* nFAW + nRRD - 1 ACT 0 0 1 1 0 1 00 0 0 0 0 RDA 0 1 0 1 0 1 00 1 0 0 0 D 1 0 0 0 0 1 00 0 0 0 0 Repeat above D Command until 2* nFAW + 2* nRRD - 1 repeat Sub-Loop 10, but BA[2:0] = 2 repeat Sub-Loop 11, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 0 0 Assert and repeat above D Command until 3* nFAW - 1, if necessary repeat Sub-Loop 10, but BA[2:0] = 4 repeat Sub-Loop 11, but BA[2:0] = 5 repeat Sub-Loop 10, but BA[2:0] = 6 repeat Sub-Loop 11, but BA[2:0] = 7 D 1 0 0 0 0 7 00 0 0 0 0 Assert and repeat above D Command until 4* nFAW - 1, if necessary Datab) 00000000 00110011 - - 00110011 00000000 - - - a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL. Rev. 0.1/ Mar 2016 23 IDD Specifications IDD values are for full operating range of voltage and temperature unless otherwise noted. IDD Specification Speed Grade Bin DDR3 - 1066 7-7-7 DDR3 - 1333 9-9-9 DDR3 - 1600 11-11-11 DDR3 - 1866 13-13-13 DDR3 - 2133 14-14-14 Symbol Max. Max. Max. Max. Max. IDD0 IDD01 IDD2P0 IDD2P1 IDD2N IDD2NT IDD2Q IDD3P IDD3N IDD4R IDD4w IDD5B IDD6 IDD6 (Low Power) IDD6ET IDD7 Unit Notes TBD TBD TBD TBD TBD mA x8 TBD TBD TBD TBD TBD mA x16 TBD TBD TBD TBD TBD mA x8 TBD TBD TBD TBD TBD mA x16 TBD TBD TBD TBD TBD mA x8 TBD TBD TBD TBD TBD mA x16 TBD TBD TBD TBD TBD mA x8 TBD TBD TBD TBD TBD mA x16 TBD TBD TBD TBD TBD mA x8 TBD TBD TBD TBD TBD mA x16 TBD TBD TBD TBD TBD mA x8 TBD TBD TBD TBD TBD mA x16 TBD TBD TBD TBD TBD mA x8 TBD TBD TBD TBD TBD mA x16 TBD TBD TBD TBD TBD mA x8 TBD TBD TBD TBD TBD mA x16 TBD TBD TBD TBD TBD mA x8 TBD TBD TBD TBD TBD mA x16 TBD TBD TBD TBD TBD mA x8 TBD TBD TBD TBD TBD mA x16 TBD TBD TBD TBD TBD mA x8 TBD TBD TBD TBD TBD mA x16 TBD TBD TBD TBD TBD mA x8 TBD TBD TBD TBD TBD mA x16 TBD TBD TBD TBD TBD mA x8 TBD TBD TBD TBD TBD mA x16 TBD TBD TBD TBD TBD mA x8 TBD TBD TBD TBD TBD mA x16 TBD TBD TBD TBD TBD mA x8 TBD TBD TBD TBD TBD mA x16 TBD TBD TBD TBD TBD mA x8 TBD TBD TBD TBD TBD mA x16 Notes: 1. Applicable for MR2 settings A6=0 and A7=0. Temperature range for IDD6 is 0 - 85oC. 2. Applicable for MR2 settings A6=0 and A7=1. Temperature range for IDD6ET is 0 - 95oC. Rev. 0.1/ Mar 2016 24 Input/Output Capacitance Parameter Symbol DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Min Input/output capacitance CIO 1.5 (DQ, DM, DQS, DQS, TDQS, TDQS) Input capacitance, CK CCK 0.8 and CK Input capacitance delta CDCK 0 CK and CK Input capacitance delta, CDDQS 0 DQS and DQS Input capacitance CI 0.75 (All other input-only pins) Input capacitance delta C -0.5 (All CTRL input-only pins) DI_CTRL Input capacitance delta CDI_ADD_ (All ADD/CMD input-only -0.5 CMD pins) Input/output capacitance CDIO -0.5 delta (DQ, DM, DQS, DQS) Input/output capacitance CZQ of ZQ pin Notes: Units Notes Max Min Max Min Max Min Max Min Max 2.7 1.5 2.5 1.5 2.3 1.4 2.2 1.4 2.1 pF 1,2,3 1.6 0.8 1.4 0.8 1.4 0.8 1.3 0.8 1.3 pF 2,3 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4 0.20 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,5 1.35 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 pF 2,3,6 0.3 -0.4 0.2 -0.4 0.2 -0.4 0.2 -0.4 0.2 pF 2,3,7,8 0.5 -0.4 0.4 -0.4 0.4 -0.4 0.4 -0.4 0.4 pF 2,3,9,10 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11 3 - 3 - 3 - 3 - 3 pF 2,3,12 1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS. 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK. 5. Absolute value of CIO(DQS)-CIO(DQS). 6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE. 7. CDI_CTR applies to ODT, CS and CKE. 8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK)) 9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE. 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK)) 11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS)) 12. Maximum external load capacitance an ZQ pin: 5 pF. Rev. 0.1/ Mar 2016 25 Standard Speed Bins DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. DDR3-1066 Speed Bins For specific Notes see “Speed Bin Table Notes” on page 31. Speed Bin DDR3-1066 CL - nRCD - nRP Parameter Symbol Unit 7-7-7 min max Internal read command to first data tAA 13.125 20 ns ACT to internal read or write delay time tRCD 13.125 — ns PRE command period tRP 13.125 — ns ACT to ACT or REF command period tRC 50.625 — ns ACT to PRE command period tRAS 37.5 9 * tREFI ns CWL = 5 tCK(AVG) 3.0 3.3 ns CWL = 6 tCK(AVG) CWL = 5 tCK(AVG) CWL = 6 tCK(AVG) CWL = 5 tCK(AVG) CWL = 6 tCK(AVG) CWL = 5 tCK(AVG) CWL = 6 tCK(AVG) CL = 5 CL = 6 CL = 7 CL = 8 ns 1, 2, 3, 4, 6, 12,13 4 ns 1, 2, 3, 6 Reserved ns 1, 2, 3, 4 Reserved ns 4 ns 1, 2, 3, 4 Reserved 2.5 3.3 1.875 < 2.5 Reserved 1.875 < 2.5 ns 4 ns 1, 2, 3 13 Supported CL Settings 5, 6, 7, 8 nCK Supported CWL Settings 5, 6 nCK Rev. 0.1/ Mar 2016 Note 26 DDR3-1333 Speed Bins For specific Notes see “Speed Bin Table Notes” on page 31. Speed Bin DDR3-1333 CL - nRCD - nRP Parameter Symbol Unit 9-9-9 min max Internal read command to first data tAA 13.5 (13.125)5,11 20 ns ACT to internal read or write delay time tRCD 13.5 (13.125)5,11 — ns PRE command period tRP 13.5 (13.125)5,11 — ns ACT to ACT or REF command period tRC 49.5 (49.125)5,11 — ns ACT to PRE command period tRAS 36 9 * tREFI ns CWL = 5 tCK(AVG) 3.0 3.3 ns CWL = 6, 7 tCK(AVG) CWL = 5 tCK(AVG) CWL = 6 tCK(AVG) CWL = 7 CL = 5 CL = 6 CL = 7 CL = 8 Note ns 1, 2, 3, 4, 7, 12,13 4 ns 1, 2, 3, 7 Reserved ns 1, 2, 3, 4, 7 tCK(AVG) Reserved ns 4 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) ns 1, 2, 3, 4, 7 CWL = 7 tCK(AVG) Reserved ns 1, 2, 3, 4 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) ns 1, 2, 3, 7 CWL = 7 tCK(AVG) ns 1, 2, 3, 4 CWL = 5, 6 tCK(AVG) CWL = 7 tCK(AVG) CWL = 5, 6 tCK(AVG) CWL = 7 tCK(AVG) Reserved 2.5 3.3 1.875 < 2.5 (Optional)5 1.875 < 2.5 Reserved ns 4 ns 1, 2, 3, 4 ns 4 (Optional) ns ns 1, 2, 3 5 Supported CL Settings 5, 6, 8, (7), 9, (10) nCK Supported CWL Settings 5, 6, 7 nCK CL = 9 CL = 10 Rev. 0.1/ Mar 2016 Reserved 1.5