200ball FBGA Specification
8Gb LPDDR4 (x16, 2 Channel, 1 CS)
H9HCNNN8KUMLHR-NxE
H9HCNNN8KUMLHR-NxI
This document is a general product description and is subject to change without notice. SK hynix does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev 1.1 / Sep 2016 / SK hynix Confidential
1
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
Revision History
Version
Description
Date
0.1
- Initial version
Final Version
Feb 2016
1.0
- Updated IDD Specifications
Jul 2016
1.1
- Editorial Changes
- Updated IDD Specifications, Table-Modified Refresh Command
Timing Constraints and Refresh Requirement Parameters per die
Rev 1.1 / Sep 2016 / SK hynix Confidential
Remark
Preliminary
Aug 2016
2
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
Ordering Information
Part Number
Mode
Operation
Voltage
Density
Speed
Package
Operating
Temperature
H9HCNNN8KUMLHR-NLE LPDDR4 1.8V/1.1/1.1
8Gb
200Ball FBGA
DDR4 3200
-25oC ~ 85oC
(x16, 2 Channel)
(Lead & Halogen Free)
H9HCNNN8KUMLHR-NME LPDDR4 1.8V/1.1/1.1
8Gb
200Ball FBGA
DDR4 3733
-25oC ~ 85oC
(x16, 2 Channel)
(Lead & Halogen Free)
H9HCNNN8KUMLHR-NLI LPDDR4 1.8V/1.1/1.1
8Gb
200Ball FBGA
DDR4 3200
-40oC ~ 95oC
(x16, 2 Channel)
(Lead & Halogen Free)
H9HCNNN8KUMLHR-NMI LPDDR4 1.8V/1.1/1.1
8Gb
200Ball FBGA
DDR4 3733
-40oC ~ 95oC
(x16, 2 Channel)
(Lead & Halogen Free)
H9HCNNN8KUMLHR-N**
SK Hynix Memory
FBGA
Product Mode :
LPDDR4
Density, Stack, Block Size
& Page Buffer for NVM1) :
None
Voltage & I/O for NVM :
None
Density, Stack, CH & CS for DRAM :
8Gb, DDP, 2Ch 1CS
Operating
Temperature
DRAM Speed
NAND Speed : none
Package Material :
Lead & Halogen Free
Package Type :
FBGA 200 Ball
Generation : 1st
Voltage, I/O & Option for DRAM :
1.1v/1.1, x16, LPDDR4
Rev 1.1 / Sep 2016 / SK hynix Confidential
3
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
Functional Block Diagram
DQ[15:0]_A
ZQ0_A
DQS[1:0]_t_A/DQS[1:0]_c_A
DMI[1:0]_A
CA[5:0]_A
CS_A, CKE_A, CLK_A
Channel A
4Gb x16
(256M x 16)
4Gb x16
(256M x 16)
Channel B
CA[5:0]_B
CS_B, CKE_B, CLK_B
DQ[15:0]_B
DQS[1:0]_t_B/DQS[1:0]_c_B
DMI[1:0]_B
Rev 1.1 / Sep 2016 / SK hynix Confidential
RESET_n
4
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
1. FEATURES
[ LPDDR4 ]
· VDD1 = 1.8V (1.7V to 1.95V)
· VDD2, VDDCA and VDDQ = 1.1V (1.06 to 1.17)
· VSSQ terminated DQ signals (DQ, DQS_t, DQS_c, DMI)
· Single data rate architecture for command and address;
- all control and address latched at rising edge of the clock
· Double data rate architecture for data Bus;
- two data accesses per clock cycle
· Differential clock inputs (CK_t, CK_c)
· Bi-directional differential data strobe (DQS_t, DQS_c)
- Source synchronous data transaction aligned to bi-directional differential data strobe (DQS_t, DQS_c)
· DMI pin support for write data masking and DBIdc functionality
· Programmable RL (Read Latency) and WL (Write Latency)
· Burst length: 16 (default), 32 and On-the-fly
- On the fly mode is enabled by MRS
· Auto refresh and self refresh supported
· All bank auto refresh and directed per bank auto refresh supported
· Auto TCSR (Temperature Compensated Self Refresh)
· PASR (Partial Array Self Refresh) by Bank Mask and Segment Mask
· Background ZQ Calibration
Rev 1.1 / Sep 2016 / SK hynix Confidential
5
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
2. Package ballout & Addressing
2.1. FBGA package
2.1.1. 200 balls, 10x15mm2, 0.8 x 0.65mm pitch
8
9
10
11
12
ZQ0
NC
VDD2
VSS
DNU
DNU
A
VDDQ
VDDQ
DQ15
a
VDDQ
DQ8
a
DNU
B
VSS
DQ14
a
DMI1
a
DQ9
a
VSS
C
VDDQ
VSS
DQS1_t
a
VSS
VDDQ
D
VSS
VSS
DQ13
a
DQS1_c
a
DQ10
a
VSS
E
VDD2
VDD2
DQ12
a
VDDQ
DQ11
a
VDD1
F
VSS
VSS
VDD1
VSS
NC
VSS
G
CS0
a
VDD2
VDD2
CA2
a
CA3
a
CA4
a
VDD2
H
VSS
CKE0
a
NC
CK_t
a
CK_c
a
VSS
CA5
a
VSS
J
VDD2
VSS
NC
NC
VSS
VDD2
VSS
VDD2
K
1
2
3
4
5
A
DNU
DNU
VSS
VDD2
B
DNU
DQ0
a
VDDQ
DQ7
a
VSS
DQ1
a
DMI0
a
DQ6
a
VDDQ
VSS
DQS0_t
a
VSS
E
VSS
DQ2
a
DQS0_c
a
DQ5
a
F
VDD1
DQ3
a
VDDQ
DQ4
a
G
VSS
ODT
a
VSS
VDD1
H
VDD2
CA0
a
NC
J
VSS
CA1
a
K
VDD2
VSS
C
D
6
7
VSS
VDDQ
L
L
M
M
N
VDD2
VSS
VDD2
VSS
NC
NC
VSS
VDD2
VSS
VDD2
P
VSS
CA1
b
VSS
CKE0
b
NC
CK_t
b
CK_c
b
VSS
CA5
b
VSS
P
R
VDD2
CA0
b
NC
CS0
b
VDD2
VDD2
CA2
b
CA3
b
CA4
b
VDD2
R
T
VSS
ODT
b
VSS
VDD1
VSS
VSS
VDD1
VSS
RESET
VSS
T
VDD1
DQ3
b
VDDQ
DQ4
b
VDD2
DQ12
b
VDDQ
DQ11
b
VDD1
U
VSS
DQ2
b
DQS0_c
b
DQ5
b
VSS
DQ13
b
DQS1_c
b
DQ10
b
VSS
V
W
U
V
VDD2
VSS
N
W
VDDQ
VSS
DQS0_t
b
VSS
VDDQ
VDDQ
VSS
DQS1_t
b
VSS
VDDQ
Y
VSS
DQ1
b
DMI0
b
DQ6
b
VSS
VSS
DQ14
b
DMI1
b
DQ9
b
VSS
Y
AA
DNU
DQ0
b
VDDQ
DQ7
b
VDDQ
VDDQ
DQ15
b
VDDQ
DQ8
b
DNU
AA
AB
DNU
DNU
VSS
VDD2
VSS
VSS
VDD2
VSS
DNU
DNU
AB
1
2
3
4
5
8
9
10
11
12
6
7
Top View
200ball LPDDR4 (2CH) only
LPDDR4 Channel a
LPDDR4 Channel b
Power (VDD1,VDD2,VDDCA,VDDQ,VREF)
Ground (VSS,VSSCA,VSSQ)
Notes:
1. 0.8mm pitch (X-axis), 0.65mm pitch (Y-axis), 22 rows
2. Top View, A1 in top left corner
3. ODT_CA_[x] balls are wired to ODT_CA)_[x] pads of Rank 0 DRAM die. The ODT input to other rank (if present) will be connected
to VSS in the package.
4. ZQ2, CKE2_A, CKE2_B, CS2_A, and CS2_B balls are reserved for 3-rank package. For 1-rank and 2-rank package those balls are NC
Rev 1.1 / Sep 2016 / SK hynix Confidential
6
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
2.2. Mechanical specification
200 Ball 0.65/0.80mm pitch 10.00mm x 15.00mm FBGA [t = 1.00mm max]
0.800 x 11 = 8.800
A1 INDEX MARK
0.800
0.600 ± 0.100
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
0.650 x 21 = 13.650
15.000 ± 0.100
J
K
N
0.650
L
M
P
R
T
U
V
W
Y
AA
200 x Ø0.300±0.050
(Post Reflow Ø 0.320±0.050)
0.675 ± 0.100
AB
10.000 ± 0.100
Ø0.15 M C A B
0.220 ± 0.050
0.900 ± 0.100
Bottom View
SEATING PLANE
C
0.10 C
Front View
Rev 1.1 / Sep 2016 / SK hynix Confidential
7
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
2.3. Pin Description
Symbol
CK_t_A, CK_c_A
Type
Input
CK_t_B, CK_c_B
Description
Clock: CK_t and CK_c are differential clock inputs. All address, command,
and control input signals are sampled on the crossing of the positive edge of
CK_t and the negative edge of CK_c. AC timings for CA parameters are refer‐
CKE_A
Input
CKE_B
enced to CK. Each channel (A & B) has its own clock pair.
Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal
clock circuits, input buffers, and output drivers. Power-saving modes
are entered and exited via CKE transitions.
CKE is part of the command code. Each channel (A & B) has its own CKE sig‐
CS_A
CS_B
CA[5:0]_A,
Input
nal.
Chip Select: CS is part of the command code. Each channel (A & B)
Input
has its own CS signal.
Command/Address Inputs: Provide the Command and Address in-
CA[5 0]_B
puts according to the Command Truth Table. Each channel (A&B) has
ODT_CA_A
Input
its own CA signals.
CA ODT Control: The ODT_CA pin is used in conjunction with the
ODT_CA_B
DQ[15:0]_A,
I/O
Mode Register to turn on/off the On-Die-Termination for CA pins.
Data Input/Output : Bi-direction data bus.
DQ[15:0]_B
DQS[1:0]_t_A,
I/O
Read Strobe: DQS_t and DQS_c are bi-directional differential output
DQS[1:0]_c_A,
clock signals used to strobe data during a READ or WRITE. The Data
DQS[1:0]_t_B,
Strobe is generated by the DRAM for a READ and is edge-aligned with
DQS[1:0]_c_B
Data. The Data Strobe is generated by the Memory Controller for a
WRITE and is center aligned with Data. Each byte of data has a Data
Strobe signal pair.
DMI[1:0]_A,
I/O
DMI[1:0]_B
Each channel (A & B) has its own DQS strobes.
Data Mask Inversion: DMI is a bi-directional signal which is driven
HIGH when the data on the data bus is inverted, or driven LOW when
the data is in its normal state. Data Inversion can be disabled via a
mode register setting. Each byte of data has a DMI signal. Each chan-
ZQ
Reference
nel (A & B) has its own DMI signals.
Calibration Referce: Used to calibrate the output drive strength and
the termination resistance. There is one ZQ pin per die. The ZQ pin
VDD1, VDD2, VDDQ Supply
shall be connected to VDDQ through a 240-Ω ± 1% resistor.
Power Supplies: Isolated on the die for improved noise immunity.
VSS
RESET_n
Ground Reference: Power supply ground reference.
RESET: When asserted LOW, the RESET pin resets both channels of
GND
Input
the die.
Rev 1.1 / Sep 2016 / SK hynix Confidential
8
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
3. Functional Description
LPDDR4-SDRAM is a high-speed synchronous DRAM device internally configured as an 2-channel memory
with 8-bank memory per each channel.
These devices contain the following number of bits per die:
4Gb has 4,294,967,296 bits
6Gb has 6,442,450,944 bits
8Gb has 8,589,934,592 bits
12Gb has 12,884,901,888 bits
16Gb has 17,179,869,184 bits
24Gb has 25,769,803,776 bits
32Gb has 34,359,738,368 bits
LPDDR4 devices use multi cycle of single data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 6-bit CA bus contains command, address and bank information. Each command uses two clock cycles, during which command information is transferred on positive
edge of the corresponding clock.
These devices also use a double data rate architecture on the DQ pins to achieve high speed operation. The
double data rate architecture is essentially an 16n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for the LPDDR4
SDRAM effectively consists of a single 16n-bit wide, one clock cycle data transfer at the internal DRAM core
and sixteen corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the LPDDR4 SDRAMs are burst oriented; accesses start at a selected location
and continue for a programmed number of locations in a programmed sequence. Accesses begin with the
registration of an Activate command, which is then followed by a Read or Write command. The address and
BA bits registered coincident with the Activate command are used to select the row and the bank to be
accessed. The address bits registered coincident with the Read or Write command are used to select the
bank and the starting column location for the burst access.
Prior to normal operation, the LPDDR4 SDRAM must be initialized. The following section provides detailed
information covering device initialization, register definition, command description and device operation
Rev 1.1 / Sep 2016 / SK hynix Confidential
9
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
3.1. LPDDR4 SDRAM Addressing
Memory Density
(per Die)
4Gb
6Gb
8Gb
12Gb
16Gb
Memory Density
(per channel)
2Gb
3Gb
4Gb
6Gb
8Gb
16 Mb x 16 DQ
x 8 banks
x 2 channels
24 Mb x 16 DQ
x 8 banks
x 2 channels
32 Mb x 16 DQ
x 8 banks
x 2 channels
48Mb x 16DQ
x 8 banks
x 2 channels
64 Mb x 16 DQ
x 8 banks
x 2 channels
2
2
2
2
2
8
8
8
8
8
256
256
256
256
256
16,384
24,576
32,768
49,152
65,536
64
64
64
64
64
2048
2048
2048
2048
2048
2,147,483,648
3,221,225,472
4,294,967,296
6,442,450,944
8,589,934,592
4,294,967,296
6,442,450,944
8,589,934,592
12,884,901,888
17,179,869,184
BA0 - BA2
BA0 - BA2
R0 – R14
(R13=0 when
R14=1)
BA0 - BA2
BA0 - BA2
R0 – R15
(R14=0 when
R15=1)
BA0 - BA2
C0 - C9
C0 - C9
C0 - C9
C0 - C9
C0 - C9
64-bit
64-bit
64-bit
64-bit
64-bit
Configuration
Number of Channels
per die
Number of Banks
per Channel
Array Pre-fetch (bits,
per channel)
Number of Rows per
Channel
Number of Columns
(fetch boundaries)
Page Size (Bytes)
Channel Density
(Bits per channel)
Total Density (Bits
per die)
Bank Address
x16
Row
Addresses
Column
Addresses
Burst Starting
Address Boundary
R0 - R13
R0 - R14
R0 - R15
1. The lower two column addresses (C0-C1) are assumed to be “zero” and are not transmitted on the CA bus.
2. Row and Column address values on the CA bus that are not used for a particular density are “don’t care.”
3. For non-binary memory densities, only half of the row address space is valid. When the MSB address bit is “HIGH”, then the MSB1 address bit must be “LOW”.
Rev 1.1 / Sep 2016 / SK hynix Confidential
10
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
3.2. Simplified State Diagram
The state diagram provides a simplified illustration of the bus interface, supported state transitions, and the commands
that control them. For a complete description of device behavior, use the information provided in the state diagram with
the truth tables and timing specifications. The truth tables describe device behavior and applicable restrictions when
considering the actual state of all banks. For command descriptions, see the Commands and Timing section.
Figure - Simplified State Diagram
Automatic sequence
Command sequence
From any state Reset_n = L
Power-on
Reset_n
=L
SREF
Power
Down
MPC
based
training
L
=
H
MR
W
=
H
MPC
Re
se
t_
n
=
E
CK
E
CK
MPC
SREF
Self
Refresh
REF
Idle
SRX
R
MR
PD
PD
X
Idle
Power
Down
MR
Write
PD
E
PD
X
WR or
MWR
WRA or
MWRA
Write or
Masked Write
w/ auto
precharge
Rev 1.1 / Sep 2016 / SK hynix Confidential
MR
Read
MRR
Per bank
Refresh
REF
RD
WRA or
MWRA
RD
WRA or
MWRA
Read
PRE, PRA
PRE(A) = Precharge (All)
ACT = Activate
WR(A) = Write (with auto precharge)
MWR(A) = Masked Write
(with auto precharge)
RD(A) = Read (with auto precharge)
MRW = Mode Register Write
MRR = Mode Register Read
PDE = Power Down Entry
PDX = Power Down Exit
SREF = Self Refresh Entry
SRX = Self Refresh Exit
REF = Refresh
MPC = Multi Purpose Command
Write or
Masked
Write
W
MR
Bank
Active
MPC
R
MW
or
WR
Command
Bus
Training
MR Read
Active
Power
Down
MPC
based
training
MPC
based
training
ACT
MR
Write
MPC
All bank
Refresh
MR
W
MR
W
R
MR
MR Read
Per bank
Refresh
F
RE
MR
W
MR
W
MPC
based
training
M
RW
Reset
Command
Bus
Training
MR
Write
PRE, PRA
RDA
PRE, PRA
Read
with autoprecharge
Precharging
11
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
Figure - Simplified Bus Interface State Diagram
Automatic sequence
a) FIFO based Write/Read Timing
Command sequence
MPC
MPC
based
training
MPC
MPC
FIFO
WRTR
MPC
b) Read DQ Calibration
MPC
MPC
FIFO
RDTR
MPC
RD DQ
Calibration
MRW
MPC
MRW
WRTR
MRW
c) ZQ Cal Start
MPC
c) ZQ Cal Latch
ZQ Cal
Start
MPC
ZQ Cal
Latch
Notes:
1. From the Self-Refresh state the device can enter Power-Down, MRR, MRW, or MPC states. See the section on Self-Refresh for
more information.
2. In IDLE state, all banks are pre-charged.
3. In the case of a MRW command to enter a training mode, the state machine will not automatically return to the IDLE state at the
conclusion of training. See the applicable training section for more information.
4. In the case of a MPC command to enter a training mode, the state machine may not automatically return to the IDLE state at the
conclusion of training. See the applicable training section for more information.
5. This simplified State Diagram is intended to provide an overview of the possible state transitions and the commands to control
them. In particular, situations involving more than one bank, the enabling or disabling of on-die termination, and some other
events are not captured in full detail.
6. States that have an “automatic return” and can be accessed from more than one prior state (Ex. MRW from either Idle or Active
states) will return to the state from when they were initiated (Ex. MRW from Idle will return to Idle).
7. The RESET_n pin can be asserted from any state, and will cause the SDRAM to go to the Reset State. The diagram shows RESET
applied from the Power-On as an example, but the Diagram should not be construed as a restriction on RESET_n.
Rev 1.1 / Sep 2016 / SK hynix Confidential
12
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
3.2.1. Power-up and Initialization
For power-up and reset initialization, in order to prevent DRAM from functioning improperly, default values of the following MR settings are defined as following table.
Item
FSP-OP/WR
WLS
WL
RL
nWR
DBI-WR/RD
CA ODT
DQ ODT
Vref(ca) Setting
Vref(ca) value
Vref(DQ) Setting
Vref(DQ) Value
MRS
MR13 OP[7:6]
MR2 OP[6]
MR2 OP[5:3]
MR2 OP[2:0]
MR1 OP[6:4]
MR3 OP[7:6]
MR11 OP[6:4]
MR11 OP[2:0]
MR12 OP[6]
MR12 OP[5:0]
MR14 OP[6]
MR14 OP[5:0]
Table - MRS defaults settings
Default setting
00B
0B
000B
000B
000B
00B
000B
000B
1B
001101B
1B
001101B
Description
FS-OP/WR[0] are enabled
Write Latency Set 0 is selected
WL = 4
RL = 6, nRTP = 8
nWR = 6
Write & Read DBI are disabled
CA ODT is disabled
DQ ODT is disabled
Vref(ca) Range[1] enabled
Range1: 27.2% of VDDQ
Vref(DQ) Range[1] enabled
Range1: 27.2% of VDDQ
3.2.1.1. Voltage Ramp and Device Initialization
The following sequence shall be used to power up the LPDDR4 device. Unless specified otherwise, these steps are mandatory. Note that the power-up sequence of all channels must proceed simultaneously.
1. While applying power (after Ta), RESET_n is recommended to be LOW (≤0.2 x VDD2) and all inputs must be between
VILmin and VIHmax. The device outputs remain at High-Z while RESET_n is held LOW. Power supply voltage ramp
requirements are provided in Table "Voltage Ramp Conditions". VDD1 must ramp at the same time or earlier than VDD2.
VDD2 must ramp at the same time or earlier than VDDQ.
After...
Ta is reached
Table - Voltage Ramp Conditions
Applicable Conditions
VDD1 must be greater than VDD2
VDD2 must be greater than VDDQ - 200mV
Note:
1. Ta is the point when any power supply first reaches 300mV.
2. Voltage ramp conditions in above table apply between Ta and power-off (controlled or uncontrolled).
3. Tb is the point at which all supply and reference voltages are within their defined ranges.
4. Power ramp duration tINIT0 (Tb-Ta) must not exceed 20ms.
5. The voltage difference between any of VSS and VSSQ pins must not excess 100mV.
2. Following the completion of the voltage ramp (Tb), RESET_n must be maintained LOW. DQ, DMI, DQS_t and DQS_c
voltage levels must be between Vssq and Vddq during voltage ramp to avoid latch-up. CKE, CK_t, CK_c, CS_n and CA
input levels must be between Vss and VDD2 during voltage ramp to avoid latch-up.
3. Beginning at Tb, RESET_n must remain LOW for at least tINIT1(Tc), after which RESET_n can be de-asserted to
HIGH(Tc). At least 10ns before CKE de-assertion, CKE is required to be set LOW. All other input signals are "Don't Care".
Rev 1.1 / Sep 2016 / SK hynix Confidential
13
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
Figure - Power Ramp and Initialization Sequence
Ta
Tb
Tc
Reset
Td
Te
Tf
Tg
Th
Initialization
Ti
Tj
Tk
Training
tINIT4=5tCK(min)
CK_c
CK_t
tINIT0
=20ms(max)
tINIT1=200us(min)
Supplies
Reset_n
tINIT2
tINIT3=2ms(min)
=10ns(min)
CKE
tZQCAL
=1ms(min)
tINIT5=2us(min)
CA[5:0]
CS
DQs
Exit PD
DES
MRW
MRR
DES
ZQCal
Start
DES
tZQLAT
=max(30ns,8tCK)(min)
ZQCal
Latch
DES
CBT
Valid
DES
Write
Leveling
Valid
DES
DQ
Training
DES
Valid
Valid
Note
1. Training is optional and may be done at the system architects discretion. The training sequence after ZQ_CAL Latch(Th,
Sequence7~9) in the above figure, is simplified recommendation and actual training sequence may vary depending on systems.
4. After RESET_n is de-asserted(Tc), wait at least tINIT3 before activating CKE. Clock(CK_t,CK_c) is required to be started and stabilized for tINIT4 before CKE goes active(Td). CS is required to be maintained LOW when controller activates
CKE.
5. After setting CKE high, wait minimum of tINIT5 to issue any MRR or MRW commands(Te). For both MRR and MRW
commands, the clock frequency must be within the range defined for tCKb. Some AC parameters (for example, tDQSCK)
could have relaxed timings (such as tDQSCKb) before the system is appropriately configured.
6. After completing all MRW commands to set the Pull-up, Pull-down and Rx termination values, the DRAM controller
can issue ZQCAL Start command to the memory(Tf). This command is used to calibrate VOH level and output impedance
over process, voltage and temperature. In systems where more than one LPDDR4 DRAM devices share one external
ZQ resistor, the controller must not overlap the ZQ calibration sequence of each LPDDR4 device. ZQ calibration sequence is completed after tZQCAL (Tg) and the ZQCAL Latch command must be issued to update the DQ drivers and
DQ+CA ODT to the calibrated values.
7. After tZQLAT is satisfied (Th) the command bus (internal VREF(ca), CS, and CA) should be trained for high-speed
operation by issuing an MRW command (Command Bus Training Mode). This command is used to calibrate the device's
internal VREF and align CS/CA with CK for high-speed operation. The LPDDR4 device will power-up with receivers configured for low-speed operations, and VREF(ca) set to a default factory setting. Normal device operation at clock speeds
higher than tCKb may not be possible until command bus training has been completed.
The command bus training MRW command uses the CA bus as inputs for the calibration data stream, and outputs the
results asynchronously on the DQ bus. See command bus training in the MRW section for information on how to enter/
Rev 1.1 / Sep 2016 / SK hynix Confidential
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LPDDR4 8Gb (x16, 2 Channel, 1 CS)
exit the training mode.
8. After command bus training, DRAM controller must perform write leveling. Write leveling mode is enabled when MR2
OP[7] is high(Ti). See write leveling section for detailed description of write leveling entry and exit sequence. In write
leveling mode, the DRAM controller adjusts write DQS_t/_c timing to the point where the LPDDR4 device recognizes
the start of write DQ data burst with desired write latency.
9. After write leveling, the DQ Bus (internal VREF(dq), DQS, and DQ) should be trained for high-speed operation using
the MPC training commands and by issuing MRW commands to adjust VREF(dq)(Tj). The LPDDR4 device will power-up
with receivers configured for low-speed operations and VREF(dq) set to a default factory setting. Normal device operation at clock speeds higher than tCKb should not be attempted until DQ Bus training has been completed. The MPC
Read Calibration command is used together with MPC FIFO Write/Read commands to train DQ bus without disturbing
the memory array contents. See DQ Bus Training section for detailed DQ Bus Training sequence.
10. At Tk the LPDDR4 device is ready for normal operation, and is ready to accept any valid command. Any more registers that have not previously been set up for normal operation should be written at this time.
Table - Initialization Timing Parameters
Parameter
tINIT0
tINIT1
tINIT2
tINIT3
tINIT4
tINIT5
tCKb
Value
Min
200
10
2
5
2
Note 1, 2
Unit
Max
20
ms
us
ns
ms
tCK
us
ns
Note 1, 2
Comment
Maximum Voltage Ramp Time
Minimum RESET_n LOW time after completion of voltage ramp
Minimum CKE LOW time before RESET_n goes HIGH
Minimum CKE LOW time after RESET_n goes HIGH
Minimum stable clock before first CKE HIGH
Minimum idle time before first MRW/MRR command
Clock cycle time during boot
Notes
1. Min tCKb guaranteed by DRAM test is 18ns.
2. The system may boot at a higher frequency than dictated by min tCKb. The higher boot frequency is system dependent
3.2.1.2. Reset Initialization with Stable Power
The following sequence is required for RESET at no power interruption initialization.
1. Assert RESET_n below 0.2 x VDD2 anytime when reset is needed. RESET_n needs to be maintained for minimum
tPW_RESET. CKE must be pulled LOW at least 10 ns before de-asserting RESET_n.
2. Repeat steps 4 to 10 in "Voltage Ramp and Device Initialization" section.
Table - Reset Timing Parameter
Parameter
tPW_RESET
Value
Unit
Min Max
100
ns
Comment
Minimum RESET_n low time for Reset Initialization with stable power
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LPDDR4 8Gb (x16, 2 Channel, 1 CS)
3.2.2. Power-off Sequence
3.2.2.1. Controlled Power-off
The following procedure is required to power off the device.
While powering off, CKE must be held LOW (≤0.2 X VDD2) and all other inputs must be between VILmin and VIHmax.
The device outputs remain at High-Z while CKE is held LOW. DQ, DMI, DQS_t and DQS_c voltage levels must be between VSSQ and VDDQ during voltage ramp to avoid latch-up. RESET_n, CK_t, CK_c, CS and CA input levels must be
between VSS and VDD2 during voltage ramp to avoid latch-up.
Tx is the point where any power supply drops below the minimum value specified.
Tz is the point where all power supplies are below 300mV. After TZ, the device is powered off.
Table - Power Supply Conditions for Power-off
Applicable Conditions
VDD1 must be greater than VDD2
VDD2 must be greater than VDDQ - 200mV
Between...
TX and TZ
Note: The voltage difference between any of VSS, VSSQ pins must not exceed 100mV
3.2.2.2. Uncontrolled Power-off Sequence
When an uncontrolled power-off occurs, the following conditions must be met:
At Tx, when the power supply drops below the minimum values specified, all power supplies must be turned off and all
power supply current capacity must be at zero, except any static charge remaining in the system.
After Tz (the point at which all power supplies first reach 300mV), the device must power off. During this period the
relative voltage between power supplies is uncontrolled. VDD1 and VDD2 must decrease with a slope lower than 0.5V/
μs between Tx and Tz.
An uncontrolled power-off sequence can occur a maximum of 400 times over the life of the device.
Table - Timing Parameters for Power-off
Symbol
tPOFF
Value
Min
Max
2
Rev 1.1 / Sep 2016 / SK hynix Confidential
Unit
s
Comment
Maximum Power-off ramp time
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H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
3.3. Mode Register Definition
Table below shows the mode registers for LPDDR4 SDRAM. Each register is denoted as "R" if it can be read
but not written, "W" if it can be written but not read, and "R/W" if it can be read and written. A Mode Register Read command is used to read a mode register. A Mode Register Write command is used to write a
mode register.
Table. Mode Register Assignment
MA
MR#
Function
Access
OP7
OP6
OP5
OP4
0
00H
Device Information
R
CATR
1
01H
Device Feature 1
W
RPST
2
02H
Device Feature 2
W
WR Lev
WLS
WL
IO Configuration 1
W
DBIWR
DBIRD
PDDS
TUF
RFU
OP3
OP2
RZQI
RFU
RDPRE
nWR (for AP)
OP1
WRPRE
OP0
Link
Refresh
Mode
MR0
BL
MR1
RL
RFU
MR2
WR-PST
PU-CAL
MR3
3
03H
4
04H
Refresh Rate
R/W
5
05H
Basic Configuration 1
R
LPDDR4 Manufacturer ID
MR5
6
06H
Basic Configuration 2
R
Revision ID-1
MR6
7
07H
Basic Configuration 3
R
8
08H
Basic Configuration 4
R
9
09H
Test Mode
W
10
0AH
ZQ Reset
W
RFU
PPRE
RFU
Refresh Rate
MR4
Revision ID-2
IO Width
MR7
Density
Type
MR8
Vendor Specific Test Mode
MR9
RFU
ZQ Reset MR10
11
0BH
ODT Feature
W
RFU
12
0CH
VREF(ca) R0
R/W
RFU
VR-CA
CA ODT
RFU
DQ ODT
MR11
13
0DH
Functional options
W
FSP-OP
FSP-WR
14
0EH
VREF(dq)
R/W
RFU
VR(dq)
15
0FH
Invert Register 0
W
Lower Byte Invert for DQ Calibration
MR15
16
10H
PASR Bank
W
PASR Bank Mask
MR16
MR17
VREF(ca)
DMD
RRO
VRCG
VRO
MR12
RPT
VREF(dq)
CBT
MR13
MR14
17
11H
PASR Segment
W
PASR Segment Mask
18
12H
DQS Oscillator 1
R
DQS Oscillator Count - LSB
MR18
19
13H
DQS Oscillator 2
R
DQS Oscillator Count - MSB
MR19
20
14H
Invert Register 1
W
Upper Byte Invert for DQ Calibration
MR20
21
15H
Vendor Specific
N/A
RFU
22
16H
SOC ODT Feature
W
23
17H
DQS Oscillator Run Time
W
24
18H
TRR
R/W
25
19H
PPR Resource
R
Post Package Repair Resources
RFU
N/A
Reserved for Future Use
DQ Calibration
- Pattern A
W
See “DQ Calibration” section
26:31 1AH:1FH
32
20H
RFU
ODTD-CA ODTE-CS ODTE-CK
TRR
TRR Bank Address
U-MAC
DNU
N/A
Do Not Use
W
See “DQ Calibration” section
41:47 29H:2FH
DNU
N/A
Do Not Use
48:63 30H:3FH
RFU
N/A
Reserved for Future Use
40
28H
MR22
MAC Value
MR24
DQS Oscillator Run Time Setting
DQ Calibration
- Pattern B
33:39 21H:27H
MR21
CODT
MR23
MR25
MR32
MR40
1. RFU bits should be set to ‘0’ during mode register writes
2. RFU bits should be read as ‘0’ during mode register reads
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3. All mode registers that are specified as RFU or Write-only shall return undefined data when read and DQS_t/DQS_c shall be toggled
4. All mode registers that are specified as RFU shall not be written
5. See vendor device datasheet for details on vendor-specific mode registers
6. Writes to Read-only registers shall have no effect on the functionality of the device
3.3.1. MR0 Register Information (MA[5:0] = 00H)
OP[7]
CATR
Function
OP[6]
OP[5]
OP[4]
RFU
Register
Type
Refresh Mode
OP[3]
RZQI
OP[2]
OP[1]
OP[0]
Refresh
Mode
RFU
Operand
Data
Notes
0B: Both legacy & modified refresh mode supported
1B: Only modified refresh mode supported
00B: RZQ Self-Test Not Supported
01B: ZQ pin may connect to VSS or float
10B: ZQ-pin may short to VDDQ
OP[4:3]
1,2,3,4
11B: ZQ-pin Self-Test Completed, no error condition
detected (ZQ-pin may not connect to VDD2 or float,
nor short to VSS)
0B: CA for this rank is not terminated
OP[7]
1B: CA for this rank is terminated
OP[0]
RZQI
(Built-in Self-Test for RZQ)
Read-only
CATR
(CA Terminating Rank)
Notes:
1. RZQI, if supported, will be set upon the completion of the MRW ZQ Initialization Calibration command.
2. If the ZQ-pin is connected to VSSQ to set default calibration, OP[4:3] shall be set to 01B. If the ZQ-pin is not connected to VSSQ,
either OP[4:3] = 01B or OP[4:3] = 10B might indicate might indicate a ZQ-pin assembly error. It is recommended that the assembly error is corrected.
3. In the case of possible assembly error, the LPDDR4-SDRAM device will default to factory trim settings for RON, and will ignore ZQ
Calibration commands. In either case, the device may not function as intended.
4. If ZQ Self-Test returns OP[4:3] = 11B, the device has detected a resistor connected to the ZQ-pin. However, this result cannot be
used to validate the ZQ resistor value or that the ZQ resistor tolerance meets the specified limits (i.e. 240Ω ± 1%).
5. OP[7] is set at power-up, according to the state of the CA-ODT pad on the die AND the state of MR11 OP[7]. If the CAODT pad
is tied LOW, then the die will not terminate the CA bus and MR12 OP[7]=0B, regardless of the state of ODTECA (MR11 OP[7]). If
the CA-ODT pad is tied HIGH AND ODTE-CA is enabled (MR11 OP[7]=1B), then this bit will be set (MR0 OP[7]=1B) and the die
will terminate the CA bus.
3.3.2. MR1 Register Information (MA[5:0] = 01H)
OP[7]
RPST
OP[6]
OP[5]
OP[4]
nWR (for AP)
Rev 1.1 / Sep 2016 / SK hynix Confidential
OP[3]
RD-PRE
OP[2]
WR-PRE
OP[1]
OP[0]
BL
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H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
Function
Register
Type
BL
(Burst Length)
Operand
OP[1:0]
WR-PRE
(WR Pre-amble Length)
RD-PRE
(RD Pre-amble Type)
OP[2]
OP[3]
Write-only
nWR
(Write-Recovery for Auto
Precharge commands)
RPST
(RD Post-amble Length)
OP[6:4]
OP[7]
Data
00B: BL=16 Sequential (default)
01B: BL=32 Sequential
10B: BL=16 or 32 Sequential (on-the-fly)
All Others: Reserved
0B: Reserved
1B: WR Pre-amble = 2nCK (default)
0B: RD Pre-amble = Static (default)
1B: RD Pre-amble = Toggle
000B: nWR = 6 (default)
001B: nWR = 10
010B: nWR = 16
011B: nWR = 20
100B: nWR = 24
101B: nWR = 30
110B: nWR = 34
111B: nWR = 40
0B: RD Post-amble = 0.5*tCK (default)
1B: RD Post-amble = 1.5*tCK
Notes
1,5,6
5,6
3,5,6
2,5,6
4,5,6
1. Burst length on-the-fly can be set to either BL=16 or BL=32 by setting the “BL” bit in the command operands. See the Command
Truth Table.
2. The programmed value of nWR is the number of clock cycles the LPDDR4-SDRAM device uses to determine the starting point of
an internal Pre-charge operation after a Write burst with AP (auto-pre-charge) enabled. See Table, “Frequency Ranges for RL, WL,
and nWR Settings” later in this section
3. For Read operations this bit must be set to select between a “toggling” pre-amble and a “Non-toggling” pre-amble. See the preamble section for a drawing of each type of pre-amble.
4. OP[7] provides an optional READ post-amble with an additional rising and falling edge of DQS_t. The optional postamble cycle is
provided for the benefit of certain memory controllers.
5. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers
for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR
address.
6. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will
operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of
the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be
changed without affecting device operation.
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LPDDR4 8Gb (x16, 2 Channel, 1 CS)
3.3.2.1. Burst Sequence
Table - Burst Sequence for Read
Burst Burst
Length Type C4 C3 C2 C1 Co
16
32
SEQ
SEQ
Burst Cycle Number and Burst Address Sequence
1
2
3
4
5
6
7
8
9
V
0
0
0
0
0
1
2
3
4
5
6
7
8
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
9
A
B
C
D
E
F
V
0
1
0
0
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
V
1
0
0
0
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
V
1
1
0
0
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
0
0
1
0
0
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13
0
1
0
0
0
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 14 15 16 17
0
1
1
0
0
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B 1C 1D 1E 1F 10 11 12 13 14 15 16 17 18 19 1A 1B
1
0
0
0
0 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
1
0
1
0
0 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
1
1
0
0
0 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 14 15 16 17 8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
1
1
1
0
0 1C 1D 1E 1F 10 11 12 13 14 15 16 17 18 19 1A 1B C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
Table - Burst Sequence for Write
Burst Burst
Length Type C4 C3 C2 C1 Co
Burst Cycle Number and Burst Address Sequence
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
16
SEQ
V
0
0
0
0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
32
SEQ
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
1. C1:C0 input is not present on CA bus. It is implied zero.
2. The starting burst address is on 64-bit (4n) boundaries.
3. C2-C3 for BL16 and C2-C4 for BL32 shall be set to ‘0’ for all Write operations.
Rev 1.1 / Sep 2016 / SK hynix Confidential
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H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
3.3.3. MR2 Register Information (MA[5:0] = 02H)
OP[7]
WR Lev
Function
OP[6]
WLS
OP[5]
Register
Type
RL
(Read latency)
OP[4]
WL
Operand
OP[2:0]
Write only
WL
(Write latency)
WLS
(Write latency set)
WR Lev
(Write Leveling)
Rev 1.1 / Sep 2016 / SK hynix Confidential
OP[5:3]
OP[6]
OP[7]
OP[3]
OP[2]
OP[1]
RL
OP[0]
Data
DBI Disable (MR3 OP[6]=0B)
000B: RL= 6 & nRTP = 8 (Default)
001B: RL= 10 & nRTP = 8
010B: RL= 14 & nRTP = 8
011B: RL= 20 & nRTP = 8
100B: RL= 24 & nRTP = 10
101B: RL= 28 & nRTP = 12
110B: RL= 32 & nRTP = 14
111B: RL= 36 & nRTP = 16
DBI Enable (MR3 OP[6]=1B)
000B: RL= 6 & nRTP = 8
001B: RL= 12 & nRTP = 8
010B: RL= 16 & nRTP = 8
011B: RL= 22 & nRTP = 8
100B: RL= 28 & nRTP = 10
101B: RL= 32 & nRTP = 12
110B: RL= 36 & nRTP = 14
111B: RL= 40 & nRTP = 16
Set “A” (MR2 OP[6]=0B)
000B: WL=4 (Default)
001B: WL=6
010B: WL=8
011B: WL=10
100B: WL=12
101B: WL=14
110B: WL=16
111B: WL=18
Set “B” (MR2 OP[6]=1B)
000B: WL=4
001B: WL=8
010B: WL=12
011B: WL=18
100B: WL=22
101B: WL=26
110B: WL=30
111B: WL=34
0B: WL Set “A” (default)
1B: WL Set “B”
0B: Disabled (default)
1B: Enabled
Notes
1,3,4
1,3,4
1,3,4
2
21
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
1. See Latency Code Frequency Table for allowable frequency ranges for RL/WL/nWR/nRTP.
2. After a MRW to set the Write Leveling Enable bit (OP[7]=1B), the LPDDR4-SDRAM device remains in the MRW state until another
MRW command clears the bit (OP[7]=0B). No other commands are allowed until the Write Leveling Enable bit is cleared.
3. There are two physical registers assigned to each bit of this MR operand, designated set point 0 and set point 1. Only the registers
for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR
address.
4. There are two physical registers assigned to each bit of this MR operand, designated set point 0 and set point 1. The device will
operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of
the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be
changed without affecting device operation.
3.3.3.1. Read and Write Latencies (Frequency Ranges for RL, WL, and nWR Settings)
Read Latency
Write Latency
No DBI
w/ DBI
Set “A”
Set “B”
6
10
14
20
24
28
32
36
6
12
16
22
28
32
36
40
4
6
8
10
12
14
16
18
4
8
12
18
22
26
30
34
6
10
16
20
24
30
34
40
8
8
8
8
10
12
14
16
10
266
533
800
1066
1333
1600
1866
Freq. limit
(Same or less
than)
266
533
800
1066
1333
1600
1866
2133
nCK
nCK
nCK
nCK
nCK
nCK
MHz
MHz
nWR nRTP
Freq. limit
(Greater than)
Notes
1,2,3,4
,5,6
Notes:
1. The LPDDR4-SDRAM device should not be operated at a frequency above the Upper Frequency Limit, or below the Lower Frequency Limit, shown for each RL, WL, nRTP, or nWR value.
2. DBI for Read operations is enabled in MR3-OP[6]. When MR3-OP[6]=0, then the “No DBI” column should be used for Read Latency.
When MR3-OP[6]=1, then the “w/DBI” column should be used for Read Latency.
3. Write Latency Set “A” and Set “B” is determined by MR2-OP[6]. When MR2-OP[6]=0, then Write Latency Set “A” should be used.
When MR2-OP[6]=1, then Write Latency Set “B” should be used.
4. The programmed value of nWR is the number of clock cycles the LPDDR4-SDRAM device uses to determine the starting point of
an internal Pre-charge operation after a Write burst with AP (auto-pre-charge) enabled. It is determined by RU(tWR/tCK).
5. The programmed value of nRTP is the number of clock cycles the LPDDR4-SDRAM device uses to determine the starting point of
an internal Pre-charge operation after a Read burst with AP (auto-pre-charge) enabled. It is determined by RU(tRTP/tCK).
6. nRTP shown in this table is valid for BL16 only. For BL32, the SDRAM will add 8 clocks to the nRTP value before starting a precharge.
3.3.4. MR3 Register Information (MA[5:0] = 03H)
OP[7]
DBI-WR
OP[6]
DBI-RD
OP[5]
Rev 1.1 / Sep 2016 / SK hynix Confidential
OP[4]
PDDS
OP[3]
OP[2]
RFU
OP[1]
WR-PST
OP[0]
PU-CAL
22
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
Function
Register
Type
Operand
PU-CAL
(Pull-up Calibration Point)
WR-PST
(Write Post-amble length)
PDDS
(Pull-down Drive Strength)
OP[0]
OP[1]
Write only
OP[5:3]
DBI-RD
(DBI-Read Enable)
DBI-WR
(DBI-WR Enable)
OP[6]
OP[7]
Data
0B: VDDQ/2.5
1B: VDDQ/3 (default)
0B: WR Post-amble = 0.5*tCK (default)
1B: WR Post-amble = 1.5*tCK (Vendor Specific)
000B: RFU
001B: RZQ/1
010B: RZQ/2
011B: RZQ/3
100B: RZQ/4
101B: RZQ/5
110B: RZQ/6 (default)
111B: Reserved
0B: Disabled (default)
1B: Enabled
0B: Disabled (default)
1B: Enabled
Notes
1,4
2,3,5
1,2,3
2,3
2,3
1. All values are “typical”. The actual value after calibration will be within the specified tolerance for a given voltage and temperature.
Re-calibration may be required as voltage and temperature vary.
2. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers
for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR
address.
3. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will
operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of
the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be
changed without affecting device operation.
4. PU-CAL setting is required as the same value for both Ch.A and Ch.B before ZQCAL start command.
5. SK hynix 8Gb LPDDR4 doesn’t require 1.5*tCK apply => 1.6GHz clock.
6. If MR3 OP[2] is set to 1b then PPR protection mode is enabled. The PPR Protection bit is a sticky bit and can only be set to 0b by
power on reset. MR4 OP[4] controls entry to PPR Mode. If PPR protection is enabled then DRAM will not allow writing of 1 to MR4
OP[4].
3.3.5. MR4 Register Information (MA[5:0] = 04H)
OP[7]
TUF
Function
Refresh Rate
OP[6]
OP[5]
RFU
OP[4]
PPRE
Register
Operand
Type
Read
OP[3]
RFU
OP[2]
OP[1]
OP[0]
Refresh Rate
Data
Notes
000B: SDRAM Low temperature operating limit exceeded
001B: 4x refresh
010B: 2x refresh
011B: 1x refresh (default)
1,2,3,4,
OP[2:0]
100B: 0.5x refresh
7,8,9
101B: 0.25x refresh, no-rating
110B: 0.25x refresh, with de-rating
111B: SDRAM High temperature operating limit exceeded
Rev 1.1 / Sep 2016 / SK hynix Confidential
23
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
Function
PPRE
(Post-package repair entry/
exit)
TUF
(Temperature Update Flag)
Register
Operand
Type
Data
Notes
Write
OP[4]
0B: Exit PPR mode (default)
1B: Enter PPR mode
Read
OP[7]
0B: No change in OP[2:0] since last MR4 read (default)
1B: Change in OP[2:0] since last MR4 read
5,9
6,7,8
1. The refresh rate for each MR4-OP[2:0] setting applies to tREFI, tREFIpb, and tREFW. If OP[2]=0B, the device temperature is less
or equal to 85’C. Other values require either a longer (2x, 4x) refresh interval at lower temperatures, or a shorter (0.5x, 0.25x)
refresh interval at higher temperatures. If OP[2]=1, the device temperature is greater than 85’C.
2. At higher temperatures (>85’C), AC timing de-rating may be required. If de-rating is required the LPDDR4-SDRAM will set
OP[2:0]=110B. See de-rating timing requirements in the AC Timing section.
3. DRAM vendors may or may not report all of the possible settings over the operating temperature range of the device. Each vendor
guarantees that their device will work at any temperature within the range using the refresh interval requested by their device.
4. The device may not operate properly when OP[2:0]=000B or 111B.
5. Post-package repair can be entered or exited by writing to OP[4].
6. When OP[7]=1, the refresh rate reported in OP[2:0] has changed since the last MR4 read. A mode register read from MR4 will
reset OP[7] to ‘0’.
7. OP[7]=0 at power-up. OP[2:0] bits are undefined at power-up.
8. See the section on “Temperature Sensor” for information on the recommended frequency of reading MR4.
9. OP[6:3] bits are that can be written in this register. All other bits will be ignored by the DRAM during a MRW to this register
3.3.6. MR5 Register Information (MA[5:0] = 05H)
OP[7]
Function
LPDDR4 Manufacturer ID
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
LPDDR4 Manufacturer ID
Register
Type
Read-only
Rev 1.1 / Sep 2016 / SK hynix Confidential
Operand
OP[7:0]
OP[1]
Data
OP[0]
Notes
00000110B : SK hynix
24
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
3.3.7. MR6 Register Information (MA[5:0] = 06H)
OP[7]
Function
LPDDR4 Revision ID-1
OP[6]
OP[5]
OP[4]
OP[3]
Revision ID-1
Register
Type
Operand
Read-only
OP[7:0]
OP[2]
OP[1]
OP[0]
Data
Notes
00000000B: A-version
00000001B: B-version
1
1. Please contact SK hynix office for MR6 code for this device.
3.3.8. MR7 Register Information (MA[5:0] = 07H)
OP[7]
Function
LPDDR4 Revision ID-1
OP[6]
OP[5]
OP[4]
OP[3]
Revision ID-2
Register
Type
Operand
Read-only
OP[7:0]
OP[2]
OP[1]
OP[0]
Data
00000000B: A-version
00000001B: B-version
Notes
1
1. Please contact SK hynix office for MR7 code for this device.
3.3.9. MR8 Register Information (MA[5:0] = 08H)
OP[7]
OP[6]
IO Width
Function
OP[5]
Register
Type
Type
Density
OP[4]
OP[3]
Density
Operand
OP[1:0]
Read-only
IO Width
Rev 1.1 / Sep 2016 / SK hynix Confidential
OP[5:2]
OP[7:6]
OP[2]
OP[1]
OP[0]
Type
Data
Notes
00B: S16 SDRAM (16n pre-fetch)
All Others: Reserved
0000B: 4Gb per die (2Gb per channel)
0001B: 6Gb per die (3Gb per channel)
0010B: 8Gb per die (4Gb per channel)
0011B: 12Gb per die (6Gb per channel)
0100B: 16Gb per die (8Gb per channel)
0101B: 24Gb per die (12Gb per channel)
0110B: 32Gb per die (16Gb per channel)
All Others: Reserved
00B: x16 (per channel)
All Others: Reserved
25
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
3.3.10. MR9 Register Information (MA[5:0] = 09H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
Vendor Specific Test Register
OP[1]
OP[0]
OP[1]
OP[0]
ZQ Reset
1. Only 00H should be written to this register.
3.3.11. MR10 Register Information (MA[5:0] = 0AH)
OP[7]
Function
ZQ Reset
OP[6]
OP[5]
OP[4]
RFU
Register
Type
Operand
Write-only
OP[0]
OP[3]
OP[2]
Data
Notes
OB: Normal Operation (Default)
1B: ZQ Reset
1,2
1. See the AC Timing tables for calibration latency and timing
2. If the ZQ-pin is connected to VDDQ through RZQ, either the ZQ calibration function or default calibration (via ZQ-Reset) is supported. If the ZQ-pin is connected to VSS, the device operates with default calibration, and ZQ calibration commands are ignored.
In both cases, the ZQ connection shall not change after power is applied to the device.
3.3.12. MR11 Register Information (MA[5:0] = 0BH)
OP[7]
RFU
Function
OP[6]
OP[5]
CA ODT
Register
Type
DQ ODT
(DQ Bus Receiver On-DieTermination)
OP[4]
Operand
OP[2:0]
Write-only
CA ODT
(CA Bus Receiver On-DieTermination)
OP[6:4]
OP[3]
RFU
OP[2]
OP[1]
DQ ODT
Data
000B: Disable (Default)
001B: RZQ/1
010B: RZQ/2
011B: RZQ/3
100B: RZQ/4
101B: RZQ/5
110B: RZQ/6
111B: RFU
0000B: Disable (Default)
0001B: RZQ/1
0010B: RZQ/2
0011B: RZQ/3
0100B: RZQ/4
0101B: RZQ/5
0110B: RZQ/6
0111B: RFU
OP[0]
Notes
1,2,3
1,2,3
1. All values are “typical”. The actual value after calibration will be within the specified tolerance for a given voltage and temperature.
Re-calibration may be required as voltage and temperature vary.
Rev 1.1 / Sep 2016 / SK hynix Confidential
26
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
2. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers
for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR
address.
3. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will
operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of
the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be
changed without affecting device operation.
3.3.13. MR12 Register Information (MA[5:0] = 0CH)
OP[7]
RFU
Function
VREF(ca)
(VREF(ca) Setting)
OP[6]
VR-CA
OP[5]
Register
Type
OP[4]
Operand
OP[5:0]
Read/Write
VREF(ca) Range
OP[6]
OP[3]
OP[2]
VREF(ca)
OP[1]
OP[0]
Data
000000B:
-- Thru –
110010B: See table below
All Others: Reserved
0B: VREF(ca) Range[0] enabled
1B: VREF(ca) Range[1] enabled (default)
Notes
1,2,3,5
,6
1,2,4,5
,6
1. This register controls the VREF(ca) levels for Frequency-Set-Point[1:0]. Values from either VR(ca)[0] or VR(ca)[1] may be selected
by setting OP[6] appropriately.
2. A read to this register places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ’s shall be set to ‘0’. See the section
on MRR Operation.
3. A write to OP[5:0] sets the internal VREF(ca) level for FSP[0] when MR13 OP[6]=0B, or sets FSP[1] when MR13 OP[6]=1B. The
time required for VREF(ca) to reach the set level depends on the step size from the current level to the new level. See the section
on VREF(ca) training for more information.
4. A write to OP[6] switches the LPDDR4-SDRAM between two internal VREF(ca) ranges. The range (Range[0] or Range[1]) must
be selected when setting the VREF(ca) register. The value, once set, will be retained until overwritten, or until the next power-on
or RESET event.
5. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers
for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR
address, or read from with an MRR command to this address.
6. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will
operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of
the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be
changed without affecting device operation.
Rev 1.1 / Sep 2016 / SK hynix Confidential
27
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
Table - VREF Settings for Range[0] and Range[1]
Range[0] Values (% of VDDQ)
Range[1] Values (% of VDDQ)
Notes
000000B: 10.0% 011010B: 20.4%
000000B: 22.0%
011010B: 32.4%
000001B: 10.4% 011011B: 20.8%
000001B: 22.4%
011011B: 32.8%
000010B: 10.8% 011100B: 21.2%
000010B: 22.8%
011100B: 33.2%
000011B: 11.2% 011101B: 21.6%
000011B: 23.2%
011101B: 33.6%
000100B: 11.6% 011110B: 22.0%
000100B: 23.6%
011110B: 34.0%
000101B: 12.0% 011111B: 22.4%
000101B: 24.0%
011111B: 34.4%
000110B: 12.4% 100000B: 22.8%
000110B: 24.4%
100000B: 34.8%
000111B: 12.8% 100001B: 23.2%
000111B: 24.8%
100001B: 35.2%
001000B: 13.2% 100010B: 23.6%
001000B: 25.2%
100010B: 35.6%
001001B: 13.6% 100011B: 24.0%
001001B: 25.6%
100011B: 36.0%
001010B: 14.0% 100100B: 24.4%
001010B: 26.0%
100100B: 36.4%
001011B: 14.4% 100101B: 24.8%
001011B: 26.4%
100101B: 36.8%
001100B: 14.8% 100110B: 25.2%
001100B: 26.8%
100110B: 37.2%
OP[5:0]
1,2,3
001101B: 15.2% 100111B: 25.6%
001101B: 27.2% (Default) 100111B: 37.6%
001110B: 15.6% 101000B: 26.0%
001110B: 27.6%
101000B: 38.0%
001111B: 16.0% 101001B: 26.4%
001111B: 28.0%
101001B: 38.4%
010000B: 16.4% 101010B: 26.8%
010000B: 28.4%
101010B: 38.8%
010001B: 16.8% 101011B: 27.2%
010001B: 28.8%
101011B: 39.2%
010010B: 17.2% 101100B: 27.6%
010010B: 29.2%
101100B: 39.6%
010011B: 17.6% 101101B: 28.0%
010011B: 29.6%
101101B: 40.0%
010100B: 18.0% 101110B: 28.4%
010100B: 30.0%
101110B: 40.4%
010101B: 18.4% 101111B: 28.8%
010101B: 30.4%
101111B: 40.8%
010110B: 18.8% 110000B: 29.2%
010110B: 30.8%
110000B: 41.2%
010111B: 19.2% 110001B: 29.6%
010111B: 31.2%
110001B: 41.6%
011000B: 19.6% 110010B: 30.0%
011000B: 31.6%
110010B: 42.0%
011001B: 20.0% All Others: Reserved 011001B: 32.0%
All Others: Reserved
Function Operand
VREF
Settings
for MR12
1. These values may be used for MR12 OP[5:0] to set the VREF(ca) levels in the LPDDR4-SDRAM.
2. The range may be selected in the MR12 register by setting OP[6] appropriately.
3. The MR12 registers represents either FSP[0] or FSP[1]. Two frequency-set-points each for CA and DQ are provided to allow for
faster switching between terminated and un-terminated operation, or between different high-frequency setting which may use
different terminations values.
Rev 1.1 / Sep 2016 / SK hynix Confidential
28
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
3.3.14. MR13 Register Information (MA[5:0] = 0DH)
OP[7]
FSP-OP
Function
OP[6]
FSP-WR
OP[5]
DMD
Register
Type
CBT
(Command Bus Training)
RPRE-TR
(Read Preamble Training)
Operand
OP[0]
OP[1]
VRO
(Vref Output)
VRCG
(VREF Current Generator)
RRO
(Refresh Rate Option)
DMD
(Data Mask Disable)
FSP-WR
(Frequency Set Point Write
Enable)
FSP-OP
(Frequency Set Point Operation Mode)
OP[4]
RRO
OP[2]
OP[3]
Write
OP[4]
OP[5]
OP[3]
VRCG
OP[2]
VRO
OP[1]
RPRE-TR
OP[0]
CBT
Data
0B: Normal Operation (default)
1B: Command Bus Training mode enabled
0B: Normal Operation (default)
1B: Read Preamble Training mode enabled
0B: Normal Operation (default)
1B: Output the Vref(ca) value on DQ[0] and the
Vref(dq) value on DQ[1]
0B: Normal Operation (default)
1B: VREF Fast Response (high current) mode
0B: Disable MR4 OP[2:0] (default)
1B: Enable MR4 OP[2:0]
0B: Data Mask Operation Enabled (default)
1B: Data Mask Operation Disabled
Notes
1
2
3
4,5
6
OP[6]
0B: Frequency-Set-Point[0] (default)
1B: Frequency-Set-Point[1]
7
OP[7]
0B: Frequency-Set-Point[0] (default)
1B: Frequency-Set-Point[1]
8
1. A write to set OP[0]=1 causes the LPDDR4-SDRAM to enter the VREF(ca) training mode. When OP[0]=1 and CKE goes LOW,
commands are ignored and the contents of CA[5:0] are mapped to the DQ bus. CKE must be brought HIGH before doing a MRW
to clear this bit (OP[0]=0) and return to normal operation. See the VREF(ca) training section for more information.
2. When set, the LPDDR4-SDRAM will output the VREF(ca) voltage on DQ[0] and the VREF(dq) voltage on DQ[1]. Only the “active”
frequency-set-point, as defined by MR13 OP[7], will be output on the DQ pins. This function allows an external test system to
measure the internal VREF levels.
3. When OP[3]=1, the VREF circuit uses a high-current mode to improve VREF settling time.
4. MR13 OP4 RRO bit is valid only when MR0 OP0 = 1. For LPDDR4 devices with MR0 OP0 = 0, MR4 OP[2:0] bits are not dependent
on MR13 OP4.
5. When OP[4] = 0, only 001b and 010b in MR4 OP[2:0] are disabled. LPDDR4 devices must report 011b instead of 001b or 010b in
this case. Controller should follow the refresh mode reported by MR4 OP[2:0], regardless of RRO setting. TCSR function does not
depend on RRO setting.
6. When enabled (OP[5]=0B) data masking is enabled for the device. When disabled (OP[5]=1B), Masked Write Command is not
allowed and it is illegal. See the Data Mask section for more information.
7. FSP-WR determines which frequency-set-point registers are accessed with MRW commands for the following functions: Vref(CA)
Setting, Vref(CA) Range, Vref(DQ) Setting, Vref(DQ) Range, CA ODT Enable, CA ODT value, DQ ODT Enable, DQ ODT value, DQ
Calibration Point, WL, RL, nWR, Read and Write Preamble, Read postamble, and DBI Enables.
8. FSP-OP determines which frequency-set-point register values are currently used to specify device operation for the following functions: Vref(CA) Setting, Vref(CA) Range, Vref(DQ) Setting, Vref(DQ) Range, CA ODT Enable, CA ODT value, DQ ODT Enable, DQ
ODT value, DQ Calibration Point, WL, RL, nWR, Read and Write Preamble, Read postamble, and DBI Enables.
Rev 1.1 / Sep 2016 / SK hynix Confidential
29
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
3.3.15. MR14 Register Information (MA[5:0] = 0EH)
OP[7]
RFU
Function
VREF(dq) Setting
for Set Point[0]
OP[6]
VR(dq)
Register
Type
OP[5]
OP[4]
Operand
OP[5:0]
Read / Write
VREF(dq) Range
OP[6]
OP[3]
OP[2]
VREF(dq)
OP[1]
OP[0]
Data
000000B:
-- Thru –
110010B: See table below
All Others: Reserved
0B: VREF(dq) Range[0] enabled
1B: VREF(dq) Range[1] enabled (default)
Notes
1,2,3,4
,5,6
1,2,3,4
,5,6
1. This register controls the VREF(dq) levels for Frequency-Set-Point[1:0]. Values from either VR(dq)[0] or VR(dq)[1] may be selected
by setting OP[6] appropriately.
2. A read (MRR) to this register places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ’s shall be set to ‘0’. See
the section on MRR Operation.
3. A write to OP[5:0] sets the internal VREF(dq) level for FSP[0] when MR13 OP[6]=0B, or sets FSP[1] when MR13 OP[6]=1B. The
time required for VREF(dq) to reach the set level depends on the step size from the current level to the new level. See the section
on VREF(dq) training for more information.
4. A write to OP[6] switches the LPDDR4-SDRAM between two internal VREF(dq) ranges. The range (Range[0] or Range[1]) must
be selected when setting the VREF(dq) register. The value, once set, will be retained until overwritten, or until the next power-on
or RESET event.
5. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers
for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR
address, or read from with an MRR command to this address.
6. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will
operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of
the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be
changed without affecting device operation.
Rev 1.1 / Sep 2016 / SK hynix Confidential
30
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
Table - VREF Settings for Range[0] and Range[1]
Range[0] Values (% of VDDQ)
Range[1] Values (% of VDDQ)
Notes
000000B: 10.0% 011010B: 20.4%
000000B: 22.0%
011010B: 32.4%
000001B: 10.4% 011011B: 20.8%
000001B: 22.4%
011011B: 32.8%
000010B: 10.8% 011100B: 21.2%
000010B: 22.8%
011100B: 33.2%
000011B: 11.2% 011101B: 21.6%
000011B: 23.2%
011101B: 33.6%
000100B: 11.6% 011110B: 22.0%
000100B: 23.6%
011110B: 34.0%
000101B: 12.0% 011111B: 22.4%
000101B: 24.0%
011111B: 34.4%
000110B: 12.4% 100000B: 22.8%
000110B: 24.4%
100000B: 34.8%
000111B: 12.8% 100001B: 23.2%
000111B: 24.8%
100001B: 35.2%
001000B: 13.2% 100010B: 23.6%
001000B: 25.2%
100010B: 35.6%
001001B: 13.6% 100011B: 24.0%
001001B: 25.6%
100011B: 36.0%
001010B: 14.0% 100100B: 24.4%
001010B: 26.0%
100100B: 36.4%
001011B: 14.4% 100101B: 24.8%
001011B: 26.4%
100101B: 36.8%
001100B: 14.8% 100110B: 25.2%
001100B: 26.8%
100110B: 37.2%
OP[5:0]
1,2,3
001101B: 15.2% 100111B: 25.6%
001101B: 27.2% (Default) 100111B: 37.6%
001110B: 15.6% 101000B: 26.0%
001110B: 27.6%
101000B: 38.0%
001111B: 16.0% 101001B: 26.4%
001111B: 28.0%
101001B: 38.4%
010000B: 16.4% 101010B: 26.8%
010000B: 28.4%
101010B: 38.8%
010001B: 16.8% 101011B: 27.2%
010001B: 28.8%
101011B: 39.2%
010010B: 17.2% 101100B: 27.6%
010010B: 29.2%
101100B: 39.6%
010011B: 17.6% 101101B: 28.0%
010011B: 29.6%
101101B: 40.0%
010100B: 18.0% 101110B: 28.4%
010100B: 30.0%
101110B: 40.4%
010101B: 18.4% 101111B: 28.8%
010101B: 30.4%
101111B: 40.8%
010110B: 18.8% 110000B: 29.2%
010110B: 30.8%
110000B: 41.2%
010111B: 19.2% 110001B: 29.6%
010111B: 31.2%
110001B: 41.6%
011000B: 19.6% 110010B: 30.0%
011000B: 31.6%
110010B: 42.0%
011001B: 20.0% All Others: Reserved 011001B: 32.0%
All Others: Reserved
Function Operand
VREF
Settings
for MR14
1. These values may be used for MR14 OP[5:0] to set the VREF(dq) levels in the LPDDR4-SDRAM.
2. The range may be selected in the MR14 register by setting OP[6] appropriately.
3. The MR14 registers represents either FSP[0] or FSP[1]. Two frequency-set-points each for CA and DQ are provided to allow for
faster switching between terminated and un-terminated operation, or between different high-frequency setting which may use
different terminations values.
Rev 1.1 / Sep 2016 / SK hynix Confidential
31
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
3.3.16. MR15 Register Information (MA[5:0] = 0FH)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
Lower Byte Invert Register for DQ Calibration
Register
Type
Function
Lower Byte Invert for
DQ Calibration
Operand
OP[1]
OP[0]
Data
Notes
The following values may be written for any operand
OP[7:0], and will be applied to the corresponding DQ locations DQ[7:0] within a byte lane:
Write
OP[7:0]
0B: Do not invert
1B: Invert the DQ Calibration patterns in MR32 and MR40
1
Default value for OP[7:0]=55H
Notes:
1. This register will invert the DQ Calibration pattern found in MR32 and MR40 for any single DQ, or any combination of DQ’s. Example: If MR15 OP[7:0]=00010101B, then the DQ Calibration patterns transmitted on DQ[7,6,5,3,1] will not be inverted, but the
DQ Calibration patterns transmitted on DQ[4,2,0] will be inverted.
2. DMI[0] is not inverted, and always transmits the “true” data contained in MR32/MR40.
3. No Data Bus Inversion (DBI) function is enacted during DQ Read Calibration, even if DBI is enabled in MR3-OP[6].
Pin
MR15
DQ0
OP0
DQ1
OP1
Table - MR15 Invert Register Pin Mapping
DQ2
DQ3
DMI0
DQ4
OP2
OP3
No-invert
OP4
DQ5
OP5
DQ6
OP6
DQ7
OP7
3.3.17. MR16 Register Information (MA[5:0] = 10H)
OP[7]
Function
Bank[7:0] Mask
OP[6]
OP[5]
OP[4]
OP[3]
PASR Bank Mask
Register
Type
Operand
Write-only
OP[7:0]
OP[n]
0
1
2
3
4
5
6
7
OP[2]
OP[1]
OP[0]
Data
0B: Bank Refresh enabled (default) : Unmasked
1B: Bank Refresh disabled : Masked
Bank Mask
xxxxxxx1
xxxxxx1x
xxxxx1xx
xxxx1xxx
xxx1xxxx
xx1xxxxx
x1xxxxxx
1xxxxxxx
Notes
1
8-Bank SDRAM
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
1. When a mask bit is asserted (OP[n]=1), refresh to that bank is disabled.
2. PASR bank masking is on a per channel basis. The two channels on the die may have different bank masking.
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H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
3.3.18. MR17 Register Information (MA[5:0] = 11H)
OP[7]
Function
PASR Segment Mask
Segment
OP[n]
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Segment
Mask
xxxxxxx1
xxxxxx1x
xxxxx1xx
xxxx1xxx
xxx1xxxx
xx1xxxxx
x1xxxxxx
1xxxxxxx
OP[6]
OP[5]
OP[4]
OP[3]
PASR Segment Mask
Register
Type
Operand
Write-only
OP[7:0]
OP[2]
OP[1]
OP[0]
Data
Notes
0B: Segment Refresh enabled (default)
1B: Segment Refresh disabled
1
4Gb
6Gb
8Gb
12Gb
16Gb
24Gb
32Gb
R13:R11
R14:R12
R14:R12
R15:R13
R15:R13
TBD
TBD
110B
111B
000B
001B
010B
011B
100B
101B
Not
Allowed
110B
111B
Not
Allowed
110B
111B
110B
111B
Not
Allowed
1. This table indicates the range of row addresses in each masked segment. “X” is don’t care for a particular segment.
2. PASR segment-masking is on a per-channel basis. The two channels on the die may have different segment masking.
3. For 6Gb, 12Gb, and 24Gb densities, OP[7:6] must always be LOW (=00B).
3.3.19. MR18 Register Information (MA[5:0] = 12H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
DQS Oscillator Count - LSB
Function
Register
Type
Operand
DQS Oscillator
(WR Training DQS Oscillator)
Read-only
OP[7:0]
OP[2]
OP[1]
OP[0]
Data
0:255 LSB DRAM DQS Oscillator Count
Notes
1,2,3
1. MR18 reports the LSB bits of the DRAM DQS Oscillator count. The DRAM DQS Oscillator count value is used to train DQS to the
DQ data valid window. The value reported by the DRAM in this mode register can be used by the memory controller to periodically
adjust the phase of DQS relative to DQ.
2. Both MR18 and MR19 must be read (MRR) and combined to get the value of the DQS Oscillator count.
3. A new MPC [Start DQS Oscillator] should be issued to reset the contents of MR18/MR19.
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H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
3.3.20. MR19 Register Information (MA[5:0] = 13H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
DQS Oscillator Count - MSB
Function
Register
Type
Operand
DQS Oscillator
(WR Training DQS Oscillator)
Read-only
OP[7:0]
OP[1]
OP[0]
Data
Notes
0:255 MSB DRAM DQS Oscillator Count
1,2
1. MR19 reports the MSB bits of the DRAM DQS Oscillator count. The DRAM DQS Oscillator count value is used to train DQS to the
DQ data valid window. The value reported by the DRAM in this mode register can be used by the memory controller to periodically
adjust the phase of DQS relative to DQ.
2. Both MR18 and MR19 must be read (MRR) and combined to get the value of the DQS Oscillator count.
3. A new MPC [Start DQS Oscillator] should be issued to reset the contents of MR18/MR19.
3.3.21. MR20 Register Information (MA[5:0] = 14H)
OP[7]
Function
Upper Byte Invert for
DQ Calibration
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
Upper Byte Invert Register for DQ Calibration
Register
Type
Operand
OP[1]
OP[0]
Data
Notes
The following values may be written for any operand
OP[7:0], and will be applied to the corresponding DQ locations DQ[15:8] within a byte lane:
Write
OP[7:0]
0B: Do not invert
1B: Invert the DQ Calibration patterns in MR32 and MR40
1,2
Default value for OP[7:0]=55H
1. This register will invert the DQ Calibration pattern found in MR32 and MR40 for any single DQ, or any combination of DQ’s. Example: If MR20 OP[7:0]=00010101B, then the DQ Calibration patterns transmitted on DQ[15,14,13,11,9] will not be inverted, but
the DQ Calibration patterns transmitted on DQ[12,10,8] will be inverted.
2. DMI[1] is not inverted, and always transmits the “true” data contained in MR32/MR40.
3. No Data Bus Inversion (DBI) function is enacted during DQ Read Calibration, even if DBI is enabled in MR3-OP[6].
Pin
MR20
DQ8
OP0
DQ9
OP1
Table - MR20 Invert Register Pin Mapping
DQ10
DQ11
DMI1
DQ12
OP2
OP3
No-invert
OP4
Rev 1.1 / Sep 2016 / SK hynix Confidential
DQ13
OP5
DQ14
OP6
DQ15
OP7
34
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
3.3.22. MR21 Register Information (MA[5:0] = 15H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
Vendor Specific Mode Registor
OP[1]
OP[0]
OP[1]
SOC ODT
OP[0]
3.3.23. MR22 Register Information (MA[5:0] = 16H)
OP[7]
OP[6]
RFU
Function
OP[5]
OP[4]
OP[3]
ODTD-CA ODTE-CS ODTE-CK
Register
Type
SoC ODT
(Controller ODT Value for VOH calibration
ODTE-CK
(CK ODT enabled for non-terminating rank)
ODTE-CS
(CS ODT enable for non-terminating
rank)
ODTD-CA
(CA ODT termination disable)
Operand
OP[2:0]
Write
OP[2]
Data
000B:
001B:
010B:
011B:
100B:
101B:
110B:
111B:
Disable (Default)
RZQ/1
RZQ/2
RZQ/3
RZQ/4
RZQ/5
RZQ/6
RFU
Notes
1,2,3
OP[3]
0B: ODT-CK Over-ride Disabled (Default)
1B: ODT-CK Over-ride Enabled
2,3,4,
6,8
OP[4]
0B: ODT-CS Over-ride Disabled (Default)
1B: ODT-CS Over-ride Enabled
2,3,5,
6,8
OP[5]
0B: ODT-CA Obeys ODT_CA bond pad (default) 2,3,6,
1B: ODT-CA Disabled
7,8
Notes:
1. All values are “typical".
2. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers
for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR
address, or read from with an MRR command to this address.
3. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will
operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of
the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be
changed without affecting device operation.
4. When OP[3]=1, then the CK signals will be terminated to the value set by MR11-OP[6:4] regardless of the state of the ODT_CA
bond pad. This overrides the ODT_CA bond pad for configurations where CA is shared by two or more DRAMs but CK is not, allowing CK to terminate on all DRAMs.
5. When OP[4]=1, then the CS signal will be terminated to the value set by MR11-OP[6:4] regardless of the state of the ODT_CA
bond pad. This overrides the ODT_CA bond pad for configurations where CA is shared by two or more DRAMs but CS is not, allowing CS to terminate on all DRAMs.
6. For system configurations where the CK, CS, and CA signals are shared between packages, the package design should provide for
the ODT_CA ball to be bonded on the system board outside of the memory package. This provides the necessary control of the
ODT function for all die with shared Command Bus signals.
7. When OP[5]=0, CA[5:0] will terminate when the ODT_CA bond pad is HIGH and MR11-OP[6:4] is VALID, and disables termination
when ODT_CA is LOW or MR11-OP[6:4] is disabled. When OP[5]=1, termination for CA[5:0] is disabled, regardless of the state
of the ODT_CA bond pad or MR11-OP[6:4].
8. To ensure proper operation in a multi-rank configuration, when CA, CK or CS ODT is enabled via MR11 OP[6:4] and also via MR22
Rev 1.1 / Sep 2016 / SK hynix Confidential
35
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
or CA-ODT pad setting, the rank providing ODT will continue to terminate the command bus in all DRAM states including Active
Self-refresh, Self-refresh Power-down, Active Power-down and Precharge Power-down.
3.3.24. MR23 Register Information (MA[5:0] = 17H)
OP[7]
Register
Type
Function
DQS oscillator
run time
Write
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
DQS oscillator run time setting
Operand
OP[7:0]
OP[1]
OP[0]
Data
Notes
00000000B: DQS timer stops via MPC Command (Default)
00000001B: DQS timer stops automatically at 16th clocks after
timer start
00000010B: DQS timer stops automatically at 32nd clocks after
timer start
00000011B: DQS timer stops automatically at 48th clocks after
timer start
00000100B: DQS timer stops automatically at 64th clocks after
timer start
-------------- Thru ---------------------00111111B: DQS timer stops automatically at (63X16)th clocks
after timer start
01XXXXXXB: DQS timer stops automatically at 2048th clocks
after timer start
10XXXXXXB: DQS timer stops automatically at 4096th clocks
after timer start
11XXXXXXB: DQS timer stops automatically at 8192nd clocks
after timer start
1, 2
Note:
1. MPC command with OP[6:0]=1001101B (Stop DQS Interval Oscillator) stops DQS interval timer in case of MR23 OP[7:0] =
00000000B.
2. MPC command with OP[6:0]=1001101B (Stop DQS Interval Oscillator) is illegal with non-zero values in MR23 OP[7:0].
3.3.25. MR24 Register Information (MA[5:0] = 18H)
OP[7]
TRR Mode
OP[6]
OP[5]
OP[4]
TRR Mode
Bank Address
Rev 1.1 / Sep 2016 / SK hynix Confidential
OP[3]
Unlimited
MAC
OP[2]
OP[1]
OP[0]
MAC Value
36
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
Function
Register
Type
MAC Value
Operand
OP[2:0]
Read
Unlimited MAC
OP[3]
TRR Mode BAn
OP[6:4]
Write
TRR Mode
OP[7]
Data
Notes
000B: Unknown when bit OP3 =0 (note 1)
Unlimited when bit OP3=1 (note 2)
001B: 700K
010B: 600K
011B: 500K
100B: 400K
101B: 300K
110B: 200K
111B: Reserved
0B: OP[2:0] define MAC value
1B: Unlimited MAC value (note 2, note 3)
000B: Bank 0
001B: Bank 1
010B: Bank 2
011B: Bank 3
100B: Bank 4
101B: Bank 5
110B: Bank 6
111B: Bank 7
0B: Disabled (default)
1B: Enabled
Note:
1. Unknown means that the device is not tested for tMAC and pass/fail value in unknown.
2. There is no restriction to number of activates.
3. MR24 OP [2:0] is set to zero.
3.3.26. MR25 Register Information (MA[5:0] = 19H)
OP[7]
Bank 7
OP[6]
Bank 6
OP[5]
Bank 5
Function
Register
Type
Operand
PPR Resource
Read
OP[7:0]
OP[4]
Bank 4
OP[3]
Bank 3
OP[2]
Bank 2
OP[1]
Bank 1
OP[0]
Bank 0
Data
Notes
0B: PPR Resource is not available
1B: PPR Resource is available
3.3.27. MR26:31 Register Information (MA[5:0] = 1AH:1FH)
OP[7]
OP[6]
Rev 1.1 / Sep 2016 / SK hynix Confidential
OP[5]
OP[4]
OP[3]
Reserved
OP[2]
OP[1]
OP[0]
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H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
3.3.28. MR32 Register Information (MA[5:0] = 20H)
OP[7]
Function
Return DQ Calibration
Pattern MR32 + MR40
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
DQ Calibration Pattern “A” (default = 5AH)
Register
Type
Write
OP[1]
OP[0]
Operand
Data
Notes
OP[7:0]
XB: An MPC command with OP[6:0]=0000011B
causes the device to return the DQ Calibration
Pattern contained in this register and (followed
by) the contents of MR40. A default pattern “5AH”
is loaded at power-up or RESET, or the pattern
may be overwritten with a MRW to this register.
The contents of MR15 and MR20 will invert the
data pattern for a given DQ (See MR15 for more
information)
3.3.29. MR33:39 Register Information (MA[5:0] = 21H:27H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
Do Not Use
OP[2]
OP[1]
OP[0]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
DQ Calibration Pattern “B” (default = 3CH)
OP[1]
OP[0]
3.3.30. MR40 Register Information (MA[5:0] = 28H)
OP[7]
Function
Return DQ Calibration
Pattern MR32 + MR40
Register
Type
Write
Operand
OP[7:0]
Data
Notes
XB: A default pattern “3CH” is loaded at power-up
or RESET, or the pattern may be overwritten with
1,2,3,4
a MRW to this register.
See MR32 for more information.
Notes:
1. The pattern contained in MR40 is contatenated to the end of MR32 and transmitted on DQ[15:0] and DMI[1:0] when DQ Read
Calibration is initiated via a MPC command. The pattern transmitted serially on each data lane, organized “little endian” such that
the low-order bit in a byte is transmitted first. If the data pattern in MR40 is 27H, then the first bit transmitted with be a ‘1’, followed
by ‘1’, ‘1’, ‘0’, ‘0’, ‘1’, ‘0’, and ‘0’. The bit stream will be 00100111B.
2. MR15 and MR22 may be used to invert the MR32/MR40 data patterns on the DQ pins. See MR15 and MR22 for more information.
Data is never inverted on the DMI[1:0] pins.
3. The data pattern is not transmitted on the DMI[1:0] pins if DBI-RD is disabled via MR3-OP[6].
4. No Data Bus Inversion (DBI) function is enacted during DQ Read Calibration, even if DBI is enabled in MR3-OP[6].
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38
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4. LPDDR4 Command Definitions and Timing Diagrams
4.1. Activate Command
The ACTIVATE command is composed of two consecutive commands, Activate-1 command and Activate-2.
Activate-1 command is issued by holding CS HIGH, CA0 HIGH and CA1 LOW at the first rising edge of the
clock and Activate-2 command issued by holding CS HIGH, CA0 HIGH and CA1 HIGH at the first rising edge
of the clock. The bank addresses BA0, BA1 and BA2 are used to select desired bank. Row addresses are
used to determine which row to activate in the selected bank. The ACTIVATE command must be applied
before any READ or WRITE operation can be executed. The device can accept a READ or WRITE command
at tRCD after the ACTIVATE command is issed. After a bank has been activated it must be precharged before
another ACTIVATE commnand can be applied to the same bank. The bank active and precharge times are
defined as tRAS and tRP respectively. The minimum time interval between ACTIVATE commands to the same
bank is determined by the RAS cycle time of the device(tRC). The minimum time interval between ACTIVATE
commands to different banks is tRRD.
CK_t
CK_c
CS
CA0-5
Bank A
RowAddrRowAddrRowAddrRowAddr
Valid
Valid
Bank A
Bank B
RowAddrRowAddrRowAddrRowAddr Col Addr Col Addr Col Addr Col Addr
Valid
Valid
Bank A
Bank
Addr.
tRRD
Valid
Valid
Valid
Valid
Bank A
RowAddrRowAddrRowAddrRowAddr
tRP
tRCD
CMD
Activate-1
Activate-2
Valid
Activate-1
Activate-2
Read-1
CAS-2
Valid
Precharge
Valid
Valid
Activate-1
Activate-2
tRC
tRAS
Figure - Activate Command Timing Example
Note : A PRECHARGE command uses tRPab timing for all-bank PRECHARGE and tRPpb timing for single-bank PRECHARGE. In this figure, tRP is used to denote either all-bank PRECHARGE or a single-bank PRECHARGE.
4.1.1. 8-Bank Device Operation
Certain restrictions on operation of the 8-bank LPDDR4 devices must be observed. There are two rules: One
rule restricts the number of sequential ACTIVATE commands that can be issued; the other provides more
time for RAS precharge for a PRECHARGE ALL command. The rules are as follows:
8 bank device Sequential Bank Activation Restriction: No more than 4 banks may be activated (or
refreshed, in the case of REFpb) in a rolling tFAW window. The number of clocks in a tFAW period is dependent upon the clock frequency, which may vary. If the clock frequency is not changed over this period,
converting clocks is done by dividing tFAW[ns] by tCK[ns], and rounding up to the next integer value. As
Rev 1.1 / Sep 2016 / SK hynix Confidential
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H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
an example of the rolling window, if RU(tFAW/tCK) is 10 clocks, and an ACTIVATE command is issued in
clock n, no more than three further ACTIVATE commands can be issued at or between clock n + 1 and n
+ 9. REFpb also counts as bank activation for purposes of tFAW. If the clock frequency is changed during
the tFAW period, the rolling tFAW window may be calculated in clock cycles by adding up the time spent in
each clock period. The tFAW requirement is met when the previous n clock cycles exceeds the tFAW time.
The 8-Bank Device Precharge-All Allowance: tRP for a PRECHRGE ALL command must equal tRPab,
which is greater than tRPpb.
CK_t
CK_c
CS
CA0-5
CMD
Bank A
RowAddrRowAddrRowAddrRowAddr VALID
Activate-1
Activate-2
Bank B
VALID RowAddrRowAddrRowAddrRowAddr VALID
VALID
Activate-1
Activate-2
Bank C
VALID RowAddrRowAddrRowAddrRowAddr VALID
VALID
Activate-1
Bank D
VALID RowAddrRowAddrRowAddrRowAddr VALID
VALID
Activate-2
Activate-1
Activate-2
Bank E
VALID RowAddrRowAddrRowAddrRowAddr
VALID
Activate-1
Activate-2
tRRD
tRRD
tRRD
tRRD
tFAW
Figure - tFAW Timing Example
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H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.2. Read and Write Access Operations
After a bank has been activated, a read or write command can be executed. This is accomplished by asserting CKE asynchronously, with CS and CA[5:0] set to the proper state (see Command Truth Table) at a
rising edge of CK.
The LPDDR4-SDRAM provides a fast column access operation. A single Read or Write command will initiate
a burst read or write operation, where data is transferred to/from the DRAM on successive clock cycles.
Burst interrupts are not allowed, but the optimal burst length may be set on the fly (see command truth
table).
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H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.3. Read Preamble and Postamble
The DQS strobe for the LPDDR4-SDRAM requires a pre-amble prior to the first latching edge (the rising edge of DQS_t
with DATA "valid"), and it requires a post-amble after the last latching edge. The pre-amble and post-amble lengths are
set via mode register writes (MRW).
For READ operations the pre-amble is 2*tCK, but the pre-amble is static (no-toggle) or toggling, selectable via mode
register.
LPDDR4 will have a DQS Read post-amble of 0.5*tCK (or extended to 1.5*tCK). Standard DQS postamble will be
0.5*tCK driven by the DRAM for Reads. A mode register setting instructs the DRAM to drive an additional (extended)
one cycle DQS Read post-amble. The drawings below show examples of DQS Read post-amble for both standard
(tRPST) and extended (tRPSTE ) post-amble operation.
T0
T1
RD-1
RD-1
T2
T3
T4
Ta0
Ta1
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
Tb6
Tc0
Tc1
Tc2
Tc3
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Tc4
CK_c
CK_t
COMMAND
CAS-2 CAS-2
RL
DES
tDQSCK
tRPRE
DQS_c
DQS_t
tDQSQ
tRPST
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n10 n11 n12 n13 n14 m15
DQ
Note
1. BL = 16, Preamble = Toggling, Postamble = 0.5nCK
2. DQS and DQ terminated VSSQ.
3. DQS_t/DQS_c is "don't care" prior to the start of tRPRE.
No transition of DQS is implied, as DQS_t/DQS_c can be HIGH, LOW, or HI-Z prior to tRPRE.
TIME BREAK
Figure - DQS Read Preamble and Postamble: Toggling Preamble and 0.5nCK Postamble
T0
T1
RD-1
RD-1
T2
T3
T4
Ta0
Ta1
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
Tb6
Tc0
Tc1
Tc2
Tc3
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Tc4
CK_c
CK_t
COMMAND
CAS-2 CAS-2
RL
tDQSCK
DES
Extended tCK
Postamble
tRPRE
DQS_c
DQS_t
tDQSQ
DQ
tRPSTE
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n10 n11 n12 n13 n14 m15
Note
1. BL = 16, Preamble = Static, Postamble = 1.5nCK (Extended)
2. DQS and DQ terminated VSSQ.
3. DQS_t/DQS_c is "don't care" prior to the start of tRPRE.
No transition of DQS is implied, as DQS_t/DQS_c can be HIGH, LOW, or HI-Z prior to tRPRE.
TIME BREAK
Figure - DQS Read Preamble and Postamble: Static Preamble and 1.5nCK Postamble
Rev 1.1 / Sep 2016 / SK hynix Confidential
42
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.4. Burst Read Operation
A burst Read command is initiated with CKE, CS, and CA[5:0] asserted to the proper state at the rising edge
of CK, as defined by the Command Truth Table. The command address bus inputs determine the starting
column address for the burst. The two low-order address bits are not transmitted on the CA bus and are
implied to be “0”, so that the starting burst address is always a multiple of four (ex. 0x0, 0x4, 0x8, 0xC).
The read latency (RL) is defined from the last rising edge of the clock that completes a read command (Ex:
the second rising edge of the CAS-2 command) to the rising edge of the clock from which the tDQSCK delay
is measured. The first valid data is available RL * tCK + tDQSCK + tDQSQ after the rising edge of Clock that
completes a read command. The data strobe output is driven tRPRE before the first valid rising strobe edge.
The first data-bit of the burst is synchronized with the first valid (i.e. post-preamble) rising edge of the data
strobe. Each subsequent dataout appears on each DQ pin, edge-aligned with the data strobe. At the end
of a burst the DQS signals are driven for another half cycle post-amble, or for a 1.5-cycle postamble if the
programmable post-amble bit is set in the mode register. The RL is programmed in the mode registers. Pin
timings for the data strobe are measured relative to the cross-point of DQS_t and DQS_c.
Figure - Burst Read Timing. BL=16, Toggling tRPRE, Extended tRPST
CK_t
CK_c
CA0-5
tCCD
tCCD
Read1
BL
Bank
Col AP
CAS2
Col
Col
Valid
Valid
Read1
BL
Bank
Col AP
CAS2
Col
Col
Valid
Valid
RL
CMD
Read-1
Bank0
CAS-2
Col A
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
RL
Read-1
Bank0
Valid
CAS-2
Col B
Valid
Valid
Valid
Valid
Valid
Valid
Valid
tDQSCK
Valid
Valid
Valid
tDQSCK
DQS_t
DQS_c
tRPSTE
tRPRE
DQ[15:0]
/DMI[1:0]
VAL
VAL
VAL
VAL
VAL
VAL BANK0,
VAL VAL
VAL VAL Col-A
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL BANK0,
VAL VAL
VAL VAL Col-B
VAL
VAL
VAL
VAL
VAL
VAL
Notes:
1. DES commands are shown for ease of illustration; other commands may be valid at these times.
Figure - Burst Read followed by Burst Write. BL=16, Non-toggling tRPRE, Extended tRPST
CK_t
CK_c
CA0-5
Read1
BL
Bank
Col AP
CAS2
Col
Col
Valid
Valid
Valid
Valid
Valid
Valid
Write1
BL
Bank
Col AP
CAS2
Col
Col
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
BL/2
RL
WL
CMD
Read-1
CAS-2
Valid
Valid
Valid
Write or
Masked Write
CAS-2
Valid
Valid
tDQSCK
Valid
Valid
Valid
tDQSS
DQS_t
DQS_c
tRPSTE
tRPRE
DQ[15:0]
/DMI[1:0]
D out
VAL
VAL
VAL
VAL
VAL
D inVAL
VAL
VAL
Notes:
1. DES commands are shown for ease of illustration; other commands may be valid at these times.
Rev 1.1 / Sep 2016 / SK hynix Confidential
43
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
The minimum time from a Burst Read command to a Write or MASK WRITE command is defined by the read
latency (RL) and the burst length (BL). Minimum READ-to-WRITE or MASK WRITE latency is defined with
tRTW paramter and it is as following equation:
DQ ODT Disabled case; MR11 OP[2:0]=000b
tRTW = RL + RU(tDQSCK(max)/tCK) + BL/2 - WL + tWPRE + RD(tRPST)
DQ ODT Enabled case; MR11 OP[2:0]≠000b
tRTW = RL + RU(tDQSCK(max)/tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon,min/tCK) + 1
Rev 1.1 / Sep 2016 / SK hynix Confidential
44
Rev 1.1 / Sep 2016 / SK hynix Confidential
DQ[15:0]
/DMI[1:0]
DQS_t
DQS_c
CMD
CA0-5
CK_t
CK_c
Bank
Col AP
Read-1
Bank0
Read1
BL
Col
CAS-2
Col A
CAS2
Col
Valid
RL
Valid
Valid
tCCD
Bank
Col AP
Col
tRPRE
CAS-2
Col B
CAS2
Col
tDQSCK
Read-1
Bank0
Read1
BL
VAL
VAL
VAL
VAL
tCCD
Bank
Col AP
VAL
VAL
VAL
Col
VAL
CAS-2
Col A
CAS2
Col
tDQSCK
Read-1
Bank1
Read1
BL
VAL BANK0,
VAL VAL Col-A
VAL
VAL
Valid
RL
Valid
Valid
VAL
VAL
VAL
tCCD
Bank
Col AP
VAL
VAL
VAL
Col
VAL
CAS-2
Col B
CAS2
Col
tDQSCK
Read-1
Bank1
Read1
BL
VALBANK0,
VAL VAL
VAL
Col-B
Valid
RL
Valid
Valid
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
Valid
Valid
Valid
tDQSCK
Valid
Valid
Valid
VAL BANK1,
VAL VAL Col-A
VAL VAL
Valid
RL
Valid
Valid
VAL
VAL
Valid
Valid
Valid
VAL BANK1,
VAL VAL Col-B
VAL VAL
Valid
Valid
VAL
Valid
VAL
Valid
VAL
tRPSTE
Valid
VAL
Valid
Valid
Valid
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
Figure - Seamless Burst Read. BL=16, Toggling tRPRE, Extended tRPST
The seamless Burst READ operation is supported by placing a READ command at every tCCD(min) interval
for BL16 (or every 2 x tCCD for BL32). The seamless Burst READ can access any open bank.
45
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.5. Read Timing
The read timing is shown in following figure:
T0
T1
RD-1
RD-1
T2
T3
T4
Ta0
Ta1
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
Tb6
Tb7
Tc0
Tc1
Tc2
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Tc3
CK_c
CK_t
COMMAND
CAS-2 CAS-2
DES
tHZ(DQS)
RL
tDQSCK
tLZ(DQS)
tRPRE
DQS_c
DQS_t
tHZ(DQ)
tDQSQ
tRPST
tLZ(DQ)
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n10 n11 n12 n13 n14 n15
DQ
DMI
Note
1. BL = 16, Preamble = Toggling, Postamble = 0.5nCK
2. DQS, DQ and DMI terminated VSSQ.
3. Output driver does not turn on before an end point of tLZ(DQS) and tLZ(DQ).
4. Output driver does not turn off before an end point of tHZ(DQS) and tHZ(DQ)
TIME BREAK
Figure - Read Timing
Rev 1.1 / Sep 2016 / SK hynix Confidential
46
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.6. tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation
tHZ and tLZ transitions occur in the same time window as valid data transitions. These parameters are referenced to a
specific voltage level that specifies when the device output is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving
tLZ(DQS), tLZ(DQ).
This section shows a method to calculate the point when the device is no longer driving tHZ(DQS) and tHZ(DQ), or
begins driving tLZ(DQS), tLZ(DQ), by measuring the signal at two different voltages. The actual voltage measurement
points are not critical as long as the calculation is consistent. The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and
tHZ(DQ) are defined as single ended.
4.6.1. tLZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment)
CK_t - CK_c crossing at 2nd CAS-2 of Read Command
CK_t
CK_c
tLZ(DQS)
VOH
DQS_c
Vsw2
0.5 x VOH
Vsw1
End point: Extrapolated point
0V
tLZ(DQS) end point is above-mentiond extrapolated point.
Note
1. Conditions for Calibration: Pull Down Driver Ron = 40ohm, VOH = VDDQ/3
2. Termination condition for DQS_t and DQS_C = 50ohm to VSSQ.
3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances.
Use the actual VOH value for tHZ and tLZ measurements.
Figure - tLZ(DQS) method for calculating transitions and end point
Rev 1.1 / Sep 2016 / SK hynix Confidential
47
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
CK_t - CK_c crossing at 2nd CAS-2 of Read Command
CK_t
CK_c
tHZ(DQS)
End point: Extrapolated point
VOH
Vsw2
0.5 x VOH
Vsw1
0V
DQS_c
tHZ(DQS) end point is above-mentiond extrapolated point.
Note
1. Conditions for Calibration: Pull Down Driver Ron = 40ohm, VOH = VDDQ/3
2. Termination condition for DQS_t and DQS_C = 50ohm to VSSQ.
3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances.
Use the actual VOH value for tHZ and tLZ measurements.
Figure - tHZ(DQS) method for calculating transitions and end point
Table - Reference voltage for tLZ(DQS), tHZ(DQS) Timing Measurements
Measured Parameter
Symbol
Vsw1 [V]
Vsw2 [V]
DQS_c low-impedance time from CK_t, CK_c
tLZ(DQS)
0.4 x VOH
0.6 x VOH
DQS_c high impedance time from CK_t, CK_c
tHZ(DQS)
0.4 x VOH
0.6 x VOH
Rev 1.1 / Sep 2016 / SK hynix Confidential
48
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.6.2. tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment)
CK_t - CK_c crossing at 2nd CAS-2 of Read Command
CK_t
CK_c
tLZ(DQ)
VOH
DQs
Vsw2
0.5 x VOH
Vsw1
End point: Extrapolated point
0V
tLZ(DQ) end point is above-mentiond extrapolated point.
Note
1. Conditions for Calibration: Pull Down Driver Ron = 40ohm, VOH = VDDQ/3
2. Termination condition for DQ and DMI = 50ohm to VSSQ.
3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances.
Use the actual VOH value for tHZ and tLZ measurements.
Figure - tLZ(DQ) method for calculating transitions and end point
Rev 1.1 / Sep 2016 / SK hynix Confidential
49
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
CK_t - CK_c crossing at 2nd CAS-2 of Read Command
CK_t
CK_c
tHZ(DQ)
End point: Extrapolated point
VOH
Vsw2
0.5 x VOH
Vsw1
0V
DQs
tHZ(DQ) end point is above-mentiond extrapolated point.
Note
1. Conditions for Calibration: Pull Down Driver Ron = 40ohm, VOH = VDDQ/3
2. Termination condition for DQ and DMI = 50ohm to VSSQ.
3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances.
Use the actual VOH value for tHZ and tLZ measurements.
Figure - tHZ(DQ) method for calculating transitions and end point
Table - Reference voltage for tLZ(DQS), tHZ(DQS) Timing Measurements
Measured Parameter
Symbol
Vsw1 [V]
Vsw2 [V]
DQ low-impedance time from CK_t, CK_c
tLZ(DQ)
0.4 x VOH
0.6 x VOH
DQ high impedance time from CK_t, CK_c
tHZ(DQ)
0.4 x VOH
0.6 x VOH
Rev 1.1 / Sep 2016 / SK hynix Confidential
50
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.7. Write Preamble and Postamble
The DQS strobe for the LPDDR4-SDRAM requires a pre-amble prior to the first latching edge (the rising edge of DQS_t
with DATA "valid"), and it requires a post-amble after the last latching edge. The pre-amble and post-amble lengths are
set via mode register writes (MRW).
For WRITE operations, a 2*tCK pre-amble is required at all operating frequencies.
LPDDR4 will have a DQS Write post-amble of 0.5*tCK or extended to 1.5*tCK. Standard DQS post-amble will be 0.5*tCK
driven by the memory controller for Writes. A mode register setting instructs the DRAM to drive an additional (extended)
one cycle DQS Write post-amble. The drawings below show examples of DQS Write post-amble for both standard
(tWPST) and extended (tWPSTE ) post-amble operation.
T0
T1
T2
T3
Valid
Valid
Valid
Valid
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
Tb6
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Tb7
CK_c
CK_t
CKE
CS
CA
COMMAND
Write-1
CAS-2
WL
tDQSS
tWPRE
DES
tWPST
tDQS2DQ
Din
n0
Din
n1
BL/2
Din
n2
Din
n3
NOTES : 1. BL = 16, Postamble = 0.5nCK
2. DQS and DQ terminated VSSQ
3. DQS_t/DQS_c is “don’t care” prior to the start of tWPRE.
No transition of DQS is implied, as DQS_t/DQS_c can be HIGH, LOW, or HI-Z prior to tWPRE.
Din
n8
Din
n9
Din
n10
Din
n11
Din
n12
Din
n13
Din
n14
Din
n15
DON'T CARE
TIME BREAK
Figure - DQS Write Preamble and Postamble; 0.5nCK Postamble
Rev 1.1 / Sep 2016 / SK hynix Confidential
51
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
T0
T1
T2
T3
Valid
Valid
Valid
Valid
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
Tb6
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Tb7
CK_c
CK_t
CKE
CS
CA
COMMAND
Write-1
CAS-2
WL
tDQSS
tWPRE
DES
tWPST
tDQS2DQ
Din
n0
Din
n1
BL/2
Din
n2
Din
n3
NOTES : 1. BL = 16, Postamble = 1.5nCK
2. DQS and DQ terminated VSSQ
3. DQS_t/DQS_c is “don’t care” prior to the start of tWPRE.
No transition of DQS is implied, as DQS_t/DQS_c can be HIGH, LOW, or HI-Z prior to tWPRE.
Din
n8
Din
n9
Din
n10
Din
n11
Din
n12
Din
n13
Din
n14
Din
n15
DON'T CARE
TIME BREAK
Figure - DQS Write Preamble and Postamble: 1.5nCK Postamble
Rev 1.1 / Sep 2016 / SK hynix Confidential
52
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.8. Burst Write Operation
A burst WRITE command is initiated with CKE, CS, and CA[5:0] asserted to the proper state at the rising
edge of CK, as defined by the Command Truth Table. Column addresses C[3:2] should be driven LOW for
Burst WRITE commands, and column addresses C[1:0] are not transmitted on the CA bus (and are assumed
to be zero), so that the starting column burst address is always aligned with a 32B boundary. The write
latency (WL) is defined from the last rising edge of the clock that completes a write command (Ex: the second rising edge of the CAS-2 command) to the rising edge of the clock from which tDQSS is measured. The
first valid “latching” edge of DQS must be driven WL * tCK + tDQSS after the rising edge of Clock that completes a write command.
The LPDDR4-SDRAM uses an un-matched DQS-DQ path for lower power, so the DQS-strobe must arrive at
the SDRAM ball prior to the DQ signal by the amount of tDQS2DQ. The DQS-strobe output is driven tWPRE
before the first valid rising strobe edge. The tWPRE, write pre-amble, is required to be 2 x tCK. The DQSstrobe must be trained to arrive at the DQ pad center-aligned with the DQ-data. The DQ-data must be held
for tDIVW (data input valid window) and the DQS must be periodically trained to stay centered in the tDIVW
window to compensate for timing changes due to temperature and voltage variation. Burst data is captured
by the SDRAM on successive edges of DQS until the 16 or 32 bit data burst is complete. The DQS-strobe
must remain active (toggling) for tWPST (WRITE post-amble) after the completion of the burst WRITE. After
a burst WRITE operation, tWR must be satisfied before a PRECHARGE command to the same bank can be
issued. Pin input timings are measured relative to the crosspoint of DQS_t and DQS_c.
Figure - Burst Write Operation
T0
T1
T2
T3
BL
BA0,
CA, AP
CA
CA
T4
Ta1
Ta0
Ta2
Ta3
Ta5
Ta4
Ta6
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Valid
BA0
Tc3
Tc4
Td0
Td1
Td2
Td3
Tb4
Td5
RA
BA0,
RA
RA
RA
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
DES
DES
DES
WL
DES
DES
DES
DES
DES
DES
BL/2 + 1 Clock
tDQSS (Min)
tWPRE
Precharge
DES
tWR
tDSS
DES
DES
DES
DES
ACT-1
ACT-2
tRP
tDSH
tDSS
DQS_c
DES
tDSH
tWPST
DQS_t
tDQS2DQ
Din Din Din Din Din Din Din Din Din Din
n0 n1 n2 n3 n4 n5 n12 n13 n14 n15
DQ
tWPRE
tDQSS (Max)
DQS_c
DQS_t
DQ
tDQS2DQ
Din Din Din Din Din Din Din Din Din Din
n0 n1 n2 n3 n4 n11 n12 n13 n14 n15
Note
1. BL=16, Write Postamble = 0.5nCK, DQ/DQS: VSSQ termination
2. Din n = data-in to columnm.n
3. The minimum number of clock cycles from the burst write command to the burst read command for any bank is [WL + 1 + BL/2 + RU(tWR/tCK)].
4. tWR starts at the rising edge of CK after the last latching edge of DQS.
5. DES commands are shown for ease of illustration; other commands may be valid at these times.
DON'T CARE
TIME BREAK
Notes
1. BL=16, Write Postamble = 0.5nCK, DQ/DQS: VSSQ termination
2. Din n = data-in to columnm.n
Rev 1.1 / Sep 2016 / SK hynix Confidential
53
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
3. The minimum number of clock cycles from the burst write command to the precharge command for any bank is [WL + 1 + BL/2
+ RU(tWR/tCK)].
4. tWR starts at the rising edge of CK after the last latching edge of DQS.
5. DES commands are shown for ease of illustration; other commands may be valid at these times.
Figure - Burst Write Followed by Burst Read
T0
T1
T2
T3
BL
BA0,
CA, AP
CA
CA
T4
Ta1
Ta0
Ta2
Ta3
Ta4
Ta5
Ta6
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
BL
BA0,
CA, AP
CA
CA
Tc7
Tc8
Tc9
Tc10
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
DES
DES
DES
WL
DES
DES
DES
DES
DES
DES
BL/2 + 1 Clock
tDQSS (Min)
tWPRE
DQS_c
DES
DES
DES
DES
Read-1
CAS-2
tWTR
tDSS
RL
tDSH
tDSS
tDSH
tWPST
DQS_t
DQ
tDQS2DQ
Din Din Din Din Din Din Din Din Din Din
n0 n1 n2 n3 n4 n5 n12 n13 n14 n15
Note
1. BL=16, Write Postamble = 0.5nCK, DQ/DQS: VSSQ termination
2. Din n = data-in to columnm.n
3. The minimum number of clock cycles from the burst write command to the burst read command for any bank is [WL + 1 + BL/2 + RU(tWTR/tCK)].
4. tWTR starts at the rising edge of CK after the last latching edge of DQS.
5. DES commands are shown for ease of illustration; other commands may be valid at these times.
DON'T CARE
TIME BREAK
Notes
1. BL=16, Write Postamble = 0.5nCK, DQ/DQS: VSSQ termination
2. Din n = data-in to columnm.n
3. The minimum number of clock cycles from the burst write command to the burst read command for any bank is [WL + 1 + BL/2
+ RU(tWTR/tCK)].
4. tWTR starts at the rising edge of CK after the last latching edge of DQS.
5. DES commands are shown for ease of illustration; other commands may be valid at these times.
Rev 1.1 / Sep 2016 / SK hynix Confidential
54
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.9. Write Timing
The write timing is shown in the following figure
T0
T1
T2
T3
BL
BA0,
CA, AP
CA
CA
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
DES
DES
DES
DES
DES
DES
DES
DES
Tb0
Tb1
Tb2
Tb3
Tb4
DES
DES
DES
DES
DES
Tb5
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
WL
tDQSS (Min)
tDSS
tWPRE
tDSH
tDSS
DQS_c
tDSH
tWPST
DQS_t
tDQS2DQ
Din Din Din Din Din Din Din Din Din Din
n0 n1 n2 n3 n4 n5 n12 n13 n14 n15
DQ
tDQSS (Max)
tWPRE
tDQSH
tDQSL
DQS_c
DQS_t
DQ
tDQS2DQ
Din Din Din Din Din Din Din Din Din Din
n0 n1 n2 n3 n4 n11 n12 n13 n14 n15
Note
1. BL=16, Write Postamble = 0.5nCK
2. Din n = data-in to columnm.n
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
DON'T CARE
TIME BREAK
Figure - Write Timing
Rev 1.1 / Sep 2016 / SK hynix Confidential
55
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.9.1. tWPRE Calculation for ATE (Automated Test Equipment)
The method for calculating differential pulse widths for tWPRE is shown in the following figure
CK_t
VrefCA
CK_c
Resulting differential signal
relevant for tWPRE specification
Vsw2
Vsw1
DQS_t - DQS_c
0V
Begin point:
Extrapolated point
tWPRE
Note
1. Termination condition for DQS_t, DQS_c, DQ and DMI = 50ohm to VSSQ.
Figure - Method for calculating tWPRE transitions and endpoints
Table - Reference Voltage for tWPRE Timing Measurements
Measured Parameter
Symbol
Vsw1 [V]
DQS_t, DQS_c differential Write Preamble
tWPRE
VIHL_AC x 0.3
Rev 1.1 / Sep 2016 / SK hynix Confidential
Vsw2 [V]
VIHL_AC x 0.7
56
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.9.2. tWPST Calculation for ATE (Automatic Test Equipment)
The method for calculating differential pulse widths for tWPST is shown in the follwing figure
CK_t
VrefCA
CK_c
Resulting differential signal
relevant for tWPST specification
0V
Vsw2
Vsw1
DQS_t - DQS_c
End point: Extrapolated point
tWPST
Note
1. Termination condition for DQS_t, DQS_c, DQ and DMI = 50ohm to VSSQ.
2. Write Postamble: 0.5tCK
3. The method for calculating differential pulse widths for 1.5 tCK Postamble is
same as 0.5 tCK Postamble.
Figure - Method for calculating tWPST transitions and endpoints
Table - Reference Voltage for tWPRE Timing Measurements
Measured Parameter
Symbol
Vsw1 [V]
DQS_t, DQS_c differential Write Preamble
tWPST
- (VIHL_AC x 0.7)
Rev 1.1 / Sep 2016 / SK hynix Confidential
Vsw2 [V]
- (VIHL_AC x 0.3)
57
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.10. Postamble and Preamble merging behavior
The DQS strobe for the device requires a preamble prior to the first latching edge (the rising edge of DQS_t with data
valid), and it requires a postamble after the last latching edge. The preamble and postamble options are set via Mode
Register Write commands.
In Read to Read or Write to Write operations with tCCD=BL/2, postamble for 1st command and preamble for 2nd command will disappear to create consecutive DQS latching edge for seamless burst operations.
But in the case of Read to Read or Write to Write operations with command interval of tCCD+1,tCCD+2, etc., they will
not completely disappear because it’s not seamless burst operations.
Timing diagrams in this material describe Postamble and Preamble merging behavior in Read to Read or Write to Write
operations with tCCD+n.
4.10.1. Read to Read Operation
T0
T1
T2
T3
BL
BA0,
CA, AP
CAn
CAn
T4
T7
T8
T9
T10
T11
BA0,
CA, AP CAm
CAm
T12
T13
T14
T15
T16
T17
T18
T19
T20
T26
T27
T28
T29
T30
T31
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Read-1
CAS-2
BL
DES
DES
Read-1
CAS-2
tCCD = 8
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPST
tRPRE
DQS_c
DQS_t
Hi-Z
Hi-Z
tDQSQ
DQ
Hi-Z
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 m0 m1 m12 m13 m14 m15
BL/2 = 8
Note
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Hi-Z
BL/2 = 8
DON'T CARE
TIME BREAK
Figure - Seamless Reads Operation: tCCD = Min, Preamble = Toggle, 1.5nCK Postamble
Rev 1.1 / Sep 2016 / SK hynix Confidential
58
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
T0
T1
T2
T3
BL
BA0,
CA, AP
CAn
CAn
T4
T7
T8
T9
T10
T11
T12
BA0,
CA, AP CAm
CAm
T13
T14
T15
T16
T17
T18
T19
T20
T21
T26
T27
T28
T29
T30
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Read-1
CAS-2
BL
DES
DES
DES
Read-1
CAS-2
tCCD = 9
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPST
DQS_c
Hi-Z
DQS_t
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
Hi-Z
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
Hi-Z
BL/2 = 8
BL/2 = 8
Note
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
DON'T CARE
TIME BREAK
Figure - Consecutive Reads Operation: tCCD = Min+1, Preamble=Toggle, 1.5nCK Postamble
T0
T1
T2
T3
BL
BA0,
CA, AP
CAn
CAn
T4
T7
T8
T9
T10
T11
T12
BA0,
CA, AP CAm
CAm
T13
T14
T15
T16
T17
T18
T19
T20
T21
T26
T27
T28
T29
T30
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Read-1
CAS-2
BL
DES
DES
DES
Read-1
CAS-2
tCCD = 9
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST tRPRE
DQS_c
DQS_t
Hi-Z
Hi-Z
tDQSQ
DQ
Hi-Z
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
BL/2 = 8
Note
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 0.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Hi-Z
tRPST
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
Hi-Z
BL/2 = 8
DON'T CARE
TIME BREAK
Figure - Consecutive Reads Operation: tCCD=Min+1, Preamble=Toggle, 0.5nCK Postamble
Rev 1.1 / Sep 2016 / SK hynix Confidential
59
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
T0
T1
T2
T3
BL
BA0,
CA, AP
CAn
CAn
T4
T7
T8
T9
T10
T11
T12
BA0,
CA, AP CAm
CAm
T13
T14
T15
T16
T17
T18
T19
T20
T21
T26
T27
T28
T29
T30
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Read-1
CAS-2
BL
DES
DES
DES
Read-1
CAS-2
tCCD = 9
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPST
DQS_c
Hi-Z
DQS_t
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
Hi-Z
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
Hi-Z
BL/2 = 8
BL/2 = 8
Note
1. BL = 16 for column n and column m, RL = 6, Preamble = Static, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
DON'T CARE
TIME BREAK
Figure - Consecutive Reads Operation: tCCD = Min +1, Preamble = Static, 1.5nCK Postamble
T0
T1
T2
T3
BL
BA0,
CA, AP
CAn
CAn
T4
T7
T8
T9
T10
T11
T12
BA0,
CA, AP CAm
CAm
T13
T14
T15
T16
T17
T18
T19
T20
T21
T26
T27
T28
T29
T30
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Read-1
CAS-2
BL
DES
DES
DES
Read-1
CAS-2
tCCD = 9
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPRE
tRPST
DQS_c
DQS_t
Hi-Z
Hi-Z
tDQSQ
DQ
Hi-Z
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
BL/2 = 8
Note
1. BL = 16 for column n and column m, RL = 6, Preamble = Static, Postamble = 0.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Hi-Z
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
Hi-Z
BL/2 = 8
DON'T CARE
TIME BREAK
Figure - Consecutive Reads Operation: tCCD = Min +1, Preamble = Static, 0.5nCK Postamble
Rev 1.1 / Sep 2016 / SK hynix Confidential
60
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
T0
T1
T2
T3
BL
BA0,
CA, AP
CAn
CAn
T4
T7
T8
T9
T10
T11
T12
T13
BA0,
CA, AP CAm
CAm
T14
T15
T16
T17
T18
T19
T20
T21
T22
T28
T29
T30
T31
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Read-1
CAS-2
BL
DES
DES
DES
DES
Read-1
CAS-2
tCCD = 10
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPRE
tRPST
DQS_c
Hi-Z
DQS_t
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
Hi-Z
Hi-Z
BL/2 = 8
BL/2 = 8
Note
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
DON'T CARE
TIME BREAK
Figure - Consecutive Reads Operation: tCCD = Min +2, Preamble = Toggle, 1.5nCK Postamble
T0
T1
T2
T3
BL
BA0,
CA, AP
CAn
CAn
T4
T7
T8
T9
T10
T11
T12
T13
BA0,
CA, AP CAm
CAm
T14
T15
T16
T17
T18
T19
T20
T21
T22
T28
T29
T30
T31
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Read-1
CAS-2
BL
DES
DES
DES
DES
Read-1
CAS-2
tCCD = 10
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPRE
tRPST
DQS_c
DQS_t
Hi-Z
Hi-Z
tDQSQ
DQ
Hi-Z
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
Hi-Z
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
BL/2 = 8
BL/2 = 8
Note
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 0.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
DON'T CARE
TIME BREAK
Figure - Consecutive Reads Operation: tCCD = Min +2, Preamble = Toggle, 0.5nCK Postamble
Rev 1.1 / Sep 2016 / SK hynix Confidential
61
Hi-Z
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
T0
T1
T2
T3
BL
BA0,
CA, AP
CAn
CAn
T4
T7
T8
T9
T10
T11
T12
T13
BA0,
CA, AP CAm
CAm
T14
T15
T16
T17
T18
T19
T20
T21
T22
T28
T29
T30
T31
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Read-1
CAS-2
BL
DES
DES
DES
DES
Read-1
CAS-2
tCCD = 10
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPRE
tRPST
DQS_c
Hi-Z
DQS_t
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
Hi-Z
Hi-Z
BL/2 = 8
BL/2 = 8
Note
1. BL = 16 for column n and column m, RL = 6, Preamble = Static, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
DON'T CARE
TIME BREAK
Figure - Consecutive Reads Operation: tCCD = Min +2, Preamble = Static, 1.5nCK Postamble
T0
T1
T2
T3
BL
BA0,
CA, AP
CAn
CAn
T4
T7
T8
T9
T10
T11
T12
T13
BA0,
CA, AP CAm
CAm
T14
T15
T16
T17
T18
T19
T20
T21
T22
T28
T29
T30
T31
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Read-1
CAS-2
BL
DES
DES
DES
DES
Read-1
CAS-2
tCCD = 10
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPRE
tRPST
DQS_c
DQS_t
Hi-Z
Hi-Z
tDQSQ
DQ
Hi-Z
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
Hi-Z
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
BL/2 = 8
Note
1. BL = 16 for column n and column m, RL = 6, Preamble = Static, Postamble = 0.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
BL/2 = 8
DON'T CARE
TIME BREAK
Figure - Consecutive Reads Operation: tCCD = Min +2, Preamble = Static, 0.5nCK Postamble
Rev 1.1 / Sep 2016 / SK hynix Confidential
62
Hi-Z
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
T0
T1
T2
T3
BL
BA0,
CA, AP
CAn
CAn
T4
T7
T8
T9
T10
T11
T13
T14
BA0,
CA, AP CAm
CAm
T12
T15
T16
T17
T18
T19
T20
T21
T22
T23
T29
T30
T31
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Read-1
CAS-2
BL
DES
DES
DES
DES
DES
Read-1
CAS-2
tCCD = 11
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPRE
tRPST
DQS_c
Hi-Z
DQS_t
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
Hi-Z
Hi-Z
BL/2 = 8
BL/2 = 8
Note
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
DON'T CARE
TIME BREAK
Figure - Consecutive Reads Operation: tCCD = Min +3, Preamble = Toggle, 1.5nCK Postamble
T0
T1
T2
T3
BL
BA0,
CA, AP
CAn
CAn
T4
T7
T8
T9
T10
T11
T13
T14
BA0,
CA, AP CAm
CAm
T12
T15
T16
T17
T18
T19
T20
T21
T22
T23
T29
T30
T31
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Read-1
CAS-2
BL
DES
DES
DES
DES
DES
Read-1
CAS-2
tCCD = 11
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPRE
tRPST
DQS_c
DQS_t
Hi-Z
Hi-Z
Hi-Z
tDQSQ
DQ
Hi-Z
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
Hi-Z
BL/2 = 8
Note
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 0.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
BL/2 = 8
DON'T CARE
TIME BREAK
Figure - Consecutive Reads Operation: tCCD = Min +3, Preamble = Toggle, 0.5nCK Postamble
Rev 1.1 / Sep 2016 / SK hynix Confidential
63
Hi-Z
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
T0
T1
T2
T3
BL
BA0,
CA, AP
CAn
CAn
T4
T7
T8
T9
T10
T11
T13
T14
BA0,
CA, AP CAm
CAm
T12
T15
T16
T17
T18
T19
T20
T21
T22
T23
T29
T30
T31
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Read-1
CAS-2
BL
DES
DES
DES
DES
DES
Read-1
CAS-2
tCCD = 11
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPRE
tRPST
DQS_c
Hi-Z
DQS_t
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
Hi-Z
Hi-Z
BL/2 = 8
BL/2 = 8
Note
1. BL = 16 for column n and column m, RL = 6, Preamble = Static, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
DON'T CARE
TIME BREAK
Figure - Consecutive Reads Operation: tCCD = Min +3, Preamble = Static, 1.5nCK Postamble
T0
T1
T2
T3
BL
BA0,
CA, AP
CAn
CAn
T4
T7
T8
T9
T10
T11
T13
T14
BA0,
CA, AP CAm
CAm
T12
T15
T16
T17
T18
T19
T20
T21
T22
T23
T29
T30
T31
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Read-1
CAS-2
BL
DES
DES
DES
DES
DES
Read-1
CAS-2
tCCD = 11
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPRE
tRPST
DQS_c
DQS_t
Hi-Z
Hi-Z
Hi-Z
tDQSQ
DQ
Hi-Z
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
Hi-Z
BL/2 = 8
Note
1. BL = 16 for column n and column m, RL = 6, Preamble = Static, Postamble = 0.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
BL/2 = 8
DON'T CARE
TIME BREAK
Figure - Consecutive Reads Operation: tCCD = Min +3, Preamble = Static, 0.5nCK Postamble
Rev 1.1 / Sep 2016 / SK hynix Confidential
64
Hi-Z
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.10.2. Write to Write operation
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T5
T6
T7
T8
T9
T10
T11
BL
BA0,
CA
CAm
CAm
T12
T13
T14
T15
T16
T17
T18
T23
T24
T25
T26
T27
T28
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
DES
DES
Write-1
tCCD = 8
WL = 4
CAS-2
WL = 4
tDQSS
tDQSS
tWPST
tWPRE
DQS_c
DQS_t
DQ
Don’t Care
Don’t Care
Don’t Care
tDQS2DQ
tDQS2DQ
Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 m0 m1 m2 m3 m12 m13 m14 m15
BL/2 = 8
Note
1. BL=16, Write Postamble = 0.5nCK
2. Dout n/m = data-in to column n and column m.
3. The minimum number of clock cycles from the burst write command to the burst write command for any bank is BL/2
4. DES commands are shown for ease of illustration; other commands may be valid at these times.
Don’t Care
BL/2 = 8
TIME BREAK
DON'T CARE
Figure - Seamless Writes Operation: tCCD = Min, 0.5nCK Postamble
Rev 1.1 / Sep 2016 / SK hynix Confidential
65
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T7
T8
T9
T10
T11
BL
BA0,
CA
CAm
CAm
T12
T13
T14
T15
T16
T17
T23
T24
T25
T31
T32
T33
T34
T35
T36
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
Write-1
DES
CAS-2
tCCD = 8
WL = 12
WL = 12
tDQSS
tDQSS
tWPST
tWPRE
DQS_c
DQS_t
DQ
Don’t Care
Don’t Care
tDQS2DQ
tDQS2DQ
Din Din Din Din Din Din Din Din Din Din Din Din
n0 n1 n2 n13 n14 n15 m0 m1 m2 m13 m14 m15
Don’t Care
ODTLon = 6
DRAM RTT
tODTon.Max
BL/2 = 8
ODT Hi-Z
Don’t Care
BL/2 = 8
ODT On
ODTLoff = 22
Note
1. Clock Frequency = 800MHz, tCK(AVG) = 1.25ns
2. BL=16, Write Postamble = 1.5nCK
3. Dout n/m = data-in to column n and column m.
3. The minimum number of clock cycles from the burst write command to the burst write command for any bank is BL/2
4. DES commands are shown for ease of illustration; other commands may be valid at these times.
ODT Hi-Z
tODToff.Min
TIME BREAK
DON'T CARE
Figure - Seamless Writes Operation: tCCD = Min, 1.5nCK Postamble,
533MHz < Clock Freq. ≤ 800MHz, ODT Worst Timing Case
Rev 1.1 / Sep 2016 / SK hynix Confidential
66
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T7
T8
T9
T10
T11
BL
BA0,
CA
CAm
CAm
T12
T15
T16
T17
T18
T19
T25
T26
T27
T33
T34
T35
T36
T37
T38
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
Write-1
CAS-2
tCCD = 8
WL = 14
tDQSS
WL = 14
tDQSS
tWPST
tWPRE
DQS_c
DQS_t
Don’t Care
DQ
Don’t Care
Don’t Care
tDQS2DQ
tDQS2DQ
Din Din Din Din Din Din Din Din Din Din Din Din
n0 n1 n2 n13 n14 n15 m0 m1 m2 m13 m14 m15
BL/2 = 8
Don’t Care
BL/2 = 8
Note
1. BL=16, Write Postamble = 1.5nCK
2. Dout n/m = data-in to column n and column m.
3. The minimum number of clock cycles from the burst write command to the burst write command for any bank is BL/2
4. DES commands are shown for ease of illustration; other commands may be valid at these times.
TIME BREAK
DON'T CARE
Figure - Seamless Writes Operation: tCCD = Min, 1.5nCK Postamble
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T8
T9
T10
T11
T12
BL
BA0,
CA
CAm
CAm
T13
T14
T15
T16
T17
T23
T24
T25
T26
T32
T33
T34
T35
T36
T36
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
Write-1
CAS-2
tCCD = 9
WL = 12
WL = 12
tDQSS
tDQSS
tWPST
tWPRE
DQS_c
DQS_t
Don’t Care
DQ
Don’t Care
Don’t Care
tDQS2DQ
tDQS2DQ
Din Din Din Din Din Din Dont’ Care Din Din Din Din Din Din
m0 m1 m2 m13 m14 m15
n0 n1 n2 n13 n14 n15
BL/2 = 8
Don’t Care
BL/2 = 8
Note
1. BL=16, Write Postamble = 0.5nCK
2. Dout n/m = data-in to column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
TIME BREAK
DON'T CARE
Figure - Consecutive Writes Operation: tCCD = Min + 1, 0.5nCK Postamble
Rev 1.1 / Sep 2016 / SK hynix Confidential
67
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T8
T9
T10
T11
T12
BL
BA0,
CA
CAm
CAm
T13
T14
T15
T16
T17
T23
T24
T25
T26
T32
T33
T34
T35
T36
T36
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
Write-1
CAS-2
tCCD = 9
WL = 12
WL = 12
tDQSS
tDQSS
tWPST
tWPRE
DQS_c
DQS_t
Don’t Care
DQ
Don’t Care
Don’t Care
tDQS2DQ
tDQS2DQ
Din Din Din Din Din Din Dont’ Care Din Din Din Din Din Din
m0 m1 m2 m13 m14 m15
n0 n1 n2 n13 n14 n15
BL/2 = 8
Don’t Care
BL/2 = 8
Note
1. BL=16, Write Postamble = 1.5nCK
2. Dout n/m = data-in to column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
TIME BREAK
DON'T CARE
Figure - Consecutive Writes Operation: tCCD = Min + 1, 1.5nCK Postamble
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T9
T10
T11
T12
T13
BL
BA0,
CA
CAm
CAm
T14
T15
T16
T17
T23
T24
T25
T26
T27
T33
T34
T35
T36
T37
T38
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
Write-1
CAS-2
tCCD = 10
WL = 12
WL = 12
tDQSS
tDQSS
tWPRE
tWPST
tWPRE
DQS_c
DQS_t
Don’t Care
DQ
Don’t Care
Don’t Care
tDQS2DQ
Din Din Din Din Din Din
n0 n1 n2 n13 n14 n15
BL/2 = 8
tWPST
Don’t Care
tDQS2DQ
Din Din Din Din Din Din
m0 m1 m2 m13 m14 m15
Don’t Care
BL/2 = 8
Note
1. BL=16, Write Postamble = 0.5nCK
2. Dout n/m = data-in to column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
TIME BREAK
DON'T CARE
Figure - Consecutive Writes Operation: tCCD = Min + 2, 0.5nCK Postamble
Rev 1.1 / Sep 2016 / SK hynix Confidential
68
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T9
T10
T11
T12
T13
BL
BA0,
CA
CAm
CAm
T14
T15
T16
T17
T23
T24
T25
T26
T27
T33
T34
T35
T36
T37
T38
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
CAS-2
Write-1
tCCD = 10
WL = 12
WL = 12
tDQSS
tDQSS
tWPRE
tWPST
tWPRE
DQS_c
Don’t Care
Don’t Care
DQS_t
tWPST
tDQS2DQ
Din Din Din Din Din Din
n0 n1 n2 n13 n14 n15
Don’t Care
DQ
tDQS2DQ
Din Din Din Din Din Din
m0 m1 m2 m13 m14 m15
Don’t Care
BL/2 = 8
Don’t Care
BL/2 = 8
Note
1. BL=16, Write Postamble = 1.5nCK
2. Dout n/m = data-in to column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
TIME BREAK
DON'T CARE
Figure - Consecutive Writes Operation: tCCD = Min + 2, 1.5nCK Postamble
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T9
T10
T11
T12
T13
T14
BL
BA0,
CA
CAm
CAm
T15
T16
T17
T23
T24
T25
T26
T27
T28
T34
T35
T36
T37
T38
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
DES
Write-1
CAS-2
tCCD = 11
WL = 12
WL = 12
tDQSS
tDQSS
tWPRE
tWPST
tWPRE
DQS_c
DQS_t
Don’t Care
tDQS2DQ
DQ
Don’t Care
Don’t Care
Dont’ Care
Din Din Din Din Din Din
n0 n1 n2 n13 n14 n15
BL/2 = 8
tWPST
tDQS2DQ
Don’t Care
Din Din Din Din Din Din
m0 m1 m2 m13 m14 m15
Don’t Care
BL/2 = 8
Note
1. BL=16, Write Postamble = 0.5nCK
2. Dout n/m = data-in to column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
TIME BREAK
DON'T CARE
Figure - Consecutive Writes Operation: tCCD = Min + 3, 0.5nCK Postamble
Rev 1.1 / Sep 2016 / SK hynix Confidential
69
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T9
T10
T11
T12
T13
T14
BL
BA0,
CA
CAm
CAm
T15
T16
T17
T23
T24
T25
T26
T27
T28
T34
T35
T36
T37
T38
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
DES
Write-1
CAS-2
tCCD = 11
WL = 12
WL = 12
tDQSS
tDQSS
tWPRE
tWPST
tWPRE
DQS_c
Don’t Care
Don’t Care
DQS_t
tWPST
tDQS2DQ
Din Din Din Din Din Din
n0 n1 n2 n13 n14 n15
Don’t Care
DQ
tDQS2DQ
Din Din Din Din Din Din
m0 m1 m2 m13 m14 m15
Don’t Care
BL/2 = 8
Don’t Care
BL/2 = 8
Note
1. BL=16, Write Postamble = 1.5nCK
2. Dout n/m = data-in to column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
TIME BREAK
DON'T CARE
Figure - Consecutive Writes Operation: tCCD = Min + 3, 1.5nCK Postamble
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T9
T10
T11
T12
T13
T14
BL
BA0,
CA
CAm
CAm
T15
T16
T17
T23
T24
T25
T26
T27
T28
T29
T35
T36
T37
T38
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
DES
Write-1
CAS-2
tCCD = 12
WL = 12
WL = 12
tDQSS
tDQSS
tWPRE
tWPST
tWPRE
DQS_c
DQS_t
Dont’ Care
Don’t Care
tDQS2DQ
DQ
Don’t Care
tWPST
Din Din Din Din Din Din
n0 n1 n2 n13 n14 n15
BL/2 = 8
Don’t Care
tDQS2DQ
Don’t Care
Din Din Din Din Din Din
m0 m1 m2 m13 m14 m15
Don’t Care
BL/2 = 8
Note
1. BL=16, Write Postamble = 1.5nCK
2. Dout n/m = data-in to column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
TIME BREAK
DON'T CARE
Figure - Consecutive Writes Operation: tCCD = Min + 4, 1.5nCK Postamble
Rev 1.1 / Sep 2016 / SK hynix Confidential
70
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.11. Masked Write Operation
The LPDDR4-SDRAM requires that Write operations which include a byte mask anywhere in the burst sequence must
use the Masked Write command. This allows the DRAM to implement efficient data protection schemes based on larger
data blocks. The Masked Write-1 command is used to begin the operation, followed by a CAS-2 command. A Masked
Write command to the same bank cannot be issued until tCCDMW is met, to allow the LPDDR4-SDRAM to finish the
internal Read-Modify-Write. One Data Mask-Invert (DMI) pin is provided per byte lane, and the Data Mask-Invert timings match data bit (DQ) timing. See the section on “Data Mask Invert” for more information on the use of the DMI
signal.
Figure - Masked Write Command - Same Bank (Shown with BL16, 2tCK Preamble)
CK_c
CK_t
CA
Bank 0
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Bank 0
Valid
Valid
Valid
tCCDMW
CMD
Masked Write
CAS-2
Valid
Valid
Valid
WL
tDQSS
Valid
Masked Write
CAS-2
DQS_c
DQS_t
tWPRE
tDQS2DQ
DQ[15:0]
DMI[1:0]
tWPST
Valid
Valid
Valid
Valid
Valid
Valid
Notes:
1. Masked Write supports only BL16 operations. For BL32 configuration, the system needs to insert only 16 bit wide data for masked
write operation.
Figure - Masked Write Command - Different Bank (shown with BL16, 2tCK Preamble)
CK_c
CK_t
CA
Bank 0
tCCD
tCCD
Bank 1
Bank 2
tCCDMW
tCCD
tCCD
Bank 3
Bank 0
WL
CMD
Mask Write
CAS-2
Mask Write
CAS-2
Mask Write
CAS-2
Mask Write
CAS-2
Mask Write
CAS-2
tDQSS
tWPST
DQS_c
DQS_t
tWPRE
Q[15:0]
DM[1:0]
tDQS2DQ
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Notes:
1. Masked Write supports only BL16 operations. For BL32 configuration, the system needs to insert only 16 bit wide data for masked
write operation.
Rev 1.1 / Sep 2016 / SK hynix Confidential
71
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.11.1. Masked Write Timing constraints
Table - Masked Write Timing constraints - Same bank
Read
Write
Activate
Masked Write
Precharge
(BL16 or 32)
(BL16 or 32)
Illegal
RU(tRCD/tCK)
RU(tRCD/tCK)
RU(tRCD/tCK)
RU(tRAS/tCK)
RL+RU(tDQSCK(max)/ RL+RU(tDQSCK(max)/
BL/2+max{(8,RU(tRTP/
Read (BL16)
Illegal
81)
tCK) +BL/2tCK) +BL/2tCK)}-8
WL+tWPRE+tRPST
WL+tWPRE+tRPST
RL+RU(tDQSCK(max)/ RL+RU(tDQSCK(max)/
BL/2+max{(8,RU(tRTP/
2)
tCK) +BL/2Read (BL32)
Illegal
16
tCK) +BL/2tCK)}-8
WL+tWPRE+tRPST
WL+tWPRE+tRPST
WL+ 1 + BL/2
WL+1+BL/2
tCCDMW3)
Write (BL16)
Illegal
81)
+RU(tWR/tCK)
+RU(tWTR/tCK)
WL+ 1 + BL/2
WL+1+BL/2
tCCDMW + 84)
Write (BL32)
Illegal
162)
+RU(tWR/tCK)
+RU(tWTR/tCK)
WL+ 1 + BL/2
WL+1+BL/2
Masked Write
Illegal
tCCD
tCCDMW3)
+RU(tWR/tCK)
+RU(tWTR/tCK)
RU(tRP/tCK),
Precharge
Illegal
Illegal
Illegal
4
RU(tRPab/tCK)
Next CMD
Current CMD
Activate
Notes:
1) In the case of BL = 16, tCCD is 8*tCK.
2) In the case of BL = 32, tCCD is 16*tCK.
3) tCCDMW = 32*tCK (4*tCCD at BL=16)
4) Write with BL=32 operation has 8*tCK longer than BL =16.
5) Units : tCK
Table - Masked Write Timing constraints - Different bank
Next CMD
Read
Write
Masked Write
Activate
Current CMD
(BL16 or 32)
(BL16 or 32)
(BL16)
Activate
RU(tRRD/tCK)
4
4
4
RL+RU(tDQSCK(max)/ RL+RU(tDQSCK(max)/
Read (BL16)
4
81)
tCK) +BL/2tCK) +BL/2WL+tWPRE+tRPST
WL+tWPRE+tRPST
RL+RU(tDQSCK(max)/ RL+RU(tDQSCK(max)/
tCK) +BL/2Read (BL32)
4
161)
tCK) +BL/2WL+tWPRE+tRPST
WL+tWPRE+tRPST
WL+1+BL/2
81)
Write (BL16)
4
81)
+RU(tWTR/tCK)
WL+1+BL/2
161)
Write (BL32)
4
161)
+RU(tWTR/tCK)
WL+1+BL/2
81)
Masked Write
4
81)
+RU(tWTR/tCK)
Precharge
4
4
4
4
Precharge
2
2
2
2
2
2
4
Notes:
1) In the case of BL = 16, tCCD is 8*tCK.
2) In the case of BL = 32, tCCD is 16*tCK.
3) Units : tCK
Rev 1.1 / Sep 2016 / SK hynix Confidential
72
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.12. LPDDR4 Data Mask (DM) and Data Bus Inversion (DBIdc) Function
LPDDR4 SDRAM supports the function of Data Mask and Data Bus inversion. Its details are shown below.
•
•
•
•
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LPDDR4 device supports Data Mask (DM) function for Write operation.
LPDDR4 device supports Data Bus Inversion (DBIdc) function for Write and Read operation.
LPDDR4 supports DM and DBIdc function with a byte granularity.
DBIdc function during Write or Masked Write can be enabled or disabled through MR3 OP[7].
DBIdc function during Read can be enabled or disabled through MR3 OP[6].
DM function during Masked Write can be enabled or disabled through MR13 OP[5].
LPDDR4 device has one Data Mask Inversion (DMI) signal pin per byte; total of 2 DMI signals per channel.
DMI signal is a bi-directional DDR signal and is sampled along with the DQ signals for Read and Write or Masked
Write operation.
There are eight possible combinations for LPDDR4 device with DM and DBIdc function. Table below describes the functional behavior for all combinations.
Table - Function Behaviour of DMI Signal During Write, Masked Write and Read Operation
DMI
DMI
DMI
DMI
DMI
DMI
DMI
Signal
Signal
Write
Read
Signal
Signal
Signal
Signal
DM
Signal
during
during
DBIdc DBIdc
during
during
during
during
Fuction
Masked during
MPC
Fuction Fuction
Write
MPC
MPC
MRR
Read
Write
[DQ Read
Command
[WR FIFO] [RD FIFO]
Command
Command
calibration]
Disable Disable Disable
Note: 1
Note: 1, 3 Note: 2
Note: 1
Note: 2
Note: 2
Note: 2
Disable Enable Disable
Note: 4
Note: 3
Note: 2
Note: 9
Note: 10
Note: 11
Note: 2
Disable Disable Enable
Note: 1
Note: 3
Note: 5
Note: 9
Note: 10
Note: 11
Note: 12
Disable Enable Enable
Note: 4
Note: 3
Note: 5
Note: 9
Note: 10
Note: 11
Note: 12
Enable Disable Disable
Note: 6
Note: 7
Note: 2
Note: 9
Note: 10
Note: 11
Note: 2
Enable Enable Disable
Note: 4
Note: 8
Note: 2
Note: 9
Note: 10
Note: 11
Note: 2
Enable Disable Enable
Note: 6
Note: 7
Note: 5
Note: 9
Note: 10
Note: 11
Note: 12
Enable Enable Enable
Note: 4
Note: 8
Note: 5
Note: 9
Note: 10
Note: 11
Note: 12
1.DMI input signal is a don’t care. DMI input receivers are turned OFF.
2.DMI output drivers are turned OFF.
3.Masked Write Command is not allowed and is considered an illegal command as DM function is disabled.
4.DMI signal is treated as DBI signal and it indicates whether DRAM needs to invert the Write data received on DQs within a byte.
The LPDDR4 device inverts Write data received on the DQ inputs in case DMI was sampled HIGH, or leaves the Write data noninverted in case DMI was sampled LOW.
5.The LPDDR4 DRAM inverts Read data on its DQ outputs associated within a byte and drives DMI signal HIGH when the number of
‘1’ data bits within a given byte lane is greater than four; otherwise the DRAM does not invert the read data and drives DMI signal
LOW.
6.The LPDDR4 DRAM does not perform any mask operation when it receives Write command. During the Write burst associated with
Write command, DMI signal must be driven LOW.
7.The LPDDR4 DRAM requires an explicit Masked Write command for all masked write operations. DMI signal is treated as DM signal
and it indicates which bit time within the burst is to be masked. When DMI signal is HIGH, DRAM masks that bit time across all
DQs associated within a byte. All DQ input signals within a byte are don’t care (either HIGH or LOW) when DMI signal is HIGH.
When DMI signal is LOW, the LPDDR4 DRAM does not perform mask operation and data received on DQ input is written to the
array.
8.The LPDDR4 DRAM requires an explicit Masked Write command for all masked write operations. The LPDDR4 device masks the
Write data received on the DQ inputs if the total count of ‘1’ data bits on DQ[2:7] or DQ[10:15] (for Lower Byte or Upper Byte
respectively) is equal to or greater than five and DMI signal is LOW. Otherwise the LPDDR4 DRAM does not perform mask operation
and treats it as a legal DBI pattern; DMI signal is treated as DBI signal and data received on DQ input is written to the array.
9. DMI signal is treated as a training pattern. The LPDDR4 SDRAM does not perform any mask operation and does not invert Write
data received on the DQ inputs.
10. DMI signal is treated as a training pattern. The LPDDR4 SDRAM returns DMI pattern written in WR-FIFO.
Rev 1.1 / Sep 2016 / SK hynix Confidential
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H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
11. DMI signal is treated as a training pattern. For more details, see MPC RD DQ Calibration session.
12. DBI may apply or may not apply during normal MRR. It's vendor specific. If read DBI is enable with MRS and vendor cannot
support the DBI during MRR, DBI pin status should be low.
If read DBI is enable with MRS and vendor can support the DBI during MRR, the LPDDR4 DRAM inverts Mode Register Read data
on its DQ outputs associated within a byte and drives DMI signal HIGH when the number of ‘1’ data bits within a given byte lane
is greater than four; otherwise the DRAM does not invert the read data and drives DMI signal LOW.
Figure - Masked Write Operation w/ Write DBI Enabled; DM Enabled
CK_c
CK_t
CKE
CS
CA
Bank 0
CMD
Valid
Masked Write
Valid
Valid
CAS-2
Valid
Valid
Valid
WL
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
tDQSS
DQS_c
DQS_t
tWPRE
DQ[7:0]
tDQS2DQ
tWPST
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
N
N
I
I
M
N
I
N
Valid
Valid
N M
Valid
Valid
N N
DMI[0]
Valid
Input data is written to DRAM cell.
Valid
Input data is inverted, then written to DRAM cell.
Valid
Input data is masked. The total count on DQ[7:2] is equal or greater than five.
Notes:
1. Data Mask (DM) is Enabled; MR13 OP[5]=1, Data Bus Inversion (DBI) Write is Enabled; MR3 OP[7]=1.
Rev 1.1 / Sep 2016 / SK hynix Confidential
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H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
Figure - Write Command w/ Write DBI Enabled; DM Disabled
CK_c
CK_t
CKE
CS
CA
CMD
Bank 0
Valid
Masked Write
Valid
Valid
CAS-2
Valid
Valid
Valid
WL
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
tDQSS
DQS_c
DQS_t
tWPRE
DQ[7:0]
tDQS2DQ
tWPST
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
N
N
I
I
N
N
I
N
Valid
Valid
N N
Valid
Valid
N N
DMI[0]
Valid
Input data is written to DRAM cell.
Valid
Input data is inverted, then written to DRAM cell.
Notes:
1. Data Mask (DM) is Disabled; MR13 OP[5]=0, Data Bus Inversion (DBI) Write is Enabled; MR3 OP[7]=1.
Rev 1.1 / Sep 2016 / SK hynix Confidential
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H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.13. Precharge Operation
The PRECHARGE command is used to precharge or close a bank that has been activated. The PRECHARGE command
is initiated with CS, and CA[5:0] in the proper state as defined by the Command Truth Table. The PRECHARGE command
can be used to precharge each bank independently or all banks simultaneously. The AB flag and the bank address bit
are used to determine which bank(s) to precharge. The precharged bank(s) will be available for subsequent row access
tRPab after an all-bank PRECHARGE command is issued, or tRPpb after a single-bank PRECHARGE command is issued.
To ensure that LPDDR4 devices can meet the instantaneous current demands, the row-precharge time for an all-bank
PRECHARGE (tRPab) is longer than the perbank precharge time (tRPpb).
AB
(CA[5], R1)
0
0
0
0
0
0
0
0
1
Table - Precharge Bank Selection
BA2
BA1
BA0
(CA[2], R2)
(CA[1], R2)
(CA[0], R2)
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Valid
Valid
Valid
Rev 1.1 / Sep 2016 / SK hynix Confidential
Precharged
Bank(s)
Bank 0 Only
Bank 1 Only
Bank 2 Only
Bank 3 Only
Bank 4 Only
Bank 5 Only
Bank 6 Only
Bank 7 Only
All banks
76
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.13.1. Burst Read Operation followed by Precharge
The PRECHARGE command can be issued as early as BL/2 clock cycles after a READ command, but PRECHARGE cannot
be issued until after tRAS is satisfied. A new bank ACTIVATE command can be issued to the same bank after the row
PRECHARGE time (tRP) has elapsed. The minimum READ-to-PRECHARGE time must also satisfy a minimum analog time
from the 2nd rising clock edge of the CAS-2 command. tRTP begins BL/2 . 8 clock cycles after the READ command. For
LPDDR4 READ-to-PRECHARGE timings see Table “Timing Between Commands (Precharge and Auto-Precharge)”.
Figure - Burst Read followed by Precharge (BL16, toggling pre-amble)
CK_t
CK_c
CA[5:0]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CAS-2
Read - 1
Valid
Valid
Valid
Valid
tRP
tRTP
CMD
Valid
Valid
Valid
Precharge
Valid
Valid
ACT1
Valid
ACT2
DQS_t
DQS_c
DQ[15:0]
DMI[1:0]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Figure - Burst Read followed by Precharge (BL32, Toggling Preamble)
CK_t
CK_c
CA[5:0]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CMD
Read - 1
CAS-2
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
tRP
tRTP
8 Clocks
Valid
Precharge
Valid
Valid
Valid
ACT1
ACT2
DQS_t
DQS_c
DQ[15:0]
DMI[1:0]
Rev 1.1 / Sep 2016 / SK hynix Confidential
Valid Valid Valid
Valid
Valid
Valid
Valid Valid
Valid Valid Valid
Valid
Valid
Valid
Valid Valid
77
H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.13.2. Burst Write followed by Precharge
A Write Recovery time (tWR) must be provided before a PRECHARGE command may be issued. This delay is referenced
from the next rising edge of CK_t after the last latching DQS clock of the burst.
LPDDR4-SDRAM devices write data to the memory array in prefetch multiples (prefetch=16). An internal WRITE operation can only begin after a prefetch group has been clocked, so tWR starts at the prefetch boundaries. The minimum
WRITE-to-PRECHARGE time for commands to the same bank is WL + BL/2 + 1 + RU(tWR/tCK) clock cycles.
Figure - Burst Write followed by Precharge (BL16, 2tCK preamble)
CK_t
CK_c
CA0-5
WR
WR
CAS
CAS
Valid
Valid
Valid
Valid
Valid
CMD
Write
CAS-2
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
BL/2 + 1 Clock
WL
Valid
Valid
Valid
Valid
Valid
tDQSS(max)
tWR
PRECHARGE
ACT-1
Valid
ACT-2
tRP
DQS_t
DQS_c
tDQS2DQ
DQ[15:0]
/DMI[1:0]
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
4.13.3. Auto Precharge operation
Before a new row can be opened in an active bank, the active bank must be precharged using either the PRECHARGE
command or the Auto-PRECHARGE function. When a READ, WRITE or Masked Write command is issued to the device,
the AP bit (CA5) can be set to enable the active bank to automatically begin precharge at the earliest possible moment
during the burst READ, WRITE or Masked Write cycle.
If AP is LOW when the READ, WRITE or Masked Write command is issued, then the normal READ, WRITE or Masked
Write burst operation is executed and the bank remains active at the completion of the burst.
If AP is HIGH when the READ, WRITE or Masked Write command is issued, the Auto-PRECHARGE function is engaged.
This feature enables the PRECHARGE operation to be partially or completely hidden during burst READ cycles (dependent upon READ or WRITE latency), thus improving system performance for random data access.
4.13.3.1. Burst Read with Auto-Precharge
If AP is HIGH when a READ command is issued, the READ with Auto-PRECHARGE function is engaged. An internal precharge procedure starts a following delay time after the READ command. And this delay time depends on BL setting.
BL = 16: tRTP
BL = 32: 8tCK + tRTP
For LPDDR4 Auto-PRECHARGE calculations, see Table 2. Following an Auto-PRECHARGE operation, an ACTIVATE command can be issued to the same bank if the following two conditions are both satisfied:
a. The RAS precharge time (tRP) has been satisfied from the clock at which the Auto-PRECHARGE began, or
b. The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Rev 1.1 / Sep 2016 / SK hynix Confidential
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H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
Figure - Burst Read with Auto-Precharge (BL16, Toggling preamble)
CK_t
CK_c
CA[5:0]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
READ-1
w/ AP
CAS-2
Valid
Valid
Valid
Valid
Valid
tRPpb
nRTP
CMD
Valid
Valid
Valid
Valid
Valid
ACT1
Valid
ACT2
DQS_t
DQS_c
DQ[15:0]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Figure - Burst Read with Auto-Precharge (BL32, Toggling preamble)
CK_t
CK_c
CA[5:0]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CMD
Read - 1
w/ AP
CAS-2
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
tRPpb
nRTP
8 Clocks
Precharge
Valid
Valid
Valid
ACT1
ACT2
DQS_t
DQS_c
DQ[15:0]
Rev 1.1 / Sep 2016 / SK hynix Confidential
Valid Valid Valid
Valid
Valid
Valid
Valid Valid
Valid Valid Valid
Valid
Valid
Valid
Valid Valid
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H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.13.3.2. Burst Write with Auto-Precharge
If AP is HIGH when a WRITE command is issued, the WRITE with Auto-PRECHARGE function is engaged.
The device starts an Auto-PRECHARGE on the rising edge tWR cycles after the completion of the Burst
WRITE.
Following a WRITE with Auto-PRECHARGE, an ACTIVATE command can be issued to the same bank if the
following conditions are met:
a. The RAS precharge time (tRP) has been satisfied from the clock at which the Auto-PRECHARGE began,
and
b. The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Table - Burst Write with Auto-Precharge (BL16, 2tCK preamble)
CK_t
CK_c
CA0-5
WR
WR
CAS
CAS
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
WL
CMD
Write
CAS-2
Valid
Valid
Valid
Valid
Valid
Valid
tDQSS(max)
Valid
ACT-1
Valid
tWR
ACT-2
tRP
DQS_t
DQS_c
tDQS2DQ
DQ[15:0]
/DMI[1:0]
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
Table - Timing Between Commands (Precharge and Auto-Precharge) - DQ ODT is Disabled
From
Minimum Delay between
To Command
Unit Notes
Command
“From Command” and “To Command”
Read
(BL16)
Read
(BL32)
Read w/ AP
(BL16)
Precharge
(to same bank as Read)
tRTP
tCK
1,6
Precharge All
tRTP
tCK
1,6
Precharge
(to same bank as Read)
8*tCK + tRTP
tCK
1,6
Precharge All
8*tCK + tRTP
tCK
1,6
Precharge
(to same bank as Read w/ AP)
nRTP
tCK
1,10
Precharge All
nRTP
tCK
1,10
Activate
(to same bank as Read w/ AP)
nRTP + tRPpb
tCK
1,8,10
Write or Write w/ AP
(same bank)
Illegal
-
3
Masked Write or Masked Write w/ AP
(same bank)
Illegal
-
Write or Write w/ AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+BL/2+RD(tRPST)WL+tWPRE
tCK
3,4,5
Masked Write or Masked Write w/ AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+BL/2+RD(tRPST)WL+tWPRE
tCK
3,4,5
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H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
From
Command
Read w/ AP
(BL16)
Read w/ AP
(BL32)
Write
(BL16 & BL32)
Masked Write
Write w/ AP
To Command
Minimum Delay between
Unit Notes
“From Command” and “To Command”
Read or Read w/ AP
(same bank)
Illegal
-
Read or Read w/ AP
(different bank)
BL/2
tCK
3
Precharge
(to same bank as Read w/ AP)
8*tCK + nRTP
tCK
1,10
Precharge All
8*tCK + nRTP
tCK
1,10
Activate
(to same bank as Read w/ AP)
8*tCK + nRTP + tRPpb
tCK
1,8,10
Write or Write w/ AP
(same bank)
Illegal
-
Masked Write or Masked Write w/ AP
(same bank)
Illegal
-
Write or Write w/ AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+BL/2+RD(tRPST)WL+tWPRE
tCK
3,4,5
Masked Write or Masked Write w/ AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+BL/2+RD(tRPST)WL+tWPRE
tCK
3,4,5
Read or Read w/ AP
(same bank)
Illegal
-
Read or Read w/ AP
(different bank)
BL/2
tCK
3
Precharge
(to same bank as Masked Write)
WL + BL/2 + tWR + 1
tCK
1,7
Precharge All
WL + BL/2 + tWR + 1
tCK
1,7
Precharge
(to same bank as Masked Write)
WL + BL/2 + tWR + 1
tCK
1,7
Precharge All
WL + BL/2 + tWR + 1
tCK
1,7
Precharge
(to same bank as Write w/ AP)
WL + BL/2 + nWR + 1
tCK
1,11
Precharge All
WL + BL/2 + nWR + 1
tCK
1,11
Activate
(to same bank as Write w/ AP)
WL + BL/2 + nWR + 1 + tRPpb
tCK
1,8,11
Write or Write w/ AP
(same bank)
Illegal
-
Write or Write w/ AP
(different bank)
BL/2
tCK
3
Masked-Write or Masked-Write w/ AP
(different bank)
BL/2
tCK
3
Read or Read w/ AP (same bank)
Illegal
-
Read or Read w/ AP (different bank)
WL + BL/2 + tWTR + 1
tCK
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H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
From
Command
Masked Write
w/ AP
Precharge
Precharge All
To Command
Minimum Delay between
Unit Notes
“From Command” and “To Command”
Precharge
(to same bank as Masked Write w/ AP)
WL + BL/2 + nWR + 1
tCK
1,11
Precharge all
WL + BL/2 + nWR + 1
tCK
1,11
Activate
(to same bank as Masked Write w/ AP)
WL + BL/2 + nWR + 1 + tRPpb
tCK
1,8,11
Write or Write w/ AP
(same bank)
Illegal
-
Masked Write or Masked Write w/ AP
(same bank)
Illegal
-
Write or Write w/ AP
(different bank)
BL/2
tCK
3
Masked Write or Masked Write w/ AP
(differenet bank)
BL/2
tCK
3
Read or Read w/ AP (same bank)
Illegal
-
Read or Read w/ AP (different bank)
WL + BL/2 + tWTR + 1
tCK
3,9
Precharge
(to same bank as Precharge)
4
tCK
1
1
Precharge All
4
tCK
Precharge
4
tCK
1
Precharge All
4
tCK
1
Notes
1. For a given bank, the precharge period should be counted from the latest precharge command, whether per-bank or all-bank,
issued to that bank. The precharge period is satisfied tRP after that latest precharge command.
2. Any command issued during the minimum delay time as specified in the table above is illegal.
3. After READ w/AP, seamless read operations to different banks are supported. After WRITE w/AP or Masked Write w/AP, seamless
write operations to different banks are supported. READ, WRITE, and Masked Write operations may not be truncated or interrupted.
4. tRPST values depend on MR1 OP[7] repectively
5. tWPRE values depend on MR1 OP[2] respectively
6. Minimum Delay between "From Command" and "To Command" in clock cycle is calculated by dividing tRTP(in ns) by tCK(in ns)
and rounding up to the next integer: Minimum Delay[cycles] = Roundup(tRTP[ns] / tCK[ns])
7. Minimum Delay between "From Command" and "To Command" in clock cycle is calculated by dividing tWR(in ns) by tCK(in ns)
and rounding up to the next integer: Minimum Delay[cycles] = Roundup(tWR[ns] / tCK[ns])
8. Minimum Delay between "From Command" and "To Command" in clock cycle is calculated by dividing tRPpb(in ns) by tCK(in ns)
and rounding up to the next integer: Minimum Delay[cycles] = Roundup(tRPpb[ns] / tCK[ns])
9. Minimum Delay between "From Command" and "To Command" in clock cycle is calculated by dividing tWTR(in ns) by tCK(in ns)
and rounding up to the next integer: Minimum Delay[cycles] = Roundup(tWTR[ns] / tCK[ns])
10. For Read w/AP the value is nRTP which is defined in Mode Register 2.
11. For Write w/AP the value is nWR which is defined in Mode Register 1.
From
Command
Read w/ AP
(BL16)
Read w/ AP
(BL32)
Table - Timing Between Commands (Precharge and Auto-Precharge) - DQ ODT is Enabled
Minimum Delay between
To Command
“From Command” and “To Command”
Unit Notes
Write or Write w/ AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+BL/2+RD(tRPST)-ODTLon-RD(tODTon,min/tCK)+1
tCK
2,3
Masked Write or Masked Write w/ AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+BL/2+RD(tRPST)-ODTLon-RD(tODTon,min/tCK)+1
tCK
2,3
Write or Write w/ AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+BL/2+RD(tRPST)-ODTLon-RD(tODTon,min/tCK)+1
tCK
2,3
Masked Write or Masked Write w/ AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+BL/2+RD(tRPST)-ODTLon-RD(tODTon,min/tCK)+1
tCK
2,3
Notes
1. The rest of Precharge and Auto-Precharge timings are as same as DQ ODT disabled case.
2. After READ w/AP, seamless read operations to different banks are supported. READ, WRITE, and Masked Write operations may
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LPDDR4 8Gb (x16, 2 Channel, 1 CS)
not be truncated or interrupted.
3. tRPST values depend on MR1 OP[7] respectively.
4.14. Refresh command
The REFRESH command is initiated with CS HIGH, CA0 LOW, CA1 LOW, CA2 LOW, CA3 HIGH and CA4 LOW at the first
rising edge of the clock. Per-bank REFRESH is initiated with CA5 LOW at the first rising edge of the clock. All-bank REFRESH is initiated with CA5 HIGH at the first rising edge of the clock.
A per-bank REFRESH command (REFpb) is performed to the bank address as transferred on CA0, CA1 and CA2 at the
second rising edge of the clock. Bank address BA0 is transferred on CA0, bank address BA1 is transferred on CA1 and
bank address BA2 is transferred on CA2. A per-bank REFRESH command (REFpb) to the eight banks can be issued in
any order. e.g. REFpb commands are issued in the following order: 1-3-0-2-4-7-5-6. After the eight banks have been
refreshed using the per-bank REFRESH command the controller can send another set of per-bank REFRESH commands
in the same order or a different order. e.g. REFpb commands are issued in the following order that is different from the
previous order: 7-1-3-5-0-4-2-6. One of the possible order can also be a sequential round robin: 0-1-2-3-4-5-6-7. It is
illegal to send a per-bank REFRESH command to the same bank unless all eight banks have been refreshed using the
per-bank REFRESH command. The count of eight REFpb commands starts with the first REFpb command after a synchronization event.
The bank count is synchronized between the controller and the SDRAM by resetting the bank count to zero. Synchronization can occur upon issuing a RESET command or at every exit from self refresh. REFab command also synchronizes
the counter between the controller and SDRAM to zero. The SDRAM device can be placed in self-refresh or a REFab
command can be issued at any time without cycling through all eight banks using per-bank REFRESH command. After
the bank count is synchronized to zero the controller can issue per-bank REFRESH commands in any order as described
in the previous paragraph.
A REFab command issued when the bank counter is not zero will reset the bank counter to zero and the DRAM will
perform refreshes to all banks as indicated by the row counter. If another refresh command (REFab or REFpb) is issued
after the REFab command then it uses an incremented value of the row counter.
The table below shows examples of both bank and refresh counter increment behavior.
Table - Bank and Refresh counter increment behavior
#
Sub
#
BA2
Refresh
Bank#
Bank
Counter #
Ref Counter #
(Row Address #)
0
0
1
To 0
-
0
0
0
0 to 1
0
0
1
1
1 to 2
0
1
0
2
2 to 3
REFpb
0
1
1
3
3 to 4
REFpb
1
0
0
4
4 to 5
6
REFpb
1
0
1
5
5 to 6
7
REFpb
1
1
0
6
6 to 7
8
REFpb
1
1
1
7
7 to 0
Command
BA0
1
REFpb
0
2
2
REFpb
3
3
REFpb
4
4
5
5
6
7
8
BA1
Reset, SRX or REFab
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#
Sub
#
Command
BA0
BA1
BA2
Refresh
Bank#
Bank
Counter #
9
1
REFpb
1
1
0
6
0 to 1
10
2
REFpb
1
1
1
7
1 to 2
Ref Counter #
(Row Address #)
n+1
15
7
REFpb
0
0
0
0
6 to 7
16
8
REFpb
1
0
0
4
7 to 0
17
1
REFpb
0
0
0
0
0 to 1
18
2
REFpb
0
0
1
1
1 to 2
19
3
REFpb
0
1
0
2
2 to 3
24
0
REFab
V
V
V
0~7
To 0
25
1
REFpb
1
1
0
6
0 to 1
26
2
REFpb
1
1
1
7
1 to 2
n+2
n+2
n+3
Snip
A bank must be idle before it can be refreshed. The controller must track the bank being refreshed by the per-bank
REFRESH command.
The REFpb command must not be issued to the device until the following conditions are met:
- tRFCab has been satisfied after the prior REFab command
- tRFCpb has been satisfied after the prior REFpb command
- tRP has been satisfied after the prior PRECHARGE command to that bank
- tRRD has been satisfied after the prior ACTIVATE command (if applicable, for example after activating a row in a different bank than the one affected by the REFpb command).
The target bank is inaccessible during per-bank REFRESH cycle time (tRFCpb), however, other banks within the device
are accessible and can be addressed during the cycle. During the REFpb operation, any of the banks other than the one
being refreshed can be maintained in an active state or accessed by a READ or a WRITE command. When the per-bank
REFRESH cycle has completed, the affected bank will be in the idle state.
After issuing REFpb, these conditions must be met:
- tRFCpb must be satisfied before issuing a REFab command
- tRFCpb must be satisfied before issuing an ACTIVATE command to the same bank
- tRRD must be satisfied before issuing an ACTIVATE command to a different bank
- tRFCpb must be satisfied before issuing another REFpb command.
An all-bank REFRESH command (REFab) issues a REFRESH command to all banks. All banks must be idle when REFab
is issued (for instance, by issuing a PRECHARGE-all command prior to issuing an all-bank REFRESH command). REFab
also synchronizes the bank count between the controller and the SDRAM to zero. The REFab command must not be
issued to the device until the following conditions have been met:
- tRFCab has been satisfied following the prior REFab command
- tRFCpb has been satisfied following the prior REFpb command
- tRP has been satisfied following the prior PRECHARGE commands.
When an all-bank refresh cycle has completed, all banks will be idle. After issuing REFab:
- tRFCab latency must be satisfied before issuing an ACTIVATE command
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- tRFCab latency must be satisfied before issuing a REFab or REFpb command.
Symbol
tRFCab
tRFCpb
tRRD
Table - REFRESH Command Scheduling Seperation requirements
minimum delay from
to
REFab
REFab
Activate command to any bank
REFpb
REFab
REFpb
Activate command to same bank as REFpb
REFpb
REFpb
Activate command to different bank than REFpb
REFpb
Activate
Activate command to different bank than prior Activate command
Notes
1
Note:
1. A bank must be in the idle state before it is refreshed, so following an ACTIVATE command REFab is prohibited; REFpb is supported only if it affects a bank that is in the idle state.
Figure - All-Bank REFRESH Operation
CK_t
CK_c
CS
CA0-5
CMD
AB
Precharge
VALID
VALID
VALID
VALID
VALID
VALID
AB
VALID
Refresh
AB
VALID
VALID
>=tRPab
VALID
Refresh
VALID
VALID
VALID
>=tRFCab
ANY
VALID
VALID
>=tRFCab
Figure - Per-Bank REFRESH Operation
CK_t
CK_c
CS
CA0-5
CMD
AB
Precharge
VALID
VALID
VALID
VALID
VALID
VALID
PB
BAx
Refresh
>=tRPab
VALID
VALID
PB
VALID
BAy
Refresh
>=tRFCpb
Refresh to Bank x
Refresh to Bank y
VALID
VALID
Bank 1
Row A
VALID
Row A
Actiavte-1
Row A
Row A
Actiavte-2
>=tRFCpb
Activate command to Bank1
1. Operations to banks other than the bank being refreshed are supported during the tRFCpb period.
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In general, a Refresh command needs to be issued to the LPDDR4 SDRAM regularly every tREFI interval. To allow for
improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of 8 Refresh commands can be postponed during operation of the LPDDR4 SDRAM, meaning that
at no point in time more than a total of 8 Refresh commands are allowed to be postponed and maximum number of
pulled-in or postponed REF command is dependent on refresh rate. It is described in the table below. In case that 8
Refresh commands are postponed in a row, the resulting maximum interval between the surrounding Refresh commands is limited to 9 × tREFI. A maximum of 8 additional Refresh commands can be issued in advance (“pulled in”),
with each one reducing the number of regular Refresh commands required later by one. Note that pulling in more than
8 Refresh commands in advance does not further reduce the number of regular Refresh commands required later, so
that the resulting maximum interval between two surrounding Refresh commands is limited to 9 × tREFI. At any given
time, a maximum of 16 REF commands can be issued within 2 x tREFI.
Self-Refresh Mode may be entered with a maximum of eight Refresh commands being postponed. After exiting SelfRefresh Mode with one or more Refresh commands postponed, additional Refresh commands may be postponed to the
extent that the total number of postponed Refresh commands (before and after the Self-Refresh) will never exceed
eight. During Self-Refresh Mode, the number of postponed or pulled-in REFcommands does not change.
Table - Legacy Refresh Command Timing Constraints
MR4
Refresh rate
OP[2:0]
Max. No. of pulled in or
postponed REFab
Max. interval between
two REFab
Max. No. of REFab within
max(2*tREFI*Refresh
rate multiplier, 16*tRFC)
Per-bank
Refresh
000B
Low Temp.
Limit
N/A
N/A
N/A
N/A
001B
4 x tREFI
8
9 x 4 x tREFI
16
1/8 of REFab
010B
2 x tREFI
8
9 x 2 x tREFI
16
1/8 of REFab
011B
1 x tREFI
8
9 x tREFI
16
1/8 of REFab
100B
0.5 x tREFI
8
9 x 0.5 x tREFI
16
1/8 of REFab
101B
0.25 x tREFI
8
9 x 0.25 x tREFI
16
1/8 of REFab
110B
0.25 x tREFI
8
9 x 0.25 x tREFI
16
1/8 of REFab
111B
High Temp.
Limit
N/A
N/A
N/A
N/A
Table - Modified Refresh Command Timing Constraints
MR4
Refresh rate
OP[2:0]
Max. No. of pulled in or
postponed REFab
Max. interval between
two REFab
Max. No. of REFab within
max(2*tREFI*Refresh
rate multiplier, 16*tRFC)
Per-bank
Refresh
000B
Low Temp.
Limit
N/A
N/A
N/A
N/A
001B
4 x tREFI
2
3 x 4 x tREFI
4
1/8 of REFab
010B
2 x tREFI
4
5 x 2 x tREFI
8
1/8 of REFab
011B
1 x tREFI
8
9 x tREFI
16
1/8 of REFab
100B
0.5 x tREFI
8
9 x 0.5 x tREFI
16
1/8 of REFab
101B
0.25 x tREFI
8
9 x 0.25 x tREFI
16
1/8 of REFab
110B
0.25 x tREFI
8
9 x 0.25 x tREFI
16
1/8 of REFab
111B
High Temp.
Limit
N/A
N/A
N/A
N/A
Notes:
1. For any thermal transition phase where Refresh mode is transitioned to either 2x tREFIor 4x tREFI, DRAM will support the previous
postponed refresh requirement provided the number of postponed refreshes is monotonically reduced to meet the new requirement. However, the pulled-in refresh commands in previous thermal phase are not applied in new thermal phase. Entering new
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thermal phase the controller must count the number of pulled-in refresh commands as zero, regardless of remaining pulled-in
refresh commands in previous thermal phase.
2. LPDDR4 devices are refreshed properly if memory controller issues refresh commands with same or shorter refresh period than
reported by MR4 OP[2:0]. If shorter refresh period is applied, the corresponding requirements from Table apply. For example,
when MR4 OP[2:0]=001B, controller can be in any refresh rate from 4xtREFI to 0.25x tREFI. When MR4 OP[2:0]=010B, the only
prohibited refresh rate is 4x tREFI.
Figure - Postponing Refresh Commands (Example)
tREFI
9 x tREFI
t
tRFC
8 REF-Commands postponed
Figure - Pulling-in Refresh Commands (Example)
tREFI
9 x tREFI
t
tRFC
8 REF-Commands postponed
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4.15. LPDDR4 Refresh Requirements by Device Density
Between SRX command and SRE command, at least one extra refresh command is required. After the DRAM Self Refresh Exit command, in addition to the normal Refresh command at tREFI interval, the LPDDR4 DRAM requires minimum
of one extra Refresh command prior to Self Refresh Entry command.
Table - Refresh Requirement Parameters per die
Density
Symbol
4Gb
6Gb
8Gb
Density per channel
2Gb
3Gb
4Gb
Number of Banks
8
Refresh Window
tREFW
32
1 x tREFI
Refresh Window
tREFW
16
0.5 x tREFI
Refresh Window
tREFW
8
0.25 x tREFI
Required number of REFRESH comR
8,192
mands
tREFI
3.904
Average Refresh Interval REFab
1 x tREFI
REFpb
tREFIpb
488
REFab
tREFI
1.952
Average Refresh Interval
0.5 x tREFI
REFpb
tREFIpb
244
tREFI
0.976
Average Refresh Interval REFab
0.25 x tREFI
REFpb
tREFIpb
122
Refresh Cycle Time (All Banks)
tRFCab
130
180
180
Refresh Cycle Time (per Bank)
tRFCpb
60
90
90
12Gb
6Gb
16Gb
8Gb
Unit
ms
ms
ms
us
ns
us
ns
us
ns
ns
ns
280
140
Notes:
1. Refresh for each channel is independent of the other channel on the die, or other channels in a package. Power delivery in the
user’s system should be verified to make sure the DC operating conditions are maintained when multiple channels are refreshed
simultaneously.
2. Self refresh abort feature is available for higher density devices starting with12 Gb device and tXSR_abort(min) is defined as tRFCpb
+ 17.5ns.
4.16. Self Refresh Operation
4.16.1. Self Refresh Entry and Exit
The Self Refresh command can be used to retain data in the LPDDR4 SDRAM, the SDRAM retains data without external
Refresh command. The device has a built-in timer to accommodate Self Refresh operation. The Self Refresh is entered
by Self Refresh Entry Command defined by having CKE High, CS High, CA0 Low, CA1 Low, CA2 Low; CA3 High; CA4
High, CA5 Valid (Valid that means it is Logic Level, High or Low) for the first rising edge and CKE High, CS Low, CA0
Valid, CA1 Valid, CA2 Valid, CA3 Valid, CA4 Valid, CA5 Valid at the second rising edge of the clock. Self Refresh command
is only allowed when SDRAM is idle state.
During Self Refresh mode, external clock input is needed and all input pin of SDRAM are activated.
SDRAM can accept the following commands, MRR-1, CAS-2, SRX, MPC, MRW-1, and MRW-2 except PASR Bank/Segment setting.
LPDDR4 SDRAM can operate in Self Refresh in both the standard or elevated temperature ranges. SDRAM will also manage Self Refresh power consumption when the operating temperature changes, lower at low temperature and higher
at high temperatures.
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For proper Self Refresh operation, power supply pins (VDD1 and VDD2) must be at valid levels. VDDQ may be turned
off during Self-Refresh after tESCKE is satisfied (Refer to Figure-Self Refresh Entry/Exit Timing with Power Down Entry/
Exit for tESCKE).
Prior to exiting Self-Refresh VDDQ must be within specified limits. The minimum time that the SDRAM must remain in
Self Refresh model is tSR,min.
The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when Self
Refresh Exit is registered. Upon exit from Self Refresh, it is required that at least one REFRESH command (8 per-bank
or 1 all-bank) is issued before entry into a subsequent Self Refresh.
Figure - Self Refresh Entry/Exit Timing
CK_c
CK_t
CKE
CS
CA
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
tSR
CMD
Self Refresh
Entry
Valid
Valid
Valid
Valid
Valid
Valid
tXSV
Valid
Self Refresh
Exit
Deselect
Time Break
Valid
Valid
Don’t Care
1. MRR-1, CAS-2, SRX, MPC, MRW-1 and MRW-2 except PASR Bank/Segment setting is allowed during Self Refresh.
2. Address input may be don’t care when input command is Deselect.
4.16.2. Power Down Entry and Exit during Self Refresh
Entering/Exiting Power Down Mode is allowed during Self Refresh mode in LPDDR4 SDRAM. The related timing parameters between Self Refresh Entry/Exit and Power Down Entry/Exit are shown in Figure-Self Refresh Entry/Exit Timing
with Power Down Entry/Exit.
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Figure - Self Refresh Entry/Exit Timing with Power Down Entry/Exit
T0
T1
T2
T3
Ta0
Tb0 Tb1
Tc0
Td1
Te0
Tf0
Tf1
Tg0
Tg1
Th0 Tk0
Tk1
Tk2
Tk3
CK_c
*2
CK_t
tCKE
tCKELCK
tCKCKEH
CKE
tCSCKEH tCKEHCS
tCSCKE tCKELCS
CS
tESCKE
tCMDCKE
CA
tXP
Valid Valid Valid Valid
Valid Valid
tSR
COMMAND
*3
Self Refresh Any Command DES
Entry
DES
DES
Enter Self Refresh
NOTES:
1. MRR-1, CAS-2, DES, SRX, MPC, MRW-1 and MRW-2 except PASR Bank/Segment setting is allowed during Self Refresh.
2. Input clock frequency can be changed or the input clock can be stopped or floated after tCKELCK saticefied and
during power-down, provided that upon exiting power-down, the clock is stable and within specified limits for a minimum
of tCKCKEH of stable clock prior to power-down exit and the clock frequency is between the minimum and maximum
specified frequency for the speed grade in use.
3. 2 Clock command for example.
Rev 1.1 / Sep 2016 / SK hynix Confidential
Self Refresh
Exit
DES
Exit Self Refresh
DON'T CARE
TIME BREAK
90
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LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.16.3. Command Input Timing after Power Down Exit
Command input timings after Power Down Exit during Self Refresh mode are shown in Figure-Command input timings
after Power Dwon Exit during Self Refresh.
Figure - Command input timings after Power Down Exit during Self Refresh
T0
T1
T2
T3
Ta0
Tb0 Tb1
Tc0
Td1
Te0
Tf0
Tf1
Tg0
Tg1
Th0 Tk0
Tk1
Tk2
Tk3
CK_c
*2
CK_t
tCKE
tCKELCK
tCKCKEH
CKE
tCSCKEH tCKEHCS
tCSCKE tCKELCS
CS
tESCKE
tCMDCKE
CA
tXP
Valid Valid Valid Valid
Valid Valid
tSR
*3
*3
COMMAND
Self Refresh Any Command DES
Entry
DES
DES Any Command DES
Enter Self Refresh
NOTES:
1. MRR-1, CAS-2, DES, SRX, MPC, MRW-1 and MRW-2 except PASR Bank/Segment setting is allowed during Self Refresh.
2. Input clock frequency can be changed or the input clock can be stopped or floated after tCKELCK saticefied and
during power-down, provided that upon exiting power-down, the clock is stable and within specified limits for a minimum
of tCKCKEH of stable clock prior to power-down exit and the clock frequency is between the minimum and maximum
specified frequency for the speed grade in use.
3. 2 Clock command for example.
Exit Self Refresh
DON'T CARE
TIME BREAK
4.16.4. Self Refresh Abort
If MR4 OP[3] is enabled then DRAM aborts any ongoing refresh during Self Refresh exit and does not increment the
internal refresh counter. Controller can issue a valid command after a delay of tXSR_abort instead of tXSR.
The value of tXSR_abort(min) is defined as tRFCpb + 17.5 ns.
Upon exit from Self Refresh mode, the LPDDR4 SDRAM requires a minimum of one extra refresh (8 per bank or 1 all
bank) before entry into a subsequent Self Refresh mode. This requirement remains the same irrespective of the setting
of the MR bit for self refresh abort.
Self refresh abort feature is available for higher density devices starting with12 Gb device.
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4.17. MRR, MRW, MPC Command during tXSR, tRFC
Mode Register Read (MRR), Mode Register Write (MRW) and Multi Purpose Command (MPC) can be issued during tXSR
period.
T0
T1
T2
T3
T4
T5
T6
T7
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
CK_c
CK_t
CKE
CS “H” for CAS-2
CS
CA
COMMAND
(Case-1)
Valid Valid Valid Valid
Valid Valid Valid Valid
DES
SRX
MPC
(2 clock command) DES
SRX
MPC
(4 clock command)
DES
DES
DES
MRW-1
MRW-2
Valid Valid
DES
DES
DES
DES
Any Command*2
DES
Any Command*2
tMRD
COMMAND
(Case-2)
DES
CAS-2
DES
DES
MRW-1
MRW-2
DES
DES
DES
tMRD
tXSR
NOTES : 1. MPC and MRW command are shown in figure at this time, Any combination of MRR, MRW and MPC is allowed during tXSR period.
2. Any command also includes MRR, MRW and all MPC command.
TIME BREAK
DON'T CARE
Figure - MRR, MRW and MPC Commands Issuing Timing during tXSR
Mode Register Read (MRR), Mode Register Write (MRW) and Multi Purpose Command (MPC) can be issued during tRFC
period.
T0
T1
T2
T3
T4
T5
T6
T7
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
CK_c
CK_t
CKE
CS “H” for CAS-2
CS
CA
Valid Valid Valid Valid
Valid Valid Valid Valid
Valid Valid
tMRD
COMMAND
(Case-1)
MPC
DES REF All Bank (2 clock command) DES
DES
DES
DES
MRW-1
MRW-2
DES
DES
DES
DES
Any Command*3
DES
Any Command*3
tMRD
COMMAND
(Case-2)
MPC
DES REF All Bank (4 clock command)
CAS-2
DES
DES
MRW-1
MRW-2
DES
DES
DES
tRFCab*2
NOTES : 1. MPC and MRW command are shown in figure at this time, Any combination of MRR, MRW and MPC is allowed during tRFCab or tRFCpb period.
2. Refresh cycle time depends on Refresh command. In case of REF per Bank command issued, Refresh cycle time will be tRFCpb.
3. Any command also includes MRR, MRW and all MPC command.
DON'T CARE
TIME BREAK
Figure - MRR, MRW and MPC Commands Issuing Timing during tRFC
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4.18. Mode Register Read (MRR) command
The Mode Register Read (MRR) command is used to read configuration and status data from the LPDDR4-SDRAM registers.The MRR command is initiated with CKE, CS and CA[5:0] in the proper state as defined by the Command Truth
Table. The mode register address operands (MA[5:0]) allow the user to select one of 64 registers. The mode register
contents are available on the first 4UI’s data bits of DQ[7:0] after RL x tCK + tDQSCK + tDQSQ following the MRR
command. Subsequent data bits contain valid but undefined content. DQS is toggled for the duration of the Mode Register READ burst. The MRR has a command burst length 16. MRR operation must not be interrupted.
BL
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DMI
0
1
2
3
4
5
6
7
8
9
10
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
11
12
13
14
15
V
V
V
V
V
V
V
V
V
Notes:
1. MRR data are extended to first 4 UI’s for DRAM controller to sample data easily.
2. DBI may apply or may not apply during normal MRR. It’s vendor specific. If read DBI is enable with MRS and vendor cannot support
the DBI during MRR, DBI pin status should be low.
3. The read pre-amble and post-amble of MRR are same as normal read.
Figure - Mode Register Read Operation
CK_t
CK_c
tMRR
CA[5:0]
MRR
Valid
CAS2
CAS2
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
RL
CMD
Mode Register
Read
CAS-2
DE-SELECT
DE-SELECT
Valid
Valid
Valid
Valid
tDQSCK
DQS_t
DQS_c
tRPRE
DQ[7:0]
/DMI[0]
DQ[15:8]
/DMI[1]
tRPSTE
Dout
A
Dout
A
Dout
A
Dout
A
Undef
Undef
Undef
Undef
Undef
Undef
Undef
Undef
Undef
Undef
Undef
Undef
Undef
Undef
Undef
Undef
1. Only BL=16 is supported.
2. Only De-Select is allowed during tMRR period.
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4.18.1. MRR after Read and Write command
After a prior READ command, the MRR command must not be issued earlier than BL/2 clock cycles, in a similar way WL
+ BL/2 + 1 + RU(tWTR/tCK) clock cycles after a prior Write, Write with AP, Mask Write, Mask Write with AP and MPC
Write FIFO command in order to avoid the collision of Read and Write burst data on SDRAM’s internal Data bus.
T0
T1
T2
T3
BL
BA0,
CA, AP
CAn
CAn
T4
T15
T16
T17
T18
T19
Valid
MA
CAn
CAn
T20
T21
T33
T34
T35
T36
T37
T43
DES
DES
DES
DES
DES
DES
DES
DES
T44
CK_c
CK_t
CS
CA
COMMAND
Read-1
CAS-2
DES
DES
MRR-1
CAS-2
BL/2
RL = 14
RL = 14
tDQSCK
DES
BL/2 = 8
tDQSCK
BL/2 = 16
tRPRE
DQS_c
DQS_t
tDQSQ
tDQSQ
tRPST
DQ7:0
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n26 n27 n28 n29 n30 n31
DQ15:8
DMI1:0
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Valid Valid Valid Valid Valid Valid
n0 n1 n2 n3 n26 n27 n28 n29 n30 n31
DON'T CARE
OP Code Out
Valid Valid
TIME BREAK
Note
1. The minimum number of clock cycles from the burst READ command to the MRR command is BL/2.
2. Read BL = 32, MRR BL = 16, RL = 14, Preamble = Toggle, Postamble = 0.5nCK, DBI = Disable, DQ/DQS: VSSQ termination
3. DES commands except tMRR period are shown for ease of illustration; other commands may be valid at these times.
Figure - Read to MRR Timing
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T0
T1
T2
T3
BL
BA0,
CA, AP
CA
CA
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Tc3
Tc4
Valid
MA
CAn
CAn
Tc5
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
DES
DES
WL
DES
DES
DES
DES
BL/2 + 1 Clock
tWPRE
DES
DES
MRR-1
tWTR
CAS-2
DES
tMRR
tWPST
DQS_c
DQS_t
tDQS2DQ
Din Din Din Din Din Din
n0 n1 n12 n13 n14 n15
DQ
DON'T CARE
TIME BREAK
Note
1. Write BL=16, Write Postamble = 0.5nCK, DQ/DQS: VSSQ termination.
2. Only DES is allowed during tMRR period.
2. Din n = data-in to columnm.n.
3. The minimum number of clock cycles from the burst write command to MRR command is WL + BL/2 + 1 + RU(tWTR/tCK).
4. tWTR starts at the rising edge of CK after the last latching edge of DQS.
5. DES commands except tMRR period are shown for ease of illustration; other commands may be valid at these times.
Figure - Write to MRR Timing
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4.18.2. MRR after Power-Down Exit
Following the power-down state, an additional time, tMRRI, is required prior to issuing the mode register
read (MRR) command. This additional time (equivalent to tRCD) is required in order to be able to maximize
power-down current savings by allowing more power-up time for the MRR data path after exit from powerdown mode.
T0
Ta0
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Td0
Td1
Td2
Td3
Td4
Td5 Td6
Td7
Td8
Td9
CK_c
CK_t
tCKCKEH
CKE
tXP
tMRRI
tMRR
CS
CA
COMMAND
Valid Valid Valid Valid
DES
DES
Any Command
Any Command
Valid
DES
DES
DES
DES
MA
MRR-1
CAn
CAn
CAS-2
DES
DON'T CARE
Note
1. Only DES is allowed during tMRR period.
2. DES commands except tMRR period are shown for ease of illustration; other commands may be valid at these times.
DES
DES
TIME BREAK
Figure - MRR Following Power-Down
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4.19. Mode Register Write (MRW) command
The Mode Register Write (MRW) command is used to write configuration data to the mode registers. The MRW command is initiated by setting CKE, CS, and CA[5:0] to valid levels at a rising edge of the clock (see Command Truth Table).
The mode register address and the data written to the mode registers is contained in CA[5:0] according to the Command Truth Table. The MRW command period is defined by tMRW. Mode register Writes to read-only registers have no
impact on the functionality of the device.
Figure - Mode Register Write Timing
CK_t
CK_c
CS
CA0-5
MRW
MRW
MRW
MRW
Valid
Valid
Valid
Valid
MRW
MRW
MRW
MRW
MRW-1
MRW-2
Deselect
Valid
Valid
Valid
tMRD
tMRW
CMD
Valid
Deselect
MRW-1
MRW-2
Deselect
Valid
1. Only De-select command is allowed during tMRW and tMRD periods
4.19.1. Mode Register Write
MRW can be issued from either a Bank-Idle or Bank-Active state. Certain restrictions may apply for MRW from an Active
state.
Table - Truth Table for Mode Register Read (MRR) and Mode Register Write (MRW)
Current State
Intermediate State
Next State
Command
SDRAM
SDRAM
SDRAM
Mode Register Reading
MRR
All Banks Idle
(All Banks Idle)
All Banks Idle
Mode Register Writing
MRW
All Banks Idle
(All Banks Idle)
MRR
Mode Register Reading
Bank(s) Active
Bank(s) Active
MRW
Mode Register Writing
Bank(s) Active
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From Command
MRR
RD/RDA
WR/WRA/
MWR/MWRA
MRW
Power Down Exit
MRW
RD/
RD FIFO/
RD DQ CAL
RD with
Auto-Precharge
WR/
MWR/
WR FIFO
WR/MWR with
Auto-Precharge
Table - MRR/MRW Timing Constraints : DQ ODT Disabled
To ComMinimum Delay between “From Command”
mand
and “To Command”
MRR
tMRR
RD/RDA
tMRR
WR/WRA/
RL+RU(tDQSCK(max)/tCK)+BL/2+ 3 -WL
MWR/MWRA
MRW
RL+RU(tDQSCK(max)/tCK)+BL/2+ 3
BL/2
nCK
nCK
nCK
WL+1+BL/2+RU(tWTR/tCK)
nCK
tMRD
tXP+tMRRI
tMRD
-
tMRD
-
tMRW
-
RL+BL/2+RU(tDQSCKmax/tCK) +RD(tRPST) +max(RU(7.5ns/
tCK),8nCK)
nCK
RL+BL/2+RU(tDQSCKmax/tCK) +RD(tRPST) +max(RU(7.5ns/
tCK),8nCK)+nRTP-8
nCK
WL+1+BL/2+max(RU(7.5ns/tCK),8nCK)
nCK
WL+1+BL/2+max(RU(7.5ns/tCK),8nCK)+nWR
nCK
MRR
RD/RDA
WR/WRA/
MWR/MWRA
MRW
MRW
Unit Notes
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From Command
MRR
RD/RDA
WR/WRA/
MWR/MWRA
MRW
Powe Down Exit
Table - MRR/MRW Timing Constraints : DQ ODT Enabled
To ComMinimum Delay between “From Command”
mand
and “To Command”
MRR
Same as ODT Disable Case
RD/RDA
WR/WRA/
RL+RU(tDQSCK(max)/tCK)+BL/2+3
MWR/MWRA
-ODTLon-RD(tODTon(min)/tCK)
MRW
Same as ODT Disable Case
MRR
Unit Notes
nCK
-
Same as ODT Disable Case
-
Same as ODT Disable Case
-
Same as ODT Disable Case
-
RD/RDA
MRW
WR/WRA/
MWR/
MWRA
MRW
RD/
RD FIFO/
RD DQ CAL
RD with
Auto-Precharge
WR/
MWR/
WR FIFO
MRW
WR/MWR with
Auto-Precharge
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4.20. Vref Current Generator (VRCG)
LPDDR4 SDRAM Vref current generators (VRCG) incorporate a high current mode to reduce the settling time of the
internal Vref(DQ) and Vref(CA) levels during training and when changing frequency set points during operation. The
high current mode is enabled by setting MR13[OP3] = 1. Only Deselect commands may be issued until tVRCG_ENABLE
is satisfied. tVRCG_ENABLE timing is shown in figure below.
Figure - VRCG Enable timing
CK_c
CK_t
CKE
CS
CA
MRW-1 MRW-1 MRW-2 MRW-2
CMD
VRCG Enable
Valid
Valid
Deselect
Valid
Valid
Valid
Deselect
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Deselect
Valid
Deselect
tVRCG_Enable
Time Break
VRCG high current mode is disabled by setting MR13[OP3] = 0. Only Deselect commands may be issued until
tVRCG_DISABLE is satisfied. tVRCG_DISABLE timing is shown in figure below.
Figure - VRCG Disable timing
CK_c
CK_t
CKE
CS
CA
MRW-1 MRW-1 MRW-2 MRW-2
CMD
VRCG Disable
Valid
Valid
Deselect
Valid
Valid
Deselect
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Deselect
Valid
Valid
Deselect
tVRCG_Disable
Time Break
Note that LPDDR4 SDRAM devices support Vref(CA) and Vref(DQ) range and value changes without enabling VRCG high
current mode.
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4.21. CA Vref Training
The DRAM internal CA Vref specification parameters are voltage operating range, stepsize, Vref set tolerance, Vref step
time and Vref valid level.
The voltage operating range specifies the minimum required Vref setting range for LPDDR4 DRAM devices. The minimum range is defined by Vrefmax and Vrefmin as depicted in Vref operating range (Vref.min, Vref.max).
Figure - Vref operating range (Vref.min, Vref.max)
VDD2
Vin DC max
Vrefmax
Vref
Range
Vrefmin
Vin DC Low
Vswing Small
System variance
Vswing Large
Total Range
The Vref stepsize is defined as the stepsize between adjacent steps. Vref stepsize ranges from 0.3% VDD2 to
0.5%VDD2. However, for a given design, DRAM has one value for Vref step size that falls within the range.
The Vref set tolerance is the variation in the Vref voltage from the ideal setting. This accounts for accumulated error
over multiple steps. There are two ranges for Vref set tolerance uncertainity. The range of Vref set tolerance uncertainity
is a function of number of steps n.
The Vref set tolerance is measured with respect to the ideal line which is based on the two endpoints. Where the endpoints are at the min and max Vref values for a specified range. An illustration depicting an example of the stepsize and
Vref set tolerance is below.
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Figure - Example of Vref set tolerance (max case only shown) and stepsize
Actual Vref
Output
Vref
Straight Line
(endpoint fit)
Vref
Tolerance
Vref
Stepsize
Digital Code
The Vref increment/decrement step times are define by Vref_time-short, middle and long. The Vref_time-short,
Vref_time-middle and Vref_time-long is defined from TS to TE as shown in the Vref_time for short, middlg and long
timing diagram below where TE is referenced to when the vref voltage is at the final DC level within the Vref valid tolerance (Vref_val_tol).
The Vref valid level is defined by Vref_val tolerance to qualify the step time TE as shown in Vref step single stepsize
increment case. This parameter is used to insure an adequate RC time constant behavior of the voltage level change
after any Vref increment/decrement adjustment. This parameter is only applicable for DRAM component level validation/characerization.
Vref_time-Short is for a single stepsize increment/decrement change in Vref voltage.
Vref_time-Middle is at least 2 stepsizes increment/decrement change within the same VrefCA range in Vref voltage.
Vref_time-Long is the time including up to Vrefmin to Vrefmax or Vrefmax to Vrefmin change across the VrefCA Range
in Vref voltage.
TS - is referenced to MRS command clock
TE - is referenced to the Vref_val_tol
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Figure - Vref_time for short, middlg and long timing diagram
CK_c
CK_t
CKE
CS
CA
MRW-1 MRW-1 MRW-2 MRW-2
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CMD
VREF(CA) Value/Range
Setting
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Vref_time-Short/Middle/Long
Old Vref Setting
Updating Vref(CA) Setting
New Vref Setting
TS
TE
Vref Setting
Adjustment
Time Break
The MRW command to the mode register bits are as follows.
MR12 OP[5:0] : VREF(CA) Setting
MR12 OP[6] : VREF(CA) Range
The minimum time required between two Vref MRS commands is Vref_time-short for single step and Vref_time-Middle
for a full voltage range step.
Figure - Vref step single stepsize increment case
Vref
Voltage
Vref DC
(VDD2 DC)
Stepsize
Vref_val_tol
t1
Time
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Figure - Vref step single stepsize decrement case
Vref
Voltage
t1
Stepsize
Vref_val_tol
Vref DC
(VDD2 DC)
Time
Figure - Vref full step from Vrefmin to Vrefmax case
Vref
Voltage
Vref DC
(VDD2 DC)
Vrefmax
Full
Range
Step
Vref_val_tol
t1
Vrefmin
Time
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Figure - Vref full step from Vrefmax to Vrefmin case
Vrefmin
t1
Vref
Voltage
Full
Range
Step
Vref_val_tol
Vref DC
(VDD2 DC)
Vrefmax
Time
The table below contains the CA internal vref specifications that will be characterized at the component level for compliance. The component level characterization method is tbd.
Parameter
Vref Max
operating point Range[0]
Vref Min
operating point
Range[0]
Vref Max
operating point Range[1]
Vref Min
operating point
Range[1]
Vref Stepsize
Vref Set
Tolerance
Vref Step Time
Vref Valid tolerance
Table - CA Internal Vref Specifications
Symbol
Min.
Typ.
Max.
Unit
Notes
Vref_max_R0
30%
-
-
VDD2
1,11
Vref_min_R0
-
-
10%
VDD2
1,11
Vref_max_R1
42%
-
-
VDD2
1,11
Vref_min_R1
-
-
22%
VDD2
1,11
Vref_step
0.30%
-1.000%
-0.10
-
0.40%
0.000%
0.00%
-
-0.10%
0.00%
0.50%
1.000%
0.10%
100
200
250
1
0.10%
VDD2
VDD2
VDD2
ns
ns
ns
ms
VDD2
2
3,4,6
3,5,7
8
12
9
13,14
10
Vref_set_tol
Vref_time-short
Vref_time-middle
Vref_time-Long
Vref_time-weak
Vref_val_tol
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Notes:
1. Vref DC voltage referenced to VDDQ_DC.
2. Vref stepsize increment/decrement range. Vref at DC level.
3. Vref_new = Vref_old + n*Vref_step; n= number of steps; if increment use "+"; If decrement use "-".
4. The minimum value of Vref setting tolerance = Vref_new - 1.0%*VDDQ. The maximum value of Vref setting tolerance = Vref_new
+ 1.0%*VDDQ. For n>4
5. The minimum value of Vref setting tolerance = Vref_new - 0.10%*VDDQ. The maximum value of Vref setting tolerance = Vref_new
+ 0.10%*VDDQ. For n≤4.
6. Measured by recording the min and max values of the Vref output over the range, drawing a straight line between those points
and comparing all other Vref output settings to that line.
7. Measured by recording the min and max values of the Vref output across 4 consectuive steps(n=4), drawing a straight line between
those points and comparing all other Vref output settings to that line.
8. Time from MRS command to increment or decrement one step size for Vref.
9. Time from MRS command to increment or decrement Vrefmin to Vrefmax or Vrefmax to Vrefmin change across the VrefCA Range
in Vref voltage.
10. Only applicable for DRAM component level test/characterization purpose. Not applicable for normal mode of operation. Vref valid
is to qualify the step times which will be characterized at the component level.
11. DRAM range 0 or 1 set by MR12 OP[6].
12. Time from MRS command to increment or decrement more than one step size up a full range of Vref voltage within the same
VrefCA range.
13. Applies when VRCG high current mode is not enabled, specified by MR13 OP[3] = 0.
14. Vref_time_weak covers all Vref(CA) Range and Value change conditions are applied to Vref_time_Short/Middle/Long.
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4.22. DQ Vref Training
The DRAM internal DQ Vref specification parameters are voltage operating range, stepsize, Vref set tolerance, Vref step
time and Vref valid level.
The voltage operating range specifies the minimum required Vref setting range for LPDDR4 DRAM devices. The minimum range is defined by Vrefmax and Vrefmin as depicted in Vref operating range (Vref.min, Vref.max).
Figure - Vref operating range (Vref.min, Vref.max)
VDDQ
Vin DC max
Vrefmax
Vref
Range
Vrefmin
Vin DC Low
Vswing Small
System variance
Vswing Large
Total Range
The Vref stepsize is defined as the stepsize between adjacent steps. However, for a given design, DRAM has one value
for Vref step size that falls within the range.
The Vref set tolerance is the variation in the Vref voltage from the ideal setting. This accounts for accumulated error
over multiple steps. There are two ranges for Vref set tolerance uncertainity. The range of Vref set tolerance uncertainity
is a function of number of steps n.
The Vref set tolerance is measured with respect to the ideal line which is based on the two endpoints. Where the endpoints are at the min and max Vref values for a specified range. An illustration depicting an example of the stepsize and
Vref set tolerance is below.
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Figure - Example of Vref set tolerance (max case only shown) and stepsize
Actual Vref
Output
Vref
Straight Line
(endpoint fit)
Vref
Tolerance
Vref
Stepsize
Digital Code
The Vref increment/decrement step times are define by Vref_time-short, middle and long. The Vref_time-short, middle
and Vref_time-long is defined from TS to TE as shown in the Vref_time for short and long timing diagram below where
TE is referenced to when the vref voltage is at the final DC level within the Vref valid tolerance(Vref_val_tol).
The Vref valid level is defined by Vref_val tolerance to qualify the step time TE as shown in Vref step single stepsize
increment case. This parameter is used to insure an adequate RC time constant behavior of the voltage level change
after any Vref increment/decrement adjustment. This parameter is only applicable for DRAM component level validation/characerization.
Vref_time-Short is for a single stepsize increment/decrement change in Vref voltage.
Vref_time-Middle is at least 2 stepsizes increment/decrement change within the same VrefDQ range in Vref voltage.
Vref_time-Long is the time including up to Vrefmin to Vrefmax or Vrefmax to Vrefmin change across the VrefDQ Range
in Vref voltage.
TS - is referenced to MRS command clock
TE - is referenced to the Vref_val_tol
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Figure - Vref_time for short and long timing diagram
CK_c
CK_t
CKE
CS
CA
MRW-1 MRW-1 MRW-2 MRW-2
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CMD
VREF(DQ)
Value/Range Setting
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Vref_time-Short/Middle/Long
Old Vref Setting
Updating Vref(DQ) Setting
New Vref Setting
TS
TE
Vref Setting
Adjustment
Time Break
The MRW command to the mode register bits are as follows.
MR14 OP[5:0] : VREF(DQ) Setting
MR14 OP[6] : VREF(DQ) Range
The minimum time required between two Vref MRS commands is Vref_time-short for single step and Vref_time-Middle
for a full voltage range step
Figure - Vref step single stepsize increment case
Vref
Voltage
Vref DC
(VDDQ DC)
Stepsize
Vref_val_tol
t1
Time
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Figure - Vref step single stepsize decrement case
Vref
Voltage
t1
Stepsize
Vref_val_tol
Vref DC
(VDDQ DC)
Time
Figure - Vref full step from Vrefmin to Vrefmax case
Vref
Voltage
Vref DC
(VDDQ DC)
Vrefmax
Full
Range
Step
Vref_val_tol
t1
Vrefmin
Time
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Figure - Vref full step from Vrefmax to Vrefmin case
Vrefmin
t1
Vref
Voltage
Full
Range
Step
Vref_val_tol
Vref DC
(VDDQ DC)
Vrefmax
Time
The table below contains the DQ internal vref specifications that will be characterized at the component level for compliance. The component level characterization method is tbd.
Parameter
Vref Max operating point Range[0]
Vref Min operating point Range[0]
Vref Max operating point Range[1]
Vref Min operating point Range[1]
Vref Stepsize
Vref Set Tolerance
Vref Step Time
Vref Valid tolerance
Table - DQ Internal Vref Specifications
Symbol
Min.
Typ.
Vref_max_R0
30%
Vref_min_R0
Vref_max_R1
42%
Vref_min_R1
Vref_step
0.30%
0.40%
-1.000%
0.000%
Vref_set_tol
-0.10
0.00%
Vref_time-short
Vref_time-Middle
Vref_time-Long
Vref_time-weak
Vref_val_tol
-0.10%
0.00%
Max.
10%
22%
0.50%
1.000%
0.10%
100
200
250
1
0.10%
Unit
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
ns
ns
ns
ms
VDDQ
Notes
1,11
1,11
1,11
1,11
2
3,4,6
3,5,7
8
12
9
13,14
10
Notes:
1. Vref DC voltage referenced to VDDQ_DC.
2. Vref stepsize increment/decrement range. Vref at DC level.
3. Vref_new = Vref_old + n*Vref_step; n= number of steps; if increment use "+"; If decrement use "-".
4. The minimum value of Vref setting tolerance = Vref_new - 1.0%*VDDQ. The maximum value of Vref setting tolerance = Vref_new
+ 1.0%*VDDQ. For n>4.
5. The minimum value of Vref setting tolerance = Vref_new - 0.10%*VDDQ. The maximum value of Vref setting tolerance = Vref_new
+ 0.10%*VDDQ. For n< 4.
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6. Measured by recording the min and max values of the Vref output over the range, drawing a straight line between those points
and comparing all other Vref output settings to that line.
7. Measured by recording the min and max values of the Vref output across 4 consectuive steps(n=4), drawing a straight line between
those points and comparing all other Vref output settings to that line.
8. Time from MRS command to increment or decrement one step size for Vref.
9. Time from MRS command to increment or decrement Vrefmin to Vrefmax or Vrefmax to Vrefmin change across the VrefDQ Range
in Vref voltage.
10.Only applicable for DRAM component level test/characterization purpose. Not applicable for normal mode of operation. Vref valid
is to qualify the step times which will be characterized at the component level.
11. DRAM range 0 or 1 set by MR14 OP[6].
12. Time from MRS command to increment or decrement more than one step size up to a full range of Vref voltage withiin the same
VrefDQ range.
13. Applies when VRCG high current mode is not enabled, specified by MR13[OP3] = 0.
14. Vref_time_weak covers all Vref(DQ) Range and Value change conditions are applied to Vref_time_Short/Middle/Long.
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4.23. Command Bus Training
The LPDDR4-SDRAM command bus must be trained before enabling termination for high-frequency operation. LPDDR4
provides an internal VREF(ca) that defaults to a level suitable for un-terminated, low-frequency operation, but the
VREF(ca) must be trained to achieve suitable receiver voltage margin for terminated, high-frequency operation. The
training mode described here centers the internal VREF(ca) in the CA data eye and at the same time allows for timing
adjustments of the CS and CA signals to meet setup/hold requirements. Because it can be difficult to capture commands
prior to training the CA inputs, the training mode described here uses a minimum of external commands to enter, train,
and exit the Command Bus Training mode.
Note: it is up to the system designer to determine what constitutes “low-frequency” and “high-frequency” based on the
capabilities of the system. Low-frequency should then be defined as an operating frequency in which the system can
reliably communicate with the SDRAM before Command Bus Training is executed.
The LPDDR4-SDRAM die has a bond-pad (ODT-CA) for multi-rank operation. In a multi-rank system, the terminating
rank should be trained first, followed by the non-terminating rank(s). See the ODT section for more information.
The LPDDR4-SDRAM uses Frequency Set-Points to enable multiple operating settings for the die. The LPDDR4-SDRAM
defaults to FSP-OP[0] at power-up, which has the default settings to operate in un-terminated, low-frequency environments. Prior to training, the mode register settings should be configured by setting MR13 OP[6]=1B (FSP-WR[1]) and
setting all other mode register bits for FSP-OP[1] to the desired settings for high-frequency operation. Prior to entering
Command Bus Training, the SDRAM will be operating from FSP-OP[x]. Upon Command Bus Training entry when CKE is
driven LOW, the LPDDR4-SDRAM will automatically switch to the alternate FSP register set (FSP-OP[y]) and use the
alternate register settings during training (See note 6 in Entering Command Bus Training Mode and CA Training Pattern
Input and Output with VrefCA Value Update for more information on FSP-OP register sets). Upon training exit when
CKE is driven HIGH, the LPDDR4-SDRAM will automatically switch back to the original FSP register set (FSP-OP[x]),
returning to the “known-good” state that was operating prior to training. The training values for VREF(ca) are not retained by the DRAM in FSP-OP[y] registers, and must be written to the registers after training exit.
1. To enter Command Bus Training mode, issue a MRW-1 command followed by a MRW-2 command to set MR13
OP[0]=1B (Command Bus Training Mode Enabled).
2. After time tMRD, CKE may be set LOW, causing the LPDDR4-SDRAM to switch from FSP-OP[x] to FSP-OP[y], and
completing the entry into Command Bus Training mode.
A status of DQS_t, DQS_c, DQ and DMI are as follows, and DQ ODT state will be followed Frequency Set Point function
except output pins.
- DQS_t[0], DQS_c[0] become input pins for capturing DQ[6:0] levels by its toggling.
- DQ[5:0] become input pins for setting VREF(ca) Level.
- DQ[6] becomes a input pin for setting VREF(ca) Range.
- DQ[7] and DMI[0] become input pins and their input level is Valid level or floating, either way is fine.
- DQ[13:8] become output pins to feedback its capturing value via command bus by CS signal.
- DQS_t[1], DQS_c[1],DMI[1] and DQ[15:14] become output pins or disable, it means that SDRAM may drive to a
valid level or left floating.
3. At time tCAENT later, LPDDR4 SDRAM can accept to chage its VREF(ca) Range and Value using input signals of
DQS_t[0], DQS_c[0] and DQ[6:0] from existing value that’s setting via MR12 OP[6:0]. The mapping between MR12 OP
code and DQ signals is shown in the table below. At least one Vref CA setting is required before proceed to next training
steps.
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MR12 OP code
DQ Number
Table - Mapping of MR12 OP Code and DQ Numbers
Mapping
OP6
OP5
OP4
OP3
OP2
DQ6
DQ5
DQ4
DQ3
DQ2
OP1
DQ1
OP0
DQ0
4. The new VREF(ca) value must “settle” for time tVREF_LONG before attempting to latch CA information.
5. To verify that the receiver has the correct VREF(ca) setting and to further train the CA eye relative to clock (CK),
values latched at the receiver on the CA bus are asynchronously output to the DQ bus.
6. To exit Command Bus Training mode, drive CKE HIGH, and after time tVREF_LONG issue the MRW-1 command followed by the MRW-2 command to set MR13 OP[0]=0B. After time tMRW the LPDDR4-SDRAM is ready for normal operation. After training exit the LPDDR4-SDRAM will automatically switch back to the FSP-OP registers that were in use
prior to training.
Command Bus Training may executed from IDLE, or Self Refresh states. When executing CBT within the Self Refresh
state, the SDRAM must not be a power down state (i.e. CKE must be HIGH prior to training entry). Command Bus Training entry and exit is the same, regardless of the SDRAM state from which CBT is initiated.
4.23.0.1. Training Sequence for single-rank systems:
Note that an example shown here is assuming an initial low-frequency, no-terminating operating point, training a highfrequency, terminating operating point. The green text is low-frequency, magenta text is high-frequency. Any operating
point may be trained from any known good operating point)
1. Set MR13 OP[6]=1B to enable writing to Frequency Set Point ‘y’ (FSP-WR[y]) (or FSP-OP[x], See note).
2. Write FSP-WR[y] (or FSP-WR[x]) registers for all channels to set up high-frequency operating parameters.
3. Issue MRW-1 and MRW-2 commands to enter Command Bus Training mode.
4. Drive CKE LOW, and change CK frequency to the high-frequency operating point.
5. Perform Command Bus Training (VREFca, CS, and CA).
6. Exit training by driving CKE HIGH, a change CK frequency to the low-frequency operating point prior to driving CKE
HIGH, then issue MRW-1 and MRW-2 commands. When CKE is driven HIGH, the SDRAM will automatically switch back
to the FSP-OP registers that were in use prior to training (i.e. trained values are not retained by the SDRAM).
7. Write the trained values to FSP-WR[y] (or FSP-WR[x]) by issuing MRW-1 and MRW-2 commands to the SDRAM and
setting all applicable mode register parameters.
8. Issue MRW-1 and MRW-2 commands to switch to FSP-OP[y] (or FSP-OP[x]), to turn on termination, and change CK
frequency to the highfrequency operating point. At this point the Command Bus is trained and you may proceed to other
training or normal operation.
4.23.0.2. Training Sequence for multi-rank systems:
(Example shown here is assuming an initial low-frequency operating point, training a high-frequency operating point.
The green text is low-frequency, magenda text is high-frequency. Any operating point may be trained from any known
good operating point)
1. Set MR13 OP[6]=1B to enable writing to Frequency Set Point ‘y’ (FSP-WR[y]) (or FSP-WR[x], See Note).
2. Write FSP-WR[y] (or FSP-WR[x]) registers for all channels and ranks to set up highfrequency operating parameters.
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3. Read MR0 OP[7] on all channels and ranks to determine which die are terminating, signified by MR0 OP[7]=1B.
4. Issue MRW-1 and MRW-2 commands to enter Command Bus Training mode on the terminating rank.
5. Drive CKE LOW on the terminating rank (or all ranks), and change CK frequency to the high-frequency operating
point.
6. Perform Command Bus Training on the terminating rank (VREFca, CS, and CA).
7. Exit training by driving CKE HIGH, change CK frequency to the low-frequency operating point, and issue MRW-1 and
MRW-2 commands to write the trained values to FSP-WR[y] (or FSP-WR[x]). When CKE is driven HIGH, the SDRAM will
automatically switch back to the FSP-OP registers that were in use prior to training (i.e. trained values are not retained
by the SDRAM).
8. Issue MRW-1 and MRW-2 command to enter training mode on the non-terminating rank (but keep CKE HIGH)
9. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[y]
(or FSP-OP[x]), to turn on termination, and change CK frequency to the highfrequency operating point.
10. Drive CKE LOW on the non-terminating (or all) ranks. The non-terminating rank(s) will now be using FSP-OP[y] (or
FSP-OP[x]).
11. Perform Command Bus Training on the non-terminating rank (VREFca, CS, and CA).
12. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[x] (or FSP-OP[y]) to turn off termination.
13. Exit training by driving CKE HIGH on the non-terminating rank, change CK frequency to the low-frequency operating
point, and issue MRW-1 and MRW-2 commands. When CKE is driven HIGH, the SDRAM will automatically switch back
to the FSP-OP registers that were in use prior to training (i.e. trained values are not retained by the SDRAM).
14. Write the trained values to FSP-WR[y] (or FSP-WR[x]) by issuing MRW-1 and MRW-2 commands to the SDRAM and
setting all applicable mode register parameters.
15. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[y] (or FSP-OP[x]), to turn on termination, and change CK frequency to the highfrequency operating point. At this point the Command Bus is trained for
both ranks and you may proceed to other training or normal operation.
4.23.0.3. Relation between CA input pin and DQ output pin
The relation between CA input pin and DQ out pin is shown in the following table.
CA Number
DQ Number
Table - Mapping of CA input pin to DQ ouput pin
Mapping
CA5
CA4
CA3
CA2
DQ13
DQ12
DQ11
DQ10
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DQ9
CA0
DQ8
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4.23.0.4. Timing Diagram
The basic timing diagrams of Command Bus Training are shown in following figures.
Figure - Entering Command Bus Training Mode and CA Training Pattern Input and Output with
VrefCA Value Update
T0
T1
T2
T3
T4
T5
Ta0
Tb0
Tb1
Tc0
CK_t
CK_c
Td0
Te0
Te1
tCKPRECS
*1
Te2
Tf0
Tg0
Th0
Th1
Th2
tCKTSPCS
*2
*7
CKE
tCKELCK *3
tMRD
tCACD
CS
CA0-5
DES
CMD
DES
MRW-1 MRW-2 MRW-1 MRW-2
Enter Command Bus Training mode
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Valid
Valid
CA Training
Pattern A
CA
Pattern B
*4
tVREFca_Long
tCAENT
tDQSCKE
tADR
DQS_t[0]
DQS_c[0]
tDStrain
tDHtrain
Valid
DQ[6:0]
DQ[7]
DMI[0]
DQ[13:8]
Pattern A
DQ[15:14]
DMI[1]
DQS_t[1]
DQS_c[1]
VrefCA
Updating Setting from FSP Switching
Setting Value of MR X (Y)
Updating Setting
Tempororay Setting Value
(Reference)
*6
tCKELODT
ODT_CA
Mode Register X (Y)
Switching MR
Mode Register Y (X)
(Reference)
Don’t Care
Time Break
Notes:
1. After tCKELCK clock can be stopped or frequency changed any time.
2. The input clock condition should be satisfied tCKPRECS and tCKPSTCS.
3. Continue to Drive CK and Hold CA & CS pins low until tCKELCK after CKE is low (which disables command decoding).
4. DRAM may or may not capture first rising/falling edge of DQS_t/c due to an unstable first rising edge. Hence provide at least
consecutive 2 pulses of DQS signal input is required in every DQS input signal at capturing DQ[6:0] signals.
The captured value of DQ[6:0] signal level by each DQS edges are overwritten at any time and the DRAM updates its VREFca
setting of MR12 temporary after time tVREFca_Long.
5. tVREF_LONG may be reduced to tVREF_SHORT if the following conditions are met: 1) The new Vref setting is a single step above
or below the old Vref setting, and 2) The DQS pulses a single time, or the new Vref setting value on DQ[6:0] is static and meets
tDSTRAIN/tDHTRAIN for every DQS pulse applied.
6. When CKE is driven LOW, the SDRAM will switch its FSP-OP registers to use the alternate (i.e. non-active) set. Example: If the
SDRAM is currently using FSP-OP[0], then it will switch to FSP-OP[1] when CKE is driven LOW. All operating parameters should
be written to the alternate mode registers before entering Command Bus Training to ensure that ODT settings, RL/WL/nWR setting, etc., are set to the correct values. If the alternate FSP-OP has ODT_CA disabled then termination will not enable in CA Bus
Training mode. If the ODT_CA pad is bonded to Vss or floating, ODT_CA termination will never enable for that die.
7. When CKE is driven low in Command Bus Training mode, the LPDDR4-SDRAM will change operation to the alternate FSP, i.e. the
inverse of the FSP programmed in the FSP-OP mode register.
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Figure - Consecutive VrefCA Value Update
T0
Ta0
Tb0
Tb1
Td0
Tc0
CK_t
CK_c
Te0
Te1
tCKEPRECS
*1
Te2
Te3
Te4
Te5
Te6
Te7
Te8
Te9
T10
Tf0
Tf1
Tf2
Tf3
*2
*7
CKE
*3
tCKELCK
CS
CA0-5
DES
DES
DES
DES
DES
CMD
DES
DES
DES
DES
DES
Valid
CA Training
Pattern A
*4
tCAENT
tDQSCKE
tVREFca_long
tCS_VREF
tVREFca_Long
*4
*5
DQS_t[0]
DQS_c[0]
tDHtrain
tDStrain
tDHtrain
tDStrain
Valid
Valid
DQ[6:0]
DQ[7]
DMI[0]
DQ[13:8]
Pattern A
DQ[15:14]
DMI[1]
DQS_t[1]
DQS_c[1]
VrefCA
Setting Value of MR X (Y)
Updating Setting from FSP Switching
Updating Setting
Temporary Setting Value
Updating Setting
(Reference)
tCKELODT
ODT_CA
Mode Register X (Y)
*6
Switching MR
Mode Register Y (X)
(Reference)
Don’t Care
Time Break
Notes:
1. After tCKELCK clock can be stopped or frequency changed any time.
2. The input clock condition should be satisfied tCKPRECS.
3. Continue to Drive CK and Hold CA & CS pins low until tCKELCK after CKE is low (which disables command decoding).
4. DRAM may or may not capture first rising/falling edge of DQS_t/c due to an unstable first rising edge. Hence provide at least
consecutive 2 pulses of DQS signal input is required in every DQS input signal at capturing DQ6:0 signals.
The captured value of DQ[6:0] signal level by each DQS edges are overwritten at any time and the DRAM updates its VREFca
setting of MR12 temporary after time tVREFca_Long.
5. tVREF_LONG may be reduced to tVREF_SHORT if the following conditions are met: 1) The new Vref setting is a single step above
or below the old Vref setting, and 2) The DQS pulses a single time, or the new Vref setting value on DQ[6:0] is static and meets
tDSTRAIN/tDHTRAIN for every DQS pulse applied.
6. When CKE is driven LOW, the SDRAM will switch its FSP-OP registers to use the alternate (i.e. non-active) set. Example: If the
SDRAM is currently using FSP-OP[0], then it will switch to FSP-OP[1] when CKE is driven LOW. All operating parameters should
be written to the alternate mode registers before entering Command Bus Training to ensure that ODT settings, RL/WL/nWR setting, etc., are set to the correct values. If the alternate FSP-OP has ODT_CA disabled then termination will not enable in CA Bus
Training mode. If the ODT_CA pad is bonded to Vss or floating, ODT_CA termination will never enable for that die.
7. When CKE is driven low in Command Bus Training mode, the LPDDR4-SDRAM will change operation to the alternate FSP, i.e. the
inverse of the FSP programmed in the FSP-OP mode register.
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Figure - Exiting Command Bus Training Mode with Valid Command
T0
T1
T2
Ta0
Ta1
CK_t
CK_c
Ta2
Tc0
Tb0
Td0
Td1
Te0
Te1
Tf0
Tf1
Tf2
Tf3
Tf4
Tg0
Tg1
Tg2
Tg3
Tg4
VALID
VALID
VALID
VALID
Tg5
tCKPSTCS
CKE
*5
tFC
tCKCKEH
tCACD
tMRW
CS
*2
CA0-5
CMD
Valid
Valid
CA
Pattern B
CA
Pattern C
tADR
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
MRW-1
MRW-1
MRW-1
MRW-1
Exiting Command Bus Training Mode
DES
DES
VALID
DES
Don’t Care
Time Break
DES
tCKEHDQS
tADR
DQS_t[0]
DQS_c[0]
DQ[6:0]
DQ[7]
DMI[0]
tMRZ
DQ[13:8]
Pattern A
Pattern B
Pattern C
DQ[15:14]
DMI[1]
DQS_t[1]
DQS_c[1]
*4
VrefCA
Temporary Setting Value
Setting Value of M X (Y)
Switching MR
(Reference)
tCKELODToff
ODT_CA
Mode Register X (Y)
Switching MR
*3
Mode Register Y (X)
(Reference)
Notes:
1. Clock can be stopped or frequency changed any time before tCKCKEH. CK must meet tCKCKEH before CKE is driven high.
When CKE is driven high the clock frequency must be returned to the original frequency (the frequency corresponding to the FSP
at which Command Bus Training mode was entered)
2. CS and CA[5:0] must be Deselect (all low) tCKCKEH before CKE is driven high.
3. When CKE is driven high, the SDRAM’s ODT_CA will revert to the state/value defined by FSP-OP prior to Command Bus Training
mode entry, i.e. the original frequency set point (FSP-OP, MR13-OP[7]).
Example: If the SDRAM was using FSP-OP[1] for training, then it will switch to FSP-OP[0] when CKE is driven HIGH.
4. Training values are not retained by the SDRAM, and must be written to the FSP-OP register set before returning to operation at
the trained frequency.
Example: VREF(ca) will return to the value programmed in the original set point.
5. When CKE is driven high the LPDDR4-SDRAM will revert to the FSP in operation when Command Bus Training mode was entered.
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Figure - Exiting Command Bus Training Mode with Power Down Entry
T0
T1
T2
Ta0
Ta1
CK_t
CK_c
Ta2
Tc0
Tb0
Td0
Td1
Te0
Te1
Tf0
Tf1
Tf2
Tf3
Tf4
Tg0
Tg1
Tg3
Tg2
tCKPSTCS
Tg4
Tg5
tCKELCK
CKE
*5
tFC
tCKCKEH
tMRD
tCKELCMD
CS
*2
CA0-5
CMD
Valid
Valid
CA
Pattern B
CA
Pattern C
tADR
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
MRW-1
MRW-1
MRW-1
MRW-1
Exiting Command Bus Training Mode
DES
DES
MRW-1
MRW-1
Power Down Entry
MRW-1
MRW-1
DES
DES
tCKEHDQS
tADR
DQS_t[0]
DQS_c[0]
DQ[6:0]
DQ[7]
DMI[0]
tMRZ
DQ[13:8]
Pattern A
Pattern B
Pattern C
DQ[15:14]
DMI[1]
DQS_t[1]
DQS_c[1]
*4
VrefCA
Temporary Setting Value
Setting Value of M X (Y)
Switching MR
(Reference)
tCKELODToff
ODT_CA
Mode Register X (Y)
Switching MR
*3
Mode Register Y (X)
(Reference)
Don’t Care
Time Break
Notes:
1. Clock can be stopped or frequency changed any time before tCKCKEH. CK must meet tCKCKEH before CKE is driven high.
When CKE is driven high the clock frequency must be returned to the original frequency (the frequency corresponding to the FSP
at which Command Bus Training mode was entered)
2. CS and CA[5:0] must be Deselect (all low) tCKCKEH before CKE is driven high.
3. When CKE is driven high, the SDRAM’s ODT_CA will revert to the state/value defined by FSP-OP prior to Command Bus Training
mode entry, i.e. the original frequency set point (FSP-OP, MR13-OP[7]).
Example: If the SDRAM was using FSP-OP[1] for training, then it will switch to FSP-OP[0] when CKE is driven HIGH.
4. Training values are not retained by the SDRAM, and must be written to the FSP-OP register set before returning to operation at
the trained frequency.
Example: VREF(ca) will return to the value programmed in the original set point.
5. When CKE is driven high the LPDDR4-SDRAM will revert to the FSP in operation when Command Bus Training mode was entered.
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4.24. Frequency Set Point (FSP)
Frequency Set-Points allow the LPDDR4-SDRAM CA Bus to be switched between two differing operating frequencies,
with changes in voltage swings and termination values, without ever being in an un-trained state which could result in
a loss of communication to the DRAM. This is accomplished by duplicating all CA Bus mode register parameters, as well
as other mode register parameters commonly changed with operating frequency. These duplicated registers form two
sets that use the same mode register addresses, with read/write access controlled by MR bit FSP-WR (Frequency SetPoint Write/Read) and the DRAM operating point controlled by another MR bit FSP-OP (Frequency Set-Point Operation).
Changing the FSP-WR bit allows MR parameters to be changed for an alternate Frequency Set-Point without affecting
the LPDDR4-SDRAM's current operation. Once all necessary parameters have been written to the alternate Set-Point,
changing the FSP-OP bit will switch operation to use all of the new parameters simultaneously (within tFC), eliminating
the possibility of a loss of communication that could be caused by a partial configuration change.
Parameters which have two physical registers controlled by FSP-WR and FSP-OP include:
Table - Mode Register Function with two physical registers
MR#
Operand
Function
OP[3]
RD-PRE (RD Pre-amble Type)
MR1
OP[6:4]
nWR (Write-Recovery for Auto-Pre-charge commands)
OP[7]
RPST (RD Post-Amble Length)
OP[2:0]
RL (Read Latency)
MR2
OP[5:3]
WL (Write Latency)
OP[6]
WLS (Write Latency Set)
OP[0]
PU-Cal (Pull-up Calibration Point)
OP[1]
WR PST (WR Post-Amble Length)
MR3
OP[5:3]
PDDS (Pull-down Drive Strength)
OP[6]
DBI-RD (DBI Read Enable)
OP[7]
DBI-WR (DBI Write Enable)
OP[2:0]
DQ ODT (DQ Bus Receiver On-Die-Termination)
MR11
OP[6:4]
CA ODT (CA Bus Receiver On-Die-Termination)
OP[5:0]
VREF(ca) (Vref(ca) Setting)
MR12
OP[6]
VR-CA (Vref(ca) Range)
OP[5:0]
Vref(dq) (Vref(dq) Setting)
MR14
OP[6]
VR-DQ (Vref(dq) Range)
OP[2:0]
SoC ODT (Controller ODT Value for VOH calibration)
OP[3]
ODTE-CK (CK ODT Enabled for nonterminating rank)
MR22
OP[4]
ODTE-CS (CS ODT enable for non terminating rank)
OP[5]
ODTD-CA (CA ODT termination disable)
Note
1
Note:
1. The synchronization MR3 OP[0] setting between Ch.0 and Ch.1 then the ZQ calibration is required in order to achieve a Driver
strength and ODT tolerance to change MR3 OP[0] PU-CAL is changed through FSP.
See Mode Register Definition for more details.
Following table shows how the two mode registers for each of the parameters above can be modified by setting the
appropriate FSP-WR value, and how device operation can be switched between operating points by setting the appropriate FSP-OP value. The FSP-WR and FSP-OP functions operate completely independently.
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Function
MR# &
Operand
FSP-WR
MR13 OP[6]
FSP-OP
MR13 OP[7]
Data
0 (Default)
1
0 (Default)
1
Operation
Note
Data write to Mode Register N for FSP-OP[0] by MRW command.
Data write to Mode Register N for FSP-OP[1] by MRW command.
DRAM operates with Mode Register N for FSP-OP[0] setting.
DRAM operates with Mode Register N for FSP-OP[1] setting.
1
2
Notes:
1. FSP-WR stands for Frequency Set Point Write/Read.
2. FSP-OP stands for Frequency Set Point Operating Point.
4.24.0.1. Frequency Set Point update timing
The Frequency set point update timing is shown in the timing diagram below. When changing the frequency set point via
MR13 OP[7], the VRCG setting: MR13 OP[3] have to be changed into VREF Fast Response (high current) mode at the
same time. After Frequency change time(tFC) is satisfied. VRCG can be changed into Normal Operation mode via MR13
OP[3].
Figure - Frequency Set Point Switching Timing
T0
T1
T2
T3
T4
T5
Ta0
Ta1
Tb0
Tb1
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
CK_c
CK_t
tCKFSPE
Frequency * 1
Change
tVRCG_DISABLE
tCKFSPX
CKE
CS
CA
COMMAND
DES
MRW-1
MRW-2
DES
DES
DES
DES
DES MRW-1 MRW-1 MRW-2 MRW-2 DES
DES
FSP changes from 0 to 1
VRCG changes from normal to High current
DES
DES
DES
DES
DES
MRW-1
MRW-2
VRCG changes
from High current to normal
DES
tFC_Short/Middle/Long
Applicable
Mode
Register
Mode Register for FSP-OP[0]
Switching Mode Register
Mode Register for FSP-OP[1]
NOTES : 1. The definition that is Clock frequency change during CKE HIGH should be followed at the frequency change operation.
For more information, refer to Section 4.42 Input Clock Stop and Frequency Change.
Table - tFC value mapping
Step size
Application
From FSP-OP0
To FSP-OP1
tFC_Short
Base
A single step increment/decrement
tFC_Middle
Base
Two or more steps increment/decrement
tFC_Long
-
DON'T CARE
TIME BREAK
Range
From FSP-OP0 To FSP-OP1
Base
No Change
Base
No Change
Base
Change
Notes:
1. As well as from FSP-OP1 to FSP-OP0
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Case
1
2
3
Table - tFC value mapping example
Vref(ca) set- Vref(ca)
FSP-OP
ting:
Range:
MR13 OP[7]
MR12:
MR12
OP[5:0]
OP[6]
0
001100
0
1
001101
0
0
001100
0
1
001110
0
0
Don’t care
0
1
Don’t care
1
From/To
From
To
From
To
From
To
Application
Note
tFC_Short
1
tFC_Middle
2
tFC_Long
3
Notes:
1. A single step size increment/decrement for Vref(ca) Setting Value.
2. Two or more step size increment/decrement for Vref(ca) Setting Value.
3. VREF(ca) Range is changed. In tis case changing VREF(ca) Setting doesn’t affect tFC value.
The LPDDR4-SDRAM defaults to FSP-OP[0] at power-up. Both Set-Points default to settings needed to operate in unterminated, low-frequency environments. To enable the LPDDR4-SDRAM to operate at higher frequencies, Command
Bus Training mode should be utilized to train the alternate Frequency Set-Point (Figure “Training Two Frequency Set
Points”). See the section Command Bus Training for more details on this training mode.
Figure - Training Two Frequency Set Points
Prepare for CBT
of FSP[1] for
High Frequency
Power up/
Initialization
FSP-OP=0
FSP-WR=0
Freq = Boot
FSP-OP=0
FSP-WR=1
Freq = Boot
CA Bus Training
FSP-OP[1]
CKE high -> Low
FSP-WR=1
Freq = High
CKE Low -> High
Exit CA Bus
Training
Switch to High
Speed Mode
FSP-OP=0
FSP-WR=1
Freq = Boot
FSP-OP=1
FSP-WR=1
Freq = High
Prepare for CBT
of FSP[0] for
Med. Frequency
FSP-WR=0
Freq = High
CKE High -> Low
CA Bus Training
FSP-OP[0]
FSP-WR=0
Freq = Med
Exit CBT
CKE Low -> High
FSP-OP=1
FSP-WR=0
Freq = High
Operate at
High Speed
Once both Frequency Set Points have been trained, switching between points can be performed by a single MRW followed by waiting for tFC (figure below)
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Figure - Switching between two trained Frequency Set Points
State n-1: FSP-OP=1
MRW Command
State n: FSP-OP=0
Operate at
High Speed
State n-1: FSP-OP=0
MRW Command
State n: FSP-OP=1
tFC
Operate at
Middle Speed
tFC
Operate at
High Speed
Switching to a third (or more) Set-Point can be accomplished if the memory controller has stored the previously-trained
values (in particular the Vref-CA calibration value) and re-writes these to the alternate Set-Point before switching FSPOP (Figure below).
Figure - Switching to a third trained Frequency Set Point
Operate at
High Speed
State n-1: FSP-OP=1
State n: FSP-OP=0
State n-1: FSP-WR=1
State n: FSP-WR=0
tFC
Rev 1.1 / Sep 2016 / SK hynix Confidential
tFC
MRW Vref(ca)
CA-ODT, DQ-ODT,
RL, WL, Vref(dq), etc
Operate at
Third Speed
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LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.25. Write Leveling Mode
To improve signal-integrity performance, the LPDDR4 SDRAM provides a write-leveling feature to compensate CK-toDQS timing skew affecting timing parameters such as tDQSS, tDSS, and tDSH. The DRAM samples the clock state with
the rising edge of DQS signals, and asynchronously feeds back to the memory controller. The memory controller
references this feedback to adjust the clock-to-data strobe signal relationship for each DQS_t/DQS_c signal pair.
All data bits (DQ[7:0] for DQS_t/DQS_c[0], and DQ[15:8] for DQS_t/DQS_c[1]) carry the training feedback to the
controller. Both DQS signals in each channel must be leveled independently. Write-leveling entry/exit is independent
between channels.
The LPDDR4 SDRAM enters into write-leveling mode when mode register MR2-OP[7] is set HIGH. When entering
write-leveling mode, the state of the DQ pins is undefined. During write-leveling mode, only DESELECT commands are
allowed, or a MRW command to exit the write-leveling operation. Depending on the absolute values of tQSL and tQSH
in the application, the value of tDQSS may have to be better than the limits provided in the chapter “AC Timing
Parameters” in order to satisfy the tDSS and tDSH specification. Upon completion of the write-leveling operation, the
DRAM exits from write-leveling mode when MR2-OP[7] is reset LOW.
Write Leveling should be performed before Write Training (DQS2DQ Training).
Write Leveling Procedure:
1. Enter into Write-leveling mode by setting MR2-OP[7]=1,
2. Once entered into Write-leveling mode, DQS_t must be driven LOW and DQS_c HIGH after a delay of tWLDQSEN.
3. Wait for a time tWLMRD before providing the first DQS signal input. The delay time tWLMRD(MAX) is controllerdependent.
4. DRAM may or may not capture first rising edge of DQS_t due to an unstable first risign edge. Hence provide at least
consecutive 2 pulses of DQS signal input is required in every DQS input signal during Write Training Mode.
The captured clock level by each DQS edges are overwritten at any time and the DRAM provides asynchronous
feedback on all the DQ bits after time tWLO.
5. The feedback provided by the DRAM is referenced by the controller to increment or decrement the DQS_t and/or
DQS_c delay settings.
6. Repeat step 4 through step 5 until the proper DQS_t/DQS_c delay is established.
7. Exit from Write-leveling mode by setting MR2-OP[7]=0.
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A Write Leveling timing example is shown in figure below.
Figure - Write Leveling Timing,
T0
T1
T2
T3
T4
MRW
MA
MRW
MA
MRW
OP
MRW
OP
DES
Ta0 Ta1 Tb0 Tb1 Tc0 Tc1
tDQSL(max)
Td0 Td1 Td2 Td3 Te0 Te1 Tf0
Tf1 Tf2 Tf3 Tf4
Tg0 Tg1 Tg2 Tg3 Tg4
CK_t
CK_c
CS
CKE
CA
CMD
MRW-1
WR Leveling
MRW-2
WR Leveling
DES
DES
DES
Deselect
Deselect
DES
DES
Deselect
DES
DES
Deselect
DES
DES
Deselect
DES
DES
DES
Deselect
DES
Deselect
MRW
MA
MRW
MA
MRW-1
WR Lev Exit
MRW
OP
MRW
OP
MRW-2
WR Lev Exit
DES
DES
Valid
Valid
Valid
Deselect
Valid
Valid
Valid
tDQSH
tWLDQSEN
tDQSL
tWLWPRE
DQS_c
DQS_t
tWLMRD
tWLO
tWLO
tMRD
tWLO
DQ
Figure - Write Leveling Timing,
T0
T1
T2
T3
T4
MRW
MA
MRW
MA
MRW
OP
MRW
OP
DES
Ta0 Ta1 Tb0 Tb1 Tc0 Tc1
tDQSL(min)
Td0 Td1 Td2 Td3 Te0 Te1 Tf0
Tf1 Tf2 Tf3 Tf4
Tg0 Tg1 Tg2 Tg3
CK_t
CK_c
CS
CKE
CA
CMD
MRW-1
WR Leveling
MRW-2
WR Leveling
DES
Deselect
DES
DES
Deselect
DES
DES
Deselect
tDQSH
tWLDQSEN
DES
DES
Deselect
DES
DES
Deselect
DES
DES
DES
Deselect
DES
Deselect
MRW
MA
MRW
MA
MRW-1
WR Lev Exit
MRW
OP
MRW
OP
MRW-2
WR Lev Exit
DES
DES
Valid
Valid
Deselect
Valid
Valid
Valid
Valid
tDQSL
tWLWPRE
DQS_c
DQS_t
tWLMRD
tWLO
tWLO
tMRD
DQ
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4.25.1. Input Clock Frequency Stop and Change
The input clock frequency can be stopped or changed from one stable clock rate to another stable clock rate during
Write Leveling mode.
The Frequency stop or change timing is shown in Figure below
Figure - Clock Stop and Timing during Write Leveling
T0
T1
T2
T3
T4
Ta0
Ta1
Tb0 Tb1
Tb2
Tc0
Td0
Te0
Te1 Te2
Te3
Te4
Tf0
DES
DES
DES
Tf1
Tf2
Tf3
CK_t
CK_c
tCKPSTDQS
tCKPRDQS
CS
CKE
MRW
MA
CA
CMD
MRW
MA
MRW-1
WR Leveling
MRW
OP
MRW
OP
MRW-2
WR Leveling
DES
DES
DES
Deselect
Deselect
tWLDQSEN
DES
DES
DES
DES
DES
Deselect
DES
Deselect
DES
DES
Deselect
Deselect
DES
Deselect
DES
DES
Deselect
tDQSH
tDQSL
tWLWPRE
DQS_c
DQS_t
tWLMRD
tWLO
tWLO
tWLO
tWLO
DQ
NOTES : 1. CK_t is held LOW and CK_c is held HIGH during clock stop.
2. CS shall be held LOW during clock clock stop
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4.26. MPC [RD DQ Calibration] Command
LPDDR4 devices feature a RD DQ Calibration training function that outputs a 16-bit user-defined pattern on the DQ pins.
RD DQ Calibration is initiated by issuing a MPC [RD DQ Calibration] command followed by a CAS-2 command, cause
the LPDDR4-SDRAM to drive the contents of MR32 followed by the contents of MR40 on each of DQ[15:0] and DMI[1:0].
The pattern can be inverted on selected DQ pins according to user-defined invert masks written to MR15 and MR20.
RD DQ Calibration Training Procedure
The procedure for executing RD DQ Calibration is:
• Issue MRW commands to write MR32 (first eight bits), MR40 (second eight bits),
MR15 (eight-bit invert mask for byte 0), and MR20 (eight-bit invert mask for byte 1)
o Optionally this step could be skipped to use the default patterns
• MR32 default = 5Ah
• MR40 default = 3Ch
• MR15 default = 55h
• MR20 default = 55h
• Issue an MPC [RD DQ Calibration] command followed immediately by a CAS-2 command
o Each time an MPC [RD DQ Calibration] command followed by a CAS-2 is received by the LPDDR4 SDRAM,
a 16-bit data burst will, after the currently set RL, drive the eight bits programmed in MR32 followed by the
eight bits programmed in MR40 on all I/O pins
o The data pattern will be inverted for I/O pins with a ‘1’ programmed in the corresponding invert mask
mode register bit (see Table "Invert Mask Assignments")
o Note that the pattern is driven on the DMI pins, but no data bus inversion function is enabled,
even if Read DBI is enabled in the DRAM mode register.
o The MPC-1 [RD DQ Calibration] command can be issued every tCCD seamlessly, and tRTRRD delay is required
between Array Read command and the MPC-1 [RD DQ Calibration] command as well the delay required between
the MPC-1 [RD DQ Calibration] command and an array read.
o The operands received with the CAS-2 command must be driven LOW
• DQ Read Training can be performed with any or no banks active, during Refresh, or during SREF with CKE high
Pin
MR20
DQ8
OP0
DQ9
OP1
Pin
MR15
DQ0
OP0
DQ1
OP1
Table - Invert Mask Assignments
DQ10
DQ11
DMI1
DQ12
OP2
OP3
N/A
OP4
DQ2
OP2
Rev 1.1 / Sep 2016 / SK hynix Confidential
DQ3
OP3
DMI0
N/A
DQ4
OP4
DQ13
OP5
DQ14
OP6
DQ15
OP7
DQ5
OP5
DQ6
OP6
DQ7
OP7
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H9HCNNN8KUMLHR Series
LPDDR4 8Gb (x16, 2 Channel, 1 CS)
Figure - DQ Read Training Timing: Read to Read DQ Calibration
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Tb0
Tb1
Tb2
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Td1
Td2
Td3
Td4
Td5
Td6
Te0
Te1
Te2 Te3
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES DES
CK_c
CK_t
CS
CA
COMMAND
Read-1
CAS-2
Valid Valid Valid Valid
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
MPC
RD DQ Cal.
CAS-2
tRTRRD
RL
RL
tDQSCK
tDQSCK
tRPST
tRPRE
tRPST
tRPRE
DQS_c
DQS_t
Hi-Z
DQ
Hi-Z
Hi-Z
Hi-Z
tDQSQ
tDQSQ
n0 n13 n14 n15
n0 n13 n14 n15
Hi-Z
NOTES : 1. Read-1 to MPC [RD DQ Calibration] Operation is shown as an example of command-to-command timing.
Timing from Read-1 to MPC [RD DQ Calibration] command is tRTRRD.
2. MPC [RD DQ Calibration] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a Read-1 command.
3. BL = 16, Read Preamble: Toggle, Read Postamble: 0.5nCK.
4. DES commands are shown for ease of illustration; other commands may be valid at these times.
DON'T CARE
Hi-Z
TIME BREAK
Figure - DQ Read Training Timing: Read DQ Cal. to Read DQ Cal. / Read
T0
T1
T2
T8
T3
T9
T10
T11
T12
T13
T14
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tc0
Tc1
Tc2
Tc3
Tc4
BL
BA0,
CA
CAn
CAn
Tc5
Td0
Td1
Td2
Td3
Td4
Te0 Te1
DES
DES
DES
DES
DES
DES
DES DES
CK_c
CK_t
CS
CA
COMMAND
Valid Valid Valid Valid
Valid Valid Valid Valid
MPC
RD DQ Cal.
CAS-2
DES
MPC
RD DQ Cal.
CAS-2
DES
DES
tCCD
RL
DES
DES
DES
DES
DES
DES
DES
DES
Read-1
CAS-2
tRTRRD
RL
tDQSCK
RL
tDQSCK
tDQSCK
tRPST
tRPRE
tRPRE
tRPST
DQS_c
DQS_t
Hi-Z
Hi-Z
tDQSQ
DQ
Hi-Z
tDQSQ
n0 n9 n10 n11 n12 n13 n14 n15 n0 n13 n14 n15
NOTES : 1. MPC [RD DQ Calibration] to MPC [RD DQ Calibration] Operation is shown as an example of command-to-command timing.
2. MPC [RD DQ Calibration] to Read-1 Operation is shown as an example of command-to-command timing.
3. MPC [RD DQ Calibration] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a Read-1 command.
4. Seamless MPC [RD DQ Calibration] commands may be executed by repeating the command every tCCD time.
5. Timing from MPC [RD DQ Calibration] command to Read-1 is tRTRRD.
6. BL = 16, Read Preamble: Toggle, Read Postamble: 0.5nCK.
7. DES commands are shown for ease of illustration; other commands may be valid at these times.
Rev 1.1 / Sep 2016 / SK hynix Confidential
tDQSQ
n0 n13 n14 n15
Hi-Z
DON'T CARE
128
TIME BREAK
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LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.26.1. MPC [RD DQ Calibration] Example
An example of MPC [RD DQ Calibration] output is shown in Table "MPC [RD DQ Calibration] Bit Ordering and Inversion
Example". This shows the 16-bit data pattern that will be driven on each DQ when one DQ Read Training command is
executed. This output assumes the following mode register values are used:
• MR32 = 1CH
• MR40 = 59H
• MR15 = 55H
• MR20 = 55H
Pin
DQ0
DQ1
DQ2
DQ3
DMI0
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DMI1
DQ12
DQ13
DQ14
DQ15
Invert?
Yes
No
Yes
No
Never
Yes
No
Yes
No
Yes
No
Yes
No
Never
Yes
No
Yes
No
Table - MPC [RD DQ Calibration] Bit Ordering and Inversion Example
Bit sequence ->
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
1
0
0
1
1
0
1
1
1
0
0
0
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
0
1
1
0
1
1
1
0
0
0
1
0
1
1
0
0
1
0
0
0
1
1
0
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
0
1
1
0
1
1
1
0
0
0
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
0
1
1
0
1
1
1
0
0
0
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
0
1
1
0
1
1
1
0
0
0
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
0
1
1
0
1
1
1
0
0
0
1
0
1
1
0
0
1
0
0
0
1
1
0
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
0
1
1
0
1
1
1
0
0
0
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
0
1
1
0
1
1
1
0
0
0
1
0
1
1
0
0
1
0
0
0
1
1
2
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
1
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
Notes:
1. The patterns contained in MR32 and MR40 are transmitted on DQ[15:0] and DMI[1:0] when RD DQ Calibration is initiated via a
MPC [RD DQ Calibration] command. The pattern transmitted serially on each data lane, organized “little endian” such that the low
order bit in a byte is transmitted first. If the data pattern is 27H, then the first bit transmitted with be a ‘1’, followed by ‘1’, ‘1’, ‘0’,
‘0’, ‘1’, ‘0’, and ‘0’. The bit stream will be 00100111.
2. MR15 and MR22 may be used to invert the MR32/MR40 data pattern on the DQ pins. See MR15 and MR20 for more information.
Data is never inverted on the DMI[1:0] pins.
3. DMI [1:0] outputs status follows in the table below
Table - MR Setting vs. DMI Status
DM Function
MR13 OP[5]
Write DBIdc Function
MR3 OP[7]
Read DBIdc Function
MR3 OP[6]
DMI Status
1: Disable
0: Disable
0: Disable
Hi-Z
1: Disable
1: Enable
0: Disable
The data pattern is transmitted
1: Disable
0: Disable
1: Enable
The data pattern is transmitted
1: Disable
1: Enable
1: Enable
The data pattern is transmitted
0: Enable
0: Disable
0: Disable
The data pattern is transmitted
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DM Function
MR13 OP[5]
Write DBIdc Function
MR3 OP[7]
Read DBIdc Function
MR3 OP[6]
DMI Status
0: Enable
1: Enable
0: Disable
The data pattern is transmitted
0: Enable
0: Disable
1: Enable
The data pattern is transmitted
0: Enable
1: Enable
1: Enable
The data pattern is transmitted
4. No Data Bus Inversion (DBI) function is enacted during RD DQ Calibration, even if DBI is enabled in MR3-OP[6].
4.26.2. MPC of Read DQ Calibration after Power-Down Exit
Following the power-down state, an additional time, tMRRI, is required prior to issuing the MPC of Read DQ Calibration
command. This additional time (equivalent to tRCD) is required in order to be able to maximize power-down current
savings by allowing more power-up time for the Read DQ data in MR32 and MR40 data path after exit from standby,
power-down mode.
Figure - MPC Read DQ Calibration Following Power-Down State
T0
Ta0
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Td0
Td1
Td2
Td3
Td4
Td5 Td6
Td7
Td8
Td9
DES
DES
DES
CK_c
CK_t
tCKCKEH
CKE
tXP
tMRRI
CS
CA
COMMAND
Valid Valid Valid Valid
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
MPC
Read DQ Cal
CAS-2
DON'T CARE
Rev 1.1 / Sep 2016 / SK hynix Confidential
TIME BREAK
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LPDDR4 8Gb (x16, 2 Channel, 1 CS)
4.27. MPC Write Training (DQS-DQ Training)
The LPDDR4-SDRAM uses an un-matched DQS-DQ path to enable high speed performance and save power in the
DRAM. As a result, the DQS strobe must be trained to arrive at the DQ latch center-aligned with the Data eye. The
SDRAM DQ receiver is located at the DQ pad, and has a shorter internal delay in the SDRAM than does the DQS signal.
The SDRAM DQ receiver will latch the data present on the DQ bus when DQS reaches the latch, and training is accomplished by delaying the DQ signals relative to DQS such that the Data eye arrives at the receiver latch centered on the
DQS transition.
Two modes of training are available in LPDDR4:
- Command-based FIFO WR/RD with user patterns
- A internal DQS clock-tree oscillator, to determine the need for, and the magnitude of, required training.
The command-based FIFO WR/RD uses the MPC command with operands to enable this special mode of operation.
When issuing the MPC command, if OP6 is set LOW then the DRAM will perform a NOP command. When OP6 is set
HIGH, then OP5:0 enable training functions or are reserved for future use (RFU). MPC commands that initiate a Read
FIFO, READ DQ Calibration or Write FIFO to the SDRAM must be followed immediately by a CAS-2 command. See "Multi
Purpose Command (MPC) Definition" for more information.
To perform Write Training, the controller can issue a MPC [Write DQ FIFO] command with OP[6:0] set as described in
the MPC Definition section, followed immediately by a CAS-2 command (CAS-2 operands should be driven LOW) to initiate a Write DQ FIFO. Timings for MPC [Write DQ FIFO] are identical to a Write command, with WL (Write Latency)
timed from the 2nd rising clock edge of the CAS-2 command. Up to 5 consecutive MPC [Write DQ FIFO] commands with
user defined patterns may be issued to the SDRAM to store up to 80 values (BL16 x5) per pin that can be read back
via the MPC [Read DQ FIFO] command. Write/Read FIFO Pointer operation is described later in this section.
After writing data to the SDRAM with the MPC [Write DQ FIFO] command, the data can be read back with the MPC
[Read DQ FIFO] command and results compared with “expect” data to see if further training (DQ delay) is needed. MPC
[Read DQ FIFO] is initiated by issuing a MPC command with OP[6:0] set as described in the MPC Definition section,
followed immediately by a CAS-2 command (CAS-2 operands must be driven LOW). Timings for the MPC [Read DQ
FIFO] command are identical to a Read command, with RL (Read Latency) timed from the 2nd rising clock edge of the
CAS-2 command.
Read DQ FIFO is non-destructive to the data captured in the FIFO, so data may be read continuously until it is either
overwritten by a Write DQ FIFO command or disturbed by CKE LOW or any of the following commands; Write, Masked
Write, Read, Read DQ Calibration and a MRR. If fewer than 5 Write DQ FIFO commands were executed, then unwritten
registers will have un-defined (but valid) data when read back.
The following command about MRW is only allowed from MPC [Write DQ FIFO] command to MPC [Read DQ FIFO].
Allowing MRW command is for OP[7]:FSP-OP, OP[6]:FSP-WR and OP[3]:VRCG of MR13 and MR14. And the rest of MRW
command is prohibited.
For example: If 5 Write DQ FIFO commands are executed sequentially, then a series of Read DQ FIFO commands will
read valid data from FIFO[0], FIFO[1]….FIFO[4], and will then wrap back to FIFO[0] on the next Read DQ FIFO.
On the other hand, if fewer than 5 Write DQ FIFO commands are executed sequentially (example=3), then a series of
Read DQ FIFO commands will return valid data for FIFO[0], FIFO[1], and FIFO[2], but the next two Read DQ FIFO
commands will return un-defined data for FIFO[3] and FIFO[4] before wrapping back to the valid data in FIFO[0].
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4.27.1. FIFO Pointer Reset and Synchronism
The Write DQ FIFO pointer is reset under the following conditions:
- Power-up initialization
- RESET_n asserted
- Power-down entry
- Self Refresh Power-Down entry
The MPC [Write DQ FIFO] command advances the WR-FIFO pointer, and the MPC [Read DQ FIFO] advances the RDFIFO pointer. Also any normal (non-FIFO) Read Operation (RD, RDA) advances both WR-FIFO pointer and RD-FIFO
pointer. Issuing (non-FIFO) Read Operation command is inhibited during Write training period. To keep the pointers
aligned, the SoC memory controller must adhere to the following restriction at the end of Write training period:
b=a+(n*c)
Where:
‘a’ is the number of MPC [Write DQ FIFO] commands
‘b’ is the number of MPC [Read DQ FIFO] commands
‘c’ is the FIFO depth (=5 for LPDDR4)
‘n’ is a positive integer, ≥ 0
Figure - MPC [Write DQ FIFO] Operation Timing
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
Ta0
T4
Ta1
Ta2
Tb0
Tb1
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Td0
Td1
Td2
Td3
Td4
Td5
Te0
Te1
Te2
Tf0
Tf1
Tg0
Tg1
Tg2 Tg3
DES
DES
DES
DES
DES
DES
DES
DES
DES DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
Valid Valid Valid Valid
Valid Valid Valid Valid
DES
DES
DES
DES
DES
DES
DES
MPC
WR FIFO
CAS-2
DES
tWRWTR
DES
MPC
WR FIFO
tCCD = 8
CAS-2
WL
WL
WL
tDQSS
tWPRE
tDQSS
tWPST
tDQSS
tWPST
tWPRE
DQS_c
DQS_t
Don’t Care
DQ
Don’t Care
Don’t Care
tDQS2DQ
Don’t Care
tDQS2DQ
n0 n13 n14 n15
Don’t Care
NOTES : 1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. Write-1 to MPC is shown as an example of command-to-command timing for MPC. Timing from Write-1 to MPC [WR-FIFO] is tWRWTR.
3. Seamless MPC [WR-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC [WR-FIFO] uses the same command-to-data timing relationship (WL, tDQSS, tDQS2DQ) as a Write-1 command.
5. A maximum of 5 MPC [WR-FIFO] commands may be executed consecutively without corrupting FIFO data.
The 6th MPC [WR-FIFO] command will overwrite the FIFO data from the first command. If fewer than 5 MPC [WR-FIFO] commands are executed,
then the remaining FIFO locations will contain undefined data.
6. For the CAS-2 command following a MPC command, the CAS-2 operands must be driven “LOW.”
7. To avoid corrupting the FIFO contents, MPC [RD-FIFO] must immediately follow MPC [WR-FIFO]/CAS-2 without any other command disturbing
FIFO pointers in-between. FIFO pointers are disturbed by CKE Low, Write, Masked Write, Read, Read DQ Calibration and MRR.
8. BL = 16, Write Postamble = 0.5nCK
9. DES commands are shown for ease of illustration; other commands may be valid at these times.
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tDQS2DQ
n0 n13 n14 n15 n0 n13 n14 n15
DON'T CARE
132
Don’t Care
TIME BREAK
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LPDDR4 8Gb (x16, 2 Channel, 1 CS)
Figure - MPC [Write FIFO] to MPC [Read FIFO] Timing
T0
T1
T2
T3
Ta0
T4
Ta1
Ta2
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Td0
Td1
Td2
Td3
Td4
Td5
Te0
Te1
Te2
Te3
Tf0
Tf1
Tg0 Tg1
DES
DES
DES
DES
DES
DES
DES
DES DES
CK_c
CK_t
CS
CA
COMMAND
MPC
WR FIFO
CAS-2
Valid Valid Valid Valid
Valid Valid Valid Valid
Valid Valid Valid Valid
DES
DES
DES
DES
WL
DES
DES
DES
BL/2 + 1 Clock
DES
MPC
RD FIFO
tWTR
CAS-2
DES
DES
MPC
RD FIFO
CAS-2
tCCD = 8
RL
tDQSCK
tDQSS
tWPRE
tWPST
tRPST
tRPRE
DQS_c
DQS_t
Don’t Care
Hi-Z/Don’t Care
tDQS2DQ
DQ
Don’t Care
tDQSQ
n0 n13 n14 n15
Hi-Z/Don’t Care
n0 n13 n14 n15 n0 n13 n14 n15
DON'T CARE
NOTES : 1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. MPC [WR-FIFO] to MPC [RD-FIFO] is shown as an example of command-to-command timing for MPC.
Timing from MPC [WR-FIFO] to MPC [RD-FIFO] is specified in the command-to-command timing table.
3. Seamless MPC [RD-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC [RD-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a Read-1 command.
5. Data may be continuously read from the FIFO without any data corruption. After 5 MPC [RD-FIFO] commands the FIFO pointer will wrap back to
the 1st FIFO and continue advancing. If fewer than 5 MPC [WR-FIFO] commands were executed, then the MPC [RD-FIFO] commands to those
FIFO locations will return undefined data. See the Write Training section for more information on the FIFO pointer behavior.
6. For the CAS-2 command immediately following a MPC command, the CAS-2 operands must be driven “LOW.”
7. DMI[1:0] signals will be driven if any of WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training section for more information on DMI behavior.
8. BL = 16, Write Postamble = 0.5nCK, Read Preamble: Toggle, Read Postamble: 0.5nCK
9. DES commands are shown for ease of illustration; other commands may be valid at these times.
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Figure - MPC [Read FIFO] to Read Timing
T0
T1
T2
T3
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Tb0
Tb1
Tb2
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
BL
BA0,
CA
CAn
CAn
Tc7
Td1
Td2
Td3
Td4
Td5
Td6
Te0
Te1
Te2 Te3
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES DES
CK_c
CK_t
CS
CA
COMMAND
Valid Valid Valid Valid
MPC
RD FIFO
CAS-2
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Read-1
CAS-2
tRTRRD
RL
RL
tDQSCK
tDQSCK
tRPST
tRPRE
tRPRE
tRPST
DQS_c
DQS_t
Hi-Z
DQ
Hi-Z
Hi-Z
tDQSQ
Hi-Z
tDQSQ
n0 n13 n14 n15
Hi-Z
n0 n13 n14 n15
NOTES : 1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
DON'T CARE
2. MPC [RD-FIFO] to Read-1 Operation is shown as an example of command-to-command timing for MPC. Timing from MPC [RD-FIFO] command
to Read is tRTRRD.
3. Seamless MPC [RD-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC [RD-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a Read-1 command.
5. Data may be continuously read from the FIFO without any data corruption. After 5 MPC [RD-FIFO] commands the FIFO pointer will wrap back to
the 1st FIFO and continue advancing. If fewer than 5 MPC [WR-FIFO] commands were executed, then the MPC [RD-FIFO] commands to those
FIFO locations will return undefined data. See the Write Training section for more information on the FIFO pointer behavior.
6. For the CAS-2 command immediately following a MPC command, the CAS-2 operands must be driven “LOW.”
7. DMI[1:0] signals will be driven if any of WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training section for more information on DMI behavior.
8. BL = 16, Read Preamble: Toggle, Read Postamble: 0.5nCK
9. DES commands are shown for ease of illustration; other commands may be valid at these times.
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TIME BREAK
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LPDDR4 8Gb (x16, 2 Channel, 1 CS)
Figure - MPC [Write FIFO] with DQ ODT Timing
T0
T1
T2
T3
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Tb0
Tb1
Tb2
Tb3
Tb4 Tb5
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Tb6
CK_c
CK_t
CS
CA
COMMAND
Valid Valid Valid Valid
MPC
WR FIFO
CAS-2
DES
DES
WL
tDQSS
tWPST
tWPRE
DQS_c
DQS_t
Don’t Care
DQ
Don’t Care
Don’t Care
tDQS2DQ
n0 n1 n2 n13 n14 n15
ODTLon
Don’t Care
tODTon.Max
tODTon.Min
DRAM RTT
ODT Hi-Z
Transition
ODT On
Transition ODT Hi-Z
ODTLoff
tODToff.Min
Note
1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh,
or during SREF with CKE HIGH.
2. MPC [WR-FIFO] uses the same command-to-data/ODT timing relationship (WL, tDQSS, tDQS2DQ,
ODTLon, ODTLoff, tODTon, tODToff) as a Write-1 command.
3. For the CAS-2 command immediately following a MPC command, the CAS-2 operands must be driven “LOW.”
4. BL = 16, Write Postamble = 0.5nCK
5. DES commands are shown for ease of illustration; other commands may be valid at these times.
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tODToff.Max
DON'T CARE
TIME BREAK
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Figure - Power Down Exit to MPC [Write FIFO] Timing
T0
Ta0
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Td0
Td1
Td2
Td3
Td4
Td5 Td6
Td7
Td8
Td9
CK_c
CK_t
tCKCKEH
CKE
tXP
tMPCWR ( = tRCD + 3nCK)
WL
CS
CA
Valid Valid Valid Valid
Valid Valid Valid Valid
*1
COMMAND
DES
DES
Any Command
Any Command
DES
DES
DES
DES
MPC
WR FIFO
CAS-2
DES
DES
DES
TIME BREAK
DON'T CARE
Note
1. Any commands except MPC WR FIFO and other exception commands defined other section in this document (i.e. MPC Read DQ Cal).
2. DES commands are shown for ease of illustration; other commands may be valid at these times.
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4.28. DQS Interval Oscillator
As voltage and temperature change on the SDRAM die, the DQS clock tree delay will shift and may require re-training.
The LPDDR4-SDRAM includes an internal DQS clock-tree oscillator to measure the amount of delay over a given time
interval (determined by the controller), allowing the controller to compare the trained delay value to the delay value
seen at a later time. The DQS Oscillator will provide the controller with important information regarding the need to retrain, and the magnitude of potential error.
The DQS Interval Oscillator is started by issuing a MPC [Start DQS Osc] command with OP[6:0] set as described in the
MPC Operation section, which will start an internal ring oscillator that counts the number of time a signal propagates
through a copy of the DQS clock tree.
The DQS Oscillator may be stopped by issuing a MPC [Stop DQS Osc] command with OP[6:0] set as described in the
MPC Operation section, or the controller may instruct the SDRAM to count for a specific number of clocks and then stop
automatically (See MR23 for more information). If MR23 is set to automatically stop the DQS Oscillator, then the MPC
[Stop DQS Osc] command should not be used (illegal). When the DQS Oscillator is stopped by either method, the result
of the oscillator counter is automatically stored in MR18 and MR19.
The controller may adjust the accuracy of the result by running the DQS Interval Oscillator for shorter (less accurate)
or longer (more accurate) duration. The accuracy of the result for a given temperature and voltage is determined by
the following equation:
DQS Oscillator Granularity Error = 2 * (DQS delay) / run time
Where:
Run Time = total time between start and stop commands
DQS delay = the value of the DQS clock tree delay (tDQS2DQ min/max)
Additional matching error must be included, which is the difference between DQS training circuit and the actual DQS
clock tree across voltage and temperature. The matching error is vendor specific.
Therefore, the total accuracy of the DQS Oscillator counter is given by:
DQS Oscillator Accuracy = 1 - Granularity Error - Matching Error
For example: If the total time between start and stop commands is 100ns, and the maximum DQS clock tree delay is
800ps (tDQS2DQ max), then the DQS Oscillator Granularity Error is:
DQS Oscillator Granularity Error = 2*(0.8ns) / 100ns = 1.6%
This equates to a granularity timing error or 12.8ps.
Assuming a circuit Matching Error of 5.5ps across voltage and temperature, then the accuracy is:
DQS Oscillator Accuracy = 1 - [(12.8+5.5) / 800] = 97.7%
For example: running the DQS oscillator for a longer period improves the accuracy. If the total time between start
and stop commands is 500ns, and the maximum DQS clock tree delay is 800ps (tDQS2DQ max), then the DQS Oscillator
Granularity Error is:
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DQS Oscillator Granularity Error = 2*(0.8ns) / 500ns = 0.32%
This equates to a granularity timing error or 2.56ps.
Assuming a circuit Matching Error of 5.5ps across voltage and temperature, then the accuracy is:
DQS Oscillator Accuracy = 1 - [(2.56+5.5) / 800] = 99.0%
The result of the DQS Interval Oscillator is defined as the number of DQS Clock Tree Delays that can be counted within
the “run time,” determined by the controller. The result is stored in MR18-OP[7:0] and MR19-OP[7:0]. MR18 contains
the least significant bits (LSB) of the result, and MR19 contains the most significant bits (MSB) of the result. MR18 and
MR19 are overwritten by the SDRAM when a MPC-1 [Stop DQS Osc] command is received. The SDRAM counter will
count to its maximum value (=2^16) and stop. If the maximum value is read from the mode registers, then the memory
controller must assume that the counter overflowed the register and discard the result. The longest “run time” for the
oscillator that will not overflow the counter registers can be calculated as follows:
Longest Run Time Interval = 216 * tDQS2DQ(min) = 216 * 0.2ns = 13.1us
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4.28.1. Interval Oscillator matching error
The interval oscillator matching error is defined as the difference between the DQS training ckt(interval oscillator) and
the actual DQS clock tree across voltage and temperature.
Parameters:
- tDQS2DQ: Actual DQS clock tree delay
- tDQSOSC: Training ckt(interval oscillator) delay
- OSCOffset: Average delay difference over voltage and temp(shown in the figure below)
- OSCMatch: DQS oscillator matching error
Figure - Interval oscillator offset (OSCoffset)
Offset 2
tDQS2DQ
tDQS osc
Time
(ps)
OSC offset = avg(offset1,offset2)
Offset 1
Offset 1(at end point) = tDQS2DQ(V,T) - tDQS osc (V,T)
Offset 2(at end point) = tDQS2DQ(V,T) - tDQS osc (V,T)
Temp(T)/Voltage(V)
OSCMatch :
OSCMatch = [tDQS2DQ(V,T) - tDQSOSC(V,T) - OSCoffset ]
tDQSOSC :
tDQSOSC(V,T) = Runtime / 2 * Count
Table - DQS Oscillator Matching Error Specification
Parameter
Symbol
Min
Max
Units
DQS Oscillator Matching Error
OSCMatch
-20
20
ps
DQS Oscillator Offset
OSCoffset
-100
100
ps
Notes
1,2,3,4,5,6,7
2,4,7
Note
1. The OSCMatch is the matching error per between the actual DQS and DQS interval oscillator over voltage and temp.
2. This parameter will be characterized or guaranteed by design.
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3. The OSCMatch is defined as the following:
OSCMatch = [tDQS2DQ(V,T) - tDQSOSC(V,T) - OSCoffset ]
Where tDQS2DQ(V,T) and tDQSOSC(V,T) are determined over the same voltage and temp conditions.
4. The runtime of the oscillator must be at least 200ns for determining tDQSOSC(V,T)
tDQSOSC(V,T) = Runtime / 2 * Count
5.
6.
7.
8.
The input stimulus for tDQS2DQ will be consistent over voltage and temp conditions.
The OSCoffset is the average difference of the endpoints across voltage and temp.
These parameters are defined per channel.
tDQS2DQ(V,T) delay will be the average of DQS to DQ delay over the runtime period.
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4.28.2. DQS Interval Oscillator Readout Timing
OSC Stop to its counting value readout timing is shown in following figures:
Figure - In case of DQS Interval Oscillator is stopped by MPC Command
T0
T1
T2
Valid
Valid
T3
T4
T5
Ta0
Ta1
Ta2
Valid
Valid
Ta3
Ta4
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
Valid
Valid
Valid
Valid
Tb6
CK_c
CK_t
CKE
CS
CA
COMMAND
DES
MPC :Start
MR Write-2
DQS
Oscillator
DES
DES
DES
DES
MPC :Stop
DQS Oscillator
DES
DES
DES
MRR-1
MR18/MR19
DES
CAS-2
tOSCO
TIME BREAK
DON'T CARE
NOTES : 1. DQS interval timer run time setting : MR23 OP[7:0] = 00000000
2. DES commands are shown for ease of illustration; other commands may be valid at these times.
Figure - In case of DQS Interval Oscillator is stopped by DQS interval timer
T0
T1
T2
Valid
Valid
T3
T4
T5
Ta0
Ta1
Ta2
Ta3
Ta4
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
Valid
Valid
Valid
Valid
Tb6
CK_c
CK_t
CKE
CS
CA
COMMAND
DES
MPC :Start
MR Write-2
DQS
Oscillator
DES
DES
DES
DES
DES
DES
DES
DES
See Note 2
NOTES : 1. DQS interval timer run time setting : MR23 OP[7:0] 00000000
2. Setting counts of MR23
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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DES
DES
MRR-1
MR18/MR19
CAS-2
tOSCO
DON'T CARE
TIME BREAK
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4.29. Read Preamble Training
LPDDR4 READ Preamble Training is supported through the MPC function.
This mode can be used to train or read level the DQS receivers. Once READ Preamble Training is enabled by MR13[OP1]
= 1, the LPDDR4 DRAM will drive DQS_t LOW, DQS_c HIGH within tSDO and remain at these levels until an MPC DQ
READ Training command is issued.
During READ Preamble Training the DQS preamble provided during normal operation will not be driven by the DRAM.
Once the MPC DQ READ Training command is issued, the DRAM will drive DQS_t/DQD_c like a normal READ burst after
RL. DRAM may or may not drive DQ[15:0] in this mode.
While in READ Preamble Training Mode, only READ DQ Calibration commands may be issued.
•Issue an MPC [RD DQ Calibration] command followed immediately by a CAS-2 command.
• Each time an MPC [RD DQ Calibration] command followed by a CAS-2 is received by the LPDDR4 SDRAM, a 16-bit
data burst will, after the currently set RL, drive the eight bits programmed in MR32 followed by the eight bits programmed in MR40 on all I/O pins.
• The data pattern will be inverted for I/O pins with a '1' programmed in the corresponding invert mask mode register
bit.
• Note that the pattern is driven on the DMI pins, but no data bus inversion function is enabled, even if Read DBI is
enabled in the DRAM mode register.
• This command can be issued every tCCD seamlessly.
• The operands received with the CAS-2 command must be driven LOW.
READ Preamble Training is exited within tSDO after setting MR13[OP1] = 0.
Figure - Read Preamble Training
T4
Ta0
Ta1
COMMAND MRW-1 MRW-1 MRW-2 MRW-2 DES
DES
DES
T0
T1
T2
T3
Ta2
Ta3
Ta4
Ta4
Ta6
Tb0
Tb1
Tc0
Tc1
Tc2
Tc3
Tc4
Td0
Td4
Te0
Te1
DES
DES
DES
DES
DES
DES
DES
DES
DES MRW-1 MRW-1 MRW-2 MRW-2 DES
DES
DES
Td1
Td2
Td3
Td4
CK_c
CK_t
CS
MPC-1 MPC-1
RD Cal. RD Cal. CAS-2 CAS-2
tSDO
RL
tDQSCK
tSDO
Read Preamble Training Mode = Enable: MR13[OP1] = 1
Read Preamble Training Mode = Disable: MR13[OP1] = 0
DQS_c
DQS_t
tDQSQ
DQ
DQ (High-Z or Driven )
Note
1. Read DQ Calibration supports only BL16 operation
Rev 1.1 / Sep 2016 / SK hynix Confidential
Dout Dout Dout Dout Dout Dout
n0 n1 n12 n13 n14 n15
DQ (High-Z or Driven )
TIME BREAK
High-Z
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4.30. Multi Purpose Command (MPC)
LPDDR4-SDRAMs use the MPC command to issue a NOP and to access various training modes. The MPC command is
initiated with CS, and CA[5:0] asserted to the proper state at the rising edge of CK, as defined by the Command Truth
Table. The MPC command has seven operands (OP[6:0]) that are decoded to execute specific commands in the SDRAM.
OP[6] is a special bit that is decoded on the first rising CK edge of the MPC command. When OP[6]=0 then the SDRAM
executes a NOP (no operation) command, and when OP[6]=1 then the SDRAM further decodes one of several training
commands.
When OP[6]=1 and when the training command includes a Read or Write operation, the MPC command must be followed immediately by a CAS-2 command. For training commands that Read or Write the SDRAM, read latency (RL) and
write latency (WL) are counted from the second rising CK edge of the CAS-2 command with the same timing relationship
as any normal Read or Write command. The operands of the CAS-2 command following a MPC Read/Write command
must be driven LOW. The following MPC commands must be followed by a CAS-2 command:
- Write FIFO
- Read FIFO
- Read DQ Calibration
All other MPC commands do not require a CAS-2 command, including:
-
NOP
Start DQS Interval Oscillator
Stop DQS Interval Oscillator
Start ZQ Calibration
Latch ZQ Calibration
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Table - MPC Command Definition
SDR Command Pins (2)
Command
CKE
CK_t(n-1)
CK_t(n)
H
H
Multi Purpose Command
(MPC)
Function
Operand
Training Modes
OP[6:0]
DDR CA Pins (10)
CS_n
CA0
CA1
CA2
CA3
CA4
CA5
H
L
L
OP0
L
OP1
L
OP2
L
OP3
L
OP4
OP6
OP5
Data
0XXXXXXB: NOP
1000001B: RD FIFO
1000011B: RD DQ Calibration (MR32/MR40)
1000101B: RFU
1000111B: WR FIFO
1001001B: RFU
1001011B: Start DQS Osc
1001101B: Stop DQS Osc
1001111B: ZQCal Start
1010001B: ZQCal Latch
All Others: Reserved
CK_t
edge
Notes
R1
1,2
R2
Notes
1,2,3,4
Notes:
1. See command truth table for more information
2. MPC commands for Read or Write training operations must be immediately followed by CAS-2 command consecutively without
any other commands in between. MPC command must be issued first before issuing the CAS-2 command.
Figure - MPC [WR FIFO] Operation
CK_t
CK_c
tCCD
tWRWTR
CA
Write
Write
CAS-2
CAS-2
VALID
VALID
MPC
MPC
CAS-2
CAS-2
VALID
VALID
MPC
MPC
CAS-2
CAS-2
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
WL
CMD
Write-1
CAS-2
VALID
MPC
CAS-2
Write FIFO
VALID
WL
MPC
Write FIFO
CAS-2
tDQSS
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
tDQSS
DQS_t
DQS_c
tWPRE
tDQS2DQ
tDQS2DQ
DQ[15:0]
D0 D1 D2 D7 D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D15
DM[1:0]
Notes:
1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. Write-1 to MPC is shown as an example of command-to-command timing for MPC. Timing from Write-1 to MPC [WR-FIFO] is
tWRWTR.
3. Seamless MPC [WR-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC [WR-FIFO] uses the same command-to-data timing relationship (WL, tDQSS, tDQS2DQ) as a Write-1 command.
5. A maximum of 5 MPC [WR-FIFO] commands may be executed consecutively without corrupting FIFO data. The 6th MPC [WRFIFO] command will overwrite the FIFO data from the first command. If fewer than 5 MPC [WR-FIFO] commands are executed,
then the remaining FIFO locations will contain undefined data.
6. For the CAS-2 command following a MPC command, the CAS-2 operands must be driven “LOW.”
7. To avoid corrupting the FIFO contents, MPC [RD-FIFO] must immediately follow MPC [WR-FIFO]/CAS-2 without any other command disturbing FIFO pointers in-between. FIFO pointers are disturbed by CKE Low, Write, Masked Write, Read, Read DQ Calibration and MRR. See Write Training session for more information on FIFO pointer behavior.
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Figure - MPC [RD FIFO] Read Operation
(Shown with tWPRE=2nCK, tWPST=0.5nCK, tRPRE=toggling, tRPST=1.5nCK)
CK_t
CK_c
tCCD
CA
VALID
VALID
MPC
CMD
Write FIFO
VALID
VALID
VALID
CAS-2
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
MPC
VALID
VALID
CAS-2
Read FIFO
VALID
VALID
VALID
VALID
VALID
MPC
Read FIFO
VALID
VALID
CAS-2
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
WL
tWTR
tDQSS
tDQSCK
RL
DQS_t
DQS_c
tDQS2DQ
tWPRE
tRPRE
tRPST
DQ[15:0]
D0 D1 D2 D15 D4 D13 D14 D15
D0 D13 D14 D15
DM[1:0]
Notes:
1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. MPC [WR FIFO] to MPC [RD FIFO] is shown as an example of command-to-command timing for MPC.
3. Seamless MPC [RD-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC [RD-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK) as a Read-1 command.
5. Data may be continuously read from the FIFO without any data corruption. After 5 MPC [RD-FIFO] commands the FIFO pointer
will wrap back to the 1st FIFO and continue advancing. If fewer than 5 MPC [WR-FIFO] commands were executed, then the MPC
[RD-FIFO] commands to those FIFO locations will return undefined data. See the Write Training section for more information on
the FIFO pointer behavior.
6. For the CAS-2 command immediately following a MPC command, the CAS-2 operands must be driven “LOW.”
7. DMI[1:0] signals will be driven if any of WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training section for
more information on DMI behavior.
Figure - MPC [RD FIFO] Operation
(Shown with tRPRE=toggling, tRPST=1.5nCK)
CK_t
CK_c
tRTRRD
CA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
RL
CMD
MPC
Read FIFO
CAS-2
VALID
VALID
RL
Read
CAS-2
VALID
VALID
VALID
tDQSCK
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
tDQSCK
DQS_t
DQS_c
tRPRE
tRPST
tRPRE
tRPST
DQ[15:0]
D0 D1 D2 D3 D4 D13 D14 D15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
DM[1:0]
Notes:
1. MPC [RD FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. MPC [RD-FIFO] to Read-1 Operation is shown as an example of command-to-command timing for MPC. Timing from MPC [RDFIFO] command to Read is tRTRRD.
3. Seamless MPC [RD-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC [RD-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK) as a Read-1 command.
5. Data may be continuously read from the FIFO without any data corruption. After 5 MPC [RD-FIFO] commands the FIFO pointer
will wrap back to the 1st FIFO and continue advancing. If fewer than 5 MPC [WR-FIFO] commands were executed, then the MPC
[RD-FIFO] commands to those FIFO locations will return undefined data. See the Write Training section for more information on
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the FIFO pointer behavior.
6. For the CAS-2 command immediately following a MPC command, the CAS-2 operands must be driven “LOW.”
7. DMI[1:0] signals will be driven if any of WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training section for
more information on DMI behavior.
Table - Timing Constraints for Training Commands
Previous
Command
WR/MWR
RD/MRR
MPC
[WR FIFO]
MPC
[RD FIFO]
MPC
[RD DQ Calibration]
Next Command
Minimum Delay
MPC [WR FIFO]
MPC [RD FIFO]
MPC [RD DQ Calibration]
MPC [WR FIFO]
MPC [RD FIFO]
MPC[RD DQ Calibration]
WR/MWR
MPC [WR FIFO]
RD/MRR
MPC [RD FIFO]
MPC [RD DQ Calibration]
WR/MWR
MPC [WR FIFO]
RD/MRR
MPC [RD FIFO]
MPC [RD DQ Calibration]
WR/MWR
MPC [WR FIFO]
RD/MRR
MPC [RD FIFO]
MPC [RD DQ Calibration]
tWRWTR
Not Allowed
WL+RU(tDQSS(max)/tCK)+BL/2+RU(tWTR/tCK)
tRTW
Not Allowed
tRTRRD
Not Allowed
tCCD
Not Allowed
WL+RU(tDQSS(max)/tCK)+BL/2+RU(tWTR/tCK)
Not Allowed
tRTW
tRTW
tRTRRD
tCCD
tRTRRD
tRTW
tRTW
tRTRRD
Not Allowed
tCCD
Unit Notes
nCK
nCK
nCK
nCK
1
2
4
2
3
2
nCK
2
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
2
4
4
3
3
4
4
3
2
nCK
Notes:
1. tWRWTR = WL + BL/2 + RU(tDQSS(max)/tCK) + max(RU(7.5ns/tCK), 8nCK)
2. No commands are allowed between MPC [WR FIFO] and MPC [RD FIFO] except MRW commands related to training parameters.
3. tRTRRD = RL + RU(tDQSCK(max)/tCK) + BL/2 + RD(tRPST) + max(RU(7.5ns/tCK),8nCK)
4. tRTW (DQ ODT Disabled case; MR11 OP[2:0]=000b)
= RL + RU(tDQSCK(max)/tCK) + BL/2 - WL + tWPRE + RD(tRPST)
tRTW (DQ ODT Enabled case; MR11 OP[2:0]≠000b)
= RL + RU(tDQSCK(max)/tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon,min/tCK) + 1
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4.31. Temperature Sensor
LPDDR4 devices feature a temperature sensor whose status can be read from MR4. This sensor can be used to determine an appropriate refresh rate, determine whether AC timing de-rating is required in the elevated temperature range,
and/or monitor the operating temperature. Either the temperature sensor or the device TOPER may be used to determine whether operating temperature requirements are being met.
LPDDR4 devices shall monitor device temperature and update MR4 according to tTSI. Upon exiting self-refresh or power-down, the device temperature status bits shall be no older than tTSI.
When using the temperature sensor, the actual device case temperature may be higher than the TOPER specification
that applies for the standard or elevated temperature ranges. For example, TCASE may be above 85oC when MR4[2:0]
equals ‘b011. LPDDR4 devices shall allow for 2oC temperature margin between the point at which the device updates
the MR4 value and the point at which the controller re-configures the system accordingly. In the case of tight thermal
coupling of the memory device to external hot spots, the maximum device temperature might be higher than what is
indicated by MR4.
To assure proper operation using the temperature sensor, applications should consider the following factors:
• TempGradient is the maximum temperature gradient experienced by the memory device at the temperature of interest
over a range of 2oC.
• ReadInterval is the time period between MR4 reads from the system.
• TempSensorInterval (tTSI) is maximum delay between internal updates of MR4.
• SysRespDelay is the maximum time between a read of MR4 and the response by the system.
In order to determine the required frequency of polling MR4, the system shall use the maximum TempGradient and the
maximum response time of the system using the following equation:
TempGradient x (ReadInterval + tTSI + SysRespDelay)
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