200ball FBGA Specification
64Gb LPDDR4X (x8, 2 Channel, 2 CS)
H9HCNNNFAMMLXR-NEE
This document is a general product description and is subject to change without notice. SK hynix does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
1
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
Revision History
Version
0.1
1.0
1.1
1.2
Description
-
Initial Release
Updated IDD Specification
Modified FBGA package ball size typo
Update JEDEC Specificaion
Rev 1.2 / Mar. 2020 / SK hynix Confidential
Date
Remark
Dec 2019
Feb 2020
Mar 2020
Mar 2020
Preliminary
2
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
Ordering Information
Part Number
Mode
H9HCNNNFAMMLXR-NEE
Operation
Voltage
LPDDR4X 1.8V/1.1/0.6
Density
Speed
Package
Operating
Temperature
64Gb
(x8, 2 Channel)
DDR4 4266
200Ball FBGA
(Lead & Halogen Free)
-25oC ~ 85oC
H9HCNNNF AMMLXR-NEE
SK Hynix Memory
FBGA
Operating
Temperature
Product Mode :
LPDDR4
DRAM Speed
Density, Stack, Block Size
& Page Buffer for NVM1) :
None
Voltage & I/O for NVM :
None
Density, Stack, CH & CS for DRAM :
64Gb, ODP, 2Ch 2CS
NAND Speed : none
Package Material :
Lead & Halogen Free
Package Type :
FBGA 200 Ball
Generation : 1st
Voltage, I/O & Option for DRAM :
1.1v/0.6, x8, LPDDR4X
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
Functional Block Diagram
CS0_A, CKE0_A, ODT_A
CS1_A, CKE1_A
Channel A
Channel A
Channel A
Channel A
8Gb x8
(1G x8)
8Gb x8
(1G x8)
8Gb x8
(1G x8)
8Gb x8
(1G x8)
DQ[7:0]_A, ZQ0_A
DQ[15:8]_A, ZQ0_A
DQS[1:0]_t_A/DQS[1:0]_c_A, DMI[1:0]_A, CA[5:0]_A, CLK_A, Reset_n
DQS[1:0]_t_B/DQS[1:0]_c_B, DMI[1:0]_B, CA[5:0]_B, CLK_B, Reset_n
DQ[7:0]_B
DQ[15:8]_B
Channel B
Channel B
Channel B
Channel B
8Gb x8
(1G x8)
8Gb x8
(1G x8)
8Gb x8
(1G x8)
8Gb x8
(1G x8)
CS1_B, CKE1_B
CS0_B, CKE0_B, ODT_B
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1. FEATURES
[ LPDDR4X ]
·
·
·
·
·
·
·
VDD1 = 1.8V (1.7V to 1.95V)
VDD2 = 1.1V (1.06V to 1.17V)
VDDQ = 0.6V (0.57V to 0.65V)
Programmable CA ODT and DQ ODT with VSSQ termination
VOH compensated output driver
Single data rate command and address entry
Double data rate architecture for data Bus;
- two data accesses per clock cycle
· Differential clock inputs (CK_t, CK_c)
· Bi-directional differential data strobe (DQS_t, DQS_c)
· DMI pin support for write data masking and DBIdc functionality
· Programmable RL (Read Latency) and WL (Write Latency)
· Burst length: 16 (default), 32 and On-the-fly
- On the fly mode is enabled by MRS
· Auto refresh and self refresh supported
· All bank auto refresh and directed per bank auto refresh supported
· Auto TCSR (Temperature Compensated Self Refresh)
· PASR (Partial Array Self Refresh) by Bank Mask and Segment Mask
· Background ZQ Calibration
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
2. Package ballout & Addressing
2.1. FBGA package
2.1.1. 200 balls, 10.00x15mm2, 0.8 x 0.65mm pitch
8
9
10
11 12
ZQ0
ZQ1
VDDQ
VDDQ
VDD2
VSS
DNU
DNU
DQ15
a
VDDQ
DQ8
a
DNU
VSS
B
VSS
DQ14
a
DMI1
a
DQ9
a
VSS
C
VSS
VDDQ
VDDQ
VSS
DQS1_t
a
DQS0_c
a
VSS
VDDQ
D
DQ5
a
VSS
VSS
DQ13
a
DQS1_c
a
DQ10
a
VSS
DQ3
a
E
VDDQ
DQ4
a
VDD2
VDD2
DQ12
a
VDDQ
DQ11
a
VDD1
F
VSS
ODT
a
VSS
VDD1
VSS
VSS
VDD1
VSS
NC
VSS
G
H
VDD2
CA0
a
CS1
a
CS0
a
VDD2
VDD2
CA2
a
CA3
a
CA4
a
VDD2
H
J
VSS
CA1
a
VSS
CKE0
a
CKE1
a
CK_t
a
CK_c
a
VSS
CA5
a
VSS
J
K
VDD2
VSS
VDD2
VSS
NC
NC
VSS
VDD2
VSS
VDD2
K
1
2
3
4
A
DNU
B
DNU
DNU
VSS
VDD2
DQ0
a
VDDQ
DQ7
a
C
VSS
DQ1
a
DMI0
a
DQ6
a
D
VDDQ
VSS
DQS0_t
a
E
VSS
DQ2
a
F
VDD1
G
5
6
7
A
L
L
M
M
N
VDD2
VSS
VDD2
VSS
NC
NC
VSS
VDD2
VSS
VDD2
P
VSS
CA1
b
VSS
CKE0
b
CKE1
b
CK_t
b
CK_c
b
VSS
CA5
b
VSS
P
R
VDD2
CA0
b
CS1
b
CS0
b
VDD2
VDD2
CA2
b
CA3
b
CA4
b
VDD2
R
T
VSS
ODT
b
VSS
VDD1
VSS
VSS
VDD1
VSS
RESET
VSS
T
U
VDD1
DQ3
b
VDDQ
DQ4
b
VDD2
VDD2
DQ12
b
VDDQ
DQ11
b
VDD1
U
V
VSS
DQ2
b
DQ5
b
VSS
VSS
DQ13
b
DQ10
b
VSS
V
W
VDDQ
VSS
VSS
VDDQ
VDDQ
VSS
VSS
VDDQ
W
DMI0
b
DQ6
b
DMI1
b
DQ9
b
N
Y
VSS
DQ1
b
VSS
VSS
DQ14
b
VSS
Y
AA
DNU
DQ0
b
VDDQ
DQ7
b
VDDQ
VDDQ
DQ15
b
VDDQ
DQ8
b
DNU
AA
AB
DNU
DNU
VSS
VDD2
VSS
VSS
VDD2
VSS
DNU
DNU
AB
1
2
3
4
5
8
9
10
11 12
6
7
200ball LPDDR4 (2CH) only
LPDDR4 Channel a
LPDDR4 Channel b
Power (VDD1,VDD2,VDDCA,VDDQ,VREF)
Ground (VSS,VSSCA,VSSQ)
Notes:
1. 0.8mm pitch (X-axis), 0.65mm pitch (Y-axis), 22 rows
2. Top View, A1 in top left corner
3. ODT_CA_[x] balls are wired to ODT_CA)_[x] pads of Rank 0 DRAM die. The ODT input to other rank (if present) will be connected to VSS in the
package.
4. ZQ2, CKE2_A, CKE2_B, CS2_A, and CS2_B balls are reserved for 3-rank package. For 1-rank and 2-rank package those balls are NC
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
2.2. Mechanical specification
200 Ball 0.65/0.80mm pitch 10.00mm x 15.00mm FBGA [t = 1.00mm max]
0.800 x 11 = 8.800
A1 INDEX MARK
0.800
0.600 ± 0.100
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
0.650 x 21 = 13.650
15.000 ± 0.100
J
K
N
0.650
L
M
P
R
T
U
V
W
Y
AA
200 x Ø 0.300 ± 0.050
(Post Reflow Ø 0.320 ± 0.050)
0.675 ± 0.100
AB
10.000 ± 0.100
Ø0.15 M C A B
0.220 ± 0.050
0.900 ± 0.100
Bottom View
SEATING PLANE
C
0.10 C
Front View
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
Pin Description.
Symbol
Type
Description
CK_t_A, CK_c_A
CK_t_B, CK_c_B
Input
Clock : CK_t and CK_c are differential clock inputs. All address, command, and control input
signals are sampled on the crossing of the positive edge of CK_t and the negative edge of
CK_c. AC timings for CA parameters are referenced to CK. Each channel (A & B) has its own
clock pair.
CKE_A
CKE_B
Input
Clock Enable : CKE HIGH activates and CKE LOW deactivates the internal clock circuits, input
buffers, and output drivers. Power-saving modes are entered and exited via CKE transitions.
CKE is part of the command code. Each channel (A & B) has its own CKE signal.
CS_A
CS_B
Input
Chip Select : CS is part of the command code. Each channel (A & B) has its own CS signal.
CA[5:0]_A,
CA[5:0]_B
Input
Command / Address Inputs : Provide the Command and Address inputs according to the
Command Truth Table. Each channel (A&B) has its own CA signals.
ODT_CA_A
ODT_CA_B
Input
CA ODT Control : The ODT_CA pin is ignored by LPDDR4x devices. ODT-CS /CA/CK function is
fully controlled through MR11 and MR22. The ODT_CA pin shall be connected to either VDD2 or
VSS
DQ[15:0]_A,
DQ[15:0]_B
I/O
Data Input / Output : Bi-direction data bus.
I/O
Read Strobe : DQS_t and DQS_c are bi-directional differential output clock signals used to
strobe data during a READ or WRITE. The Data Strobe is generated by the DRAM for a READ
and is edge-aligned with Data. The Data Strobe is generated by the Memory Controller for a
WRITE and is center aligned with Data. Each byte of data has a Data Strobe signal pair.
Each channel (A & B) has its own DQS strobes.
I/O
Data Mask Inversion : DMI is a bi-directional signal which is driven HIGH when the data on
the data bus is inverted, or driven LOW when the data is in its normal state. Data Inversion can
be disabled via a mode register setting. Each byte of data has a DMI signal. Each channel (A &
B) has its own DMI signals. This signal is also used along with the DQ signals to provide write
data masking information to the DRAM. The DMI pin function - Data Inversion or Data mask depends on Mode Register setting.
DQS[1:0]_t_A,
DQS[1:0]_c_A,
DQS[1:0]_t_B,
DQS[1:0]_c_B
DMI[1:0]_A,
DMI[1:0]_B
ZQ
Calibration Reference : Used to calibrate the output drive strength and the termination
Reference resistance. There is one ZQ pin per die. The ZQ pin shall be connected to VDDQ through a 240Ω ± 1% resistor.
VDD1, VDD2, VDDQ
Supply
Power Supplies : Isolated on the die for improved noise immunity.
VSS
GND
Ground Reference : Power supply ground reference.
RESET_n
Input
RESET : When asserted LOW, the RESET pin resets both channels of the die.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1. Functional Description
LPDDR4-SDRAM is a high-speed synchronous DRAM device internally configured as an 2-channel memory with 8-bank memory per
each channel.
Single-channel SDRAM devices contain the following number of bits:
1Gb has 1,073,741,824 bits
2Gb has 2,147,483,648 bits
3Gb has 3,221,225,472 bits
4Gb has 4,294,967,296 bits
6Gb has 6,442,450,944 bits
8Gb has 8,589,934,592 bits
12Gb has 12,884,901,888 bits
16Gb has 17,179,869,184 bits
Dual-channel SDRAM devices contain the following number of bits:
2Gb has 2,147,483,648 bits
4Gb has 4,294,967,296 bits
6Gb has 6,442,450,944 bits
8Gb has 8,589,934,592 bits
12Gb has 12,884,901,888 bits
16Gb has 17,179,869,184 bits
24Gb has 25,769,803,776 bits
32Gb has 34,359,738,368 bits
LPDDR4 devices use multi cycle of single data rate architecture on the Command/Address (CA) bus to reduce the number of input
pins in the system. The 6-bit CA bus contains command, address and bank information. Each command uses two clock cycles, during
which command information is transferred on positive edge of the corresponding clock.
These devices also use a double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially an 16n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the
I/O pins. A single read or write access for the LPDDR4 SDRAM effectively consists of a single 16n-bit wide, one clock cycle data transfer at the internal DRAM core and sixteen corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the LPDDR4 SDRAMs are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Activate command, which is
then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to
select the row and the bank to be accessed. The address bits registered coincident with the Read or Write command are used to
select the bank and the starting column location for the burst access.
Prior to normal operation, the LPDDR4 SDRAM must be initialized. The following section provides detailed information covering
device initialization, register definition, command description and device operation.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.1. LPDDR4 SDRAM Addressing
LPDDR4 SDRAM x16 Mode
Memory Density
(per Die)
4Gb
6Gb
8Gb
12Gb
16Gb
Memory Density
(per channel)
2Gb
3Gb
4Gb
6Gb
8Gb
Configuration
16 Mb x 16 DQ
x 8 banks
x 2 channels
24 Mb x 16 DQ
x 8 banks
x 2 channels
32 Mb x 16 DQ
x 8 banks
x 2 channels
48Mb x 16DQ
x 8 banks
x 2 channels
64 Mb x 16 DQ
x 8 banks
x 2 channels
Number of Channels per
die
2
2
2
2
2
Number of Banks per
Channel
8
8
8
8
8
Array Pre-fetch
(bits, per channel)
256
256
256
256
256
Number of Rows per
Channel
16,384
24,576
32,768
49,152
65,536
Number of Columns
(fetch boundaries)
64
64
64
64
64
Page Size (Bytes)
2048
2048
2048
2048
2048
Channel Density
(Bits per channel)
2,147,483,648
3,221,225,472
4,294,967,296
6,442,450,944
8,589,934,592
Total Density
(Bits per die)
4,294,967,296
6,442,450,944
8,589,934,592
12,884,901,888
17,179,869,184
Bank Address
BA0 - BA2
BA0 - BA2
BA0 - BA2
BA0 - BA2
BA0 - BA2
Row Addresses
R0 - R13
R0 – R14
(R13=0 when
R14=1)
R0 - R14
R0 – R15
(R14=0 when
R15=1)
R0 - R15
Column
Addresses
C0 - C9
C0 - C9
C0 - C9
C0 - C9
C0 - C9
64-bit
64-bit
64-bit
64-bit
64-bit
x16
Burst Starting Address
Boundary
Notes
1. The lower two column addresses (C0-C1) are assumed to be “zero” and are not transmitted on the CA bus.
2. Row and Column address values on the CA bus that are not used for a particular density be at valid logic levels.
3. For non-binary memory densities, only half of the row address space is valid. When the MSB address bit is “HIGH”,
then the MSB-1 address bit must be “LOW”.
4. The row address input which violates restriction described in note 3 in this table may result in undefined one.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
LPDDR4 SDRAM x8 Mode
Memory Density
(per Die)
4Gb
6Gb
8Gb
12Gb
16Gb
Memory Density
(per channel)
2Gb
3Gb
4Gb
6Gb
8Gb
Configuration
32 Mb x 8 DQ
x 8 banks
x 2 channels
48 Mb x 8 DQ
x 8 banks
x 2 channels
64 Mb x 8 DQ
x 8 banks
x 2 channels
96 Mb x 8DQ
x 8 banks
x 2 channels
128 Mb x 8 DQ
x 8 banks
x 2 channels
Number of Channels per
die
2
2
2
2
2
Number of Banks per
Channel
8
8
8
8
8
Array Pre-fetch (bits,
per channel)
256
256
256
256
256
Number of Rows per
Channel
32,768
49,152
65,536
98,304
131,072
Number of Columns
(fetch boundaries)
64
64
64
64
64
Page Size (Bytes)
1024
1024
1024
1024
1024
Channel Density (Bits
per channel)
2,147,483,648
3,221,225,472
4,294,967,296
6,442,450,944
8,589,934,592
Total Density (Bits per
die)
4,294,967,296
6,442,450,944
8,589,934,592
12,884,901,888
17,179,869,184
Bank Address
BA0 - BA2
BA0 - BA2
BA0 - BA2
BA0 - BA2
BA0 - BA2
Row Addresses
R0 - R14
R0 – R15
(R14=0 when
R15=1)
R0 - R15
R0 – R16
(R15=0 when
R16=1)
R0 - R16
Column
Addresses
C0 - C9
C0 - C9
C0 - C9
C0 - C9
C0 - C9
64-bit
64-bit
64-bit
64-bit
64-bit
x8
Burst Starting Address
Boundary
Notes
1. The lower two column addresses (C0-C1) are assumed to be “zero” and are not transmitted on the CA bus.
2. Row and Column address values on the CA bus that are not used for a particular density be at valid logic levels.
3. For non-binary memory densities, only half of the row address space is valid. When the MSB address bit is “HIGH”,
then the MSB-1 address bit must be “LOW”.
4. The row address input which violates restriction described in note 3 in this table may result in undefined one.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.2. Simplified State Diagram
The state diagram provides a simplified illustration of the bus interface, supported state transitions, and the commands that control
them. For a complete description of device behavior, use the information provided in the state diagram with the truth tables and timing specifications. The truth tables describe device behavior and applicable restrictions when considering the actual state of all
banks. For command descriptions, see the Commands and Timing section.
Automatic sequence
Command sequence
From any state Reset_n = L
Power-on
Reset_n
=L
SREF
Power
Down
L
E
=
H
MR
W
se
t_
n
=
MPC
Re
=
CK
M
RW
MPC
E
CK
H
MPC
SREF
Self
Refresh
R
MR
MR
PD
W
PD
X
R
Idle
Power
Down
WR or
MWR
E
MR
Read
MRR
Per bank
Refresh
REF
RD
WR
Write or
Masked
Write
Write or
Masked Write
w/ auto
precharge
W
Bank
Active
MPC
WRA or
MWRA
MR
WRA or
MWRA
RD
WRA or
MWRA
Read
PRE, PRA
PRE(A) = Precharge (All)
ACT = Activate
WR(A) = Write (with auto precharge)
MWR(A) = Masked Write
(with auto precharge)
RD(A) = Read (with auto precharge)
MRW = Mode Register Write
MRR = Mode Register Read
PDE = Power Down Entry
PDX = Power Down Exit
SREF = Self Refresh Entry
SRX = Self Refresh Exit
REF = Refresh
MPC = Multi Purpose Command
MR
Read
Command
Bus
Training
MR
Write
PD
X
M
or
MPC
based
training
MR Read
PD
WR
MRR
MR
Write
W
W
Active
Power
Down
MPC
based
training
MPC
All bank
Refresh
MR
Read
ACT
MR
Write
MR
MR
MR Read
MRW
REF
Idle
SRX
MRR
MRW
Per bank
Refresh
F
RE
MR
W
MR
MPC
based
training
MR
Write
MPC
based
training
Reset
Command
Bus
Training
MPC
based
training
RDA
PRE, PRA
PRE, PRA
Read
with autoprecharge
Precharging
Figure 1 - Simplified State Diagram
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
Automatic sequence
a) FIFO based Write/Read Timing
Command sequence
MPC
MPC
based
training
MPC
MPC
FIFO
WRTR
MPC
b) Read DQ Calibration
MPC
MPC
FIFO
RDTR
MPC
RD DQ
Calibration
MRW
MPC
MRW
MRW
c) ZQ Cal Start
MPC
d) ZQ Cal Latch
ZQ Cal
Start
MPC
ZQ Cal
Latch
Figure 2 - Simplified Bus Interface State Diagram
Notes
1. From the Self-Refresh state the device can enter Power-Down, MRR, MRW, or MPC states. See the section on Self-Refresh for
more information.
2. In IDLE state, all banks are pre-charged.
3. In the case of a MRW command to enter a training mode, the state machine will not automatically return to the IDLE state at
the conclusion of training. See the applicable training section for more information.
4. In the case of a MPC command to enter a training mode, the state machine may not automatically return to the IDLE state at
the conclusion of training. See the applicable training section for more information.
5. This simplified State Diagram is intended to provide an overview of the possible state transitions and the commands to control
them. In particular, situations involving more than one bank, the enabling or disabling of on-die termination, and some other
events are not captured in full detail.
6. States that have an “automatic return” and can be accessed from more than one prior state (Ex. MRW from either Idle or Active
states) will return to the state from when they were initiated (Ex. MRW from Idle will return to Idle).
7. The RESET_n pin can be asserted from any state, and will cause the SDRAM to go to the Reset State. The diagram shows RESET
applied from the Power-On as an example, but the Diagram should not be construed as a restriction on RESET_n.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.3. Power-up and Initialization
For power-up and reset initialization, in order to prevent DRAM from functioning improperly, default values of the following MR settings are defined as following table.
Table 1 - MRS defaults settings
Item
MRS
Default setting
Description
FSP-OP/WR
MR13 OP[7:6]
00B
FS-OP/WR[0] are enabled
WLS
MR2 OP[6]
0B
Write Latency Set 0 is selected
WL
MR2 OP[5:3]
000B
WL = 4
RL
MR2 OP[2:0]
000B
RL = 6, nRTP = 8
nWR
MR1 OP[6:4]
000B
nWR = 6
DBI-WR/RD
MR3 OP[7:6]
00B
Write & Read DBI are disabled
CA ODT
MR11 OP[6:4]
000B
CA ODT is disabled
DQ ODT
MR11 OP[2:0]
000B
DQ ODT is disabled
VREF(CA) Setting
MR12 OP[6]
1B
VREF(CA) Range[1] enabled
VREF(CA) value
MR12 OP[5:0]
011101B
Range1: 50.3% of VDDQ
VREF(DQ) Setting
MR14 OP[6]
1B
VREF(DQ) Range[1] enabled
VREF(DQ) Value
MR14 OP[5:0]
011101B
Range1: 50.3% of VDDQ
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.3.1. Voltage Ramp and Device Initialization
The following sequence shall be used to power up the LPDDR4 device. Unless specified otherwise, these steps are mandatory. Note
that the power-up sequence of all channels must proceed simultaneously.
1. While applying power (after Ta), RESET_n is recommended to be LOW (≤0.2 x VDD2) and all inputs must be between VILmin
and VIHmax. The device outputs remain at High-Z while RESET_n is held LOW. Power supply voltage ramp requirements are
provided in Table "Voltage Ramp Conditions". VDD1 must ramp at the same time or earlier than VDD2. VDD2 must ramp at the
same time or earlier than VDDQ.
Table 2 - Voltage Ramp Conditions
After
Applicable Conditions
VDD1 must be greater than VDD2
Ta is reached
VDD2 must be greater than VDDQ - 200mV
Notes
1. Ta is the point when any power supply first reaches 300mV.
2. Voltage ramp conditions in above table apply between Ta and power-off (controlled or uncontrolled).
3. Tb is the point at which all supply and reference voltages are within their defined ranges.
4. Power ramp duration tINIT0 (Tb-Ta) must not exceed 20ms.
5. The voltage difference between any of VSS and VSSQ pins must not excess 100mV.
2. Following the completion of the voltage ramp (Tb), RESET_n must be maintained LOW. DQ, DMI, DQS_t and DQS_c voltage
levels must be between VSSQ and VDDQ during voltage ramp to avoid latch-up. CKE, CK_t, CK_c, CS_n and CA input levels must
be between VSS and VDD2 during voltage ramp to avoid latch-up.
3. Beginning at Tb, RESET_n must remain LOW for at least tINIT1(Tc), after which RESET_n can be deasserted to HIGH(Tc).
At least 10ns before RESET_n de-assertion, CKE is required to be set LOW. All other input signals are "Don't Care".
Ta
Tb
Tc
R eset
Td
Te
Tf
Tg
Th
I n it ia liz a t io n
Ti
Tj
Tk
T r a in in g
t I N I T 4 = 5 t C K ( m in )
CK_c
CK_t
tIN IT 0
= 2 0m s(m ax)
t I N I T 1 = 2 0 0 u s ( m in )
S u p p lie s
R e se t_ n
tIN IT 2
t I N I T 3 = 2 m s ( m in )
= 1 0 n s ( m in )
CKE
tZ Q C A L
= 1 m s ( m in )
t I N I T 5 = 2 u s ( m in )
C A [5 :0 ]
CS
E x it P D
DQs
DES
MRW
MRR
DES
ZQ Cal
S ta rt
DES
tZ Q L A T
= m a x ( 3 0 n s , 8 t C K ) ( m in )
ZQ C al
L a tc h
DES
CBT
V a lid
DES
W r it e
L e v e lin g
V a lid
DES
DQ
T r a in in g
DES
V a lid
V a lid
Figure 3 - Power Ramp and Initialization Sequence
Notes
1. Training is optional and may be done at the system architects discretion. The training sequence after ZQ_CAL Latch (Th, Sequence7~9) in the
above Figure, is simplified recommendation and actual training sequence may vary depending on systems.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
4. After RESET_n is de-asserted(Tc), wait at least tINIT3 before activating CKE. Clock(CK_t,CK_c) is required to be started and
stabilized for tINIT4 before CKE goes active(Td). CS is required to be maintained LOW when controller activates CKE.
5. After setting CKE high, wait minimum of tINIT5 to issue any MRR or MRW commands(Te). For both MRR and MRW commands,
the clock frequency must be within the range defined for tCKb. Some AC parameters (forexample, tDQSCK) could have relaxed
timings (such as tDQSCKb) before the system is appropriately configured.
6. After completing all MRW commands to set the Pull-up, Pull-down and Rx termination values, the DRAM controller can issue
ZQCAL Start command to the memory(Tf). This command is used to calibrate VOH level and output impedance over process,
voltage and temperature. In systems where more than one LPDDR4 DRAM devices share one external ZQ resistor, the controller
must not overlap the ZQ calibration sequence of each LPDDR4 device. ZQ calibration sequence is completed after tZQCAL(Tg)
and the ZQCAL Latch command must be issued to update the DQ drivers and DQ+CA ODT to the calibrated values.
7. After tZQLAT is satisfied (Th), the command bus (internal VREF(CA), CS, and CA) should be trained for high-speed operation
by issuing an MRW command (Command Bus Training Mode). This command is used to calibrate the device's internal VREF and
align CS/CA with CK for high-speed operation.
The LPDDR4 device will power-up with receivers configured for low-speed operations, and VREF(CA) set to a default factory
setting. Normal device operation at clock speeds higher than tCKb may not be possible until command bus training has been
completed. The command bus training MRW command uses the CA bus as inputs for the calibration date stream, and outputs
the results asynchronously on the DQ bus. See command bus training in the MRW section for information on how to enter/exit
the training mode.
8. After command bus training, DRAM controller must perform write leveling. Write leveling mode is enabled when MR2 OP[7] is
high(Ti). See Write Leveling Parameters section for detailed description of write leveling entry and exit sequence.
In write leveling mode, the DRAM controller adjusts write DQS_t/_c timing to the point where the LPDDR4 device recognizes the
start of write DQ data burst with desired write latency.
9. After write leveling, the DQ Bus (internal VREF(DQ), DQS, and DQ) should be trained for high-speed operation using the MPC
training commands and by issuing MRW commands to adjust VREF(DQ)(Tj). The LPDDR4 device will power-up with receivers
configured for low-speed operations and VREF(DQ) set to a default factory setting. Normal device operation at clock speeds
higher than tCKb should not be attempted until DQ Bus training has been completed. The MPC Read Calibration command is
used together with MPC FIFO Write/Read commands to train DQ bus without disturbing the memory array contents.
See DQ Bus Training section for detailed DQ Bus Training sequence.
10. At Tk the LPDDR4 device is ready for normal operation, and is ready to accept any valid command. Any more registers that
have not previously been set up for normal operation should be written at this time.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
Table 3 - Initialization Timing Parameters
Parameter
Value
Min
tINIT0
Max
20
Unit
Comment
ms
Maximum Voltage Ramp Time
tINIT1
200
us
Minimum RESET_n LOW time after completion of voltage ramp
tINIT2
10
ns
Minimum CKE LOW time before RESET_n goes HIGH
tINIT3
2
ms
Minimum CKE LOW time after RESET_n goes HIGH
tINIT4
5
tCK
Minimum stable clock before first CKE HIGH
tINIT5
2
us
Minimum idle time before first MRW/MRR command
tZQCAL
1
us
ZQ Calibration time
tZQLAT
Max(30ns.8tCK)
ns
ZQCAL latch quite time
tCKb
Note 1, 2
ns
Clock cycle time during boot
Note 1, 2
Notes
1. Min tCKb guaranteed by DRAM test is 18ns.
2. The system may boot at a higher frequency than dictated by min tCKb. The higher boot frequency is system dependent
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.3.2. Reset Initialization with Stable Power
The following sequence is required for RESET at no power interruption initialization.
1. Assert RESET_n below 0.2 x VDD2 anytime when reset is needed. RESET_n needs to be maintained for minimum tPW_RESET.
CKE must be pulled LOW at least 10 ns before de-asserting RESET_n.
2. Repeat steps 4 to 10 in "Voltage Ramp and Device Initialization" section.
Table 4 - Reset Timing Parameter
Parameter
tPW_RESET
Value
Min
Max
100
-
Unit
Comment
ns
Minimum RESET_n low time for Reset Initialization with stable power
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.3.3. Power-off Sequence
1.3.3.1. Controlled Power-off Sequence
The following procedure is required to power off the device.
While powering off, CKE must be held LOW (≤0.2 X VDD2) and all other inputs must be between VILmin and VIHmax. The device
outputs remain at High-Z while CKE is held LOW. DQ, DMI, DQS_t and DQS_c voltage levels must be between VSSQ and VDDQ
during voltage ramp to avoid latch-up. RESET_n, CK_t, CK_c, CS and CA input levels must be between VSS and VDD2 during voltage
ramp to avoid latch-up.
Tx is the point where any power supply drops below the minimum value specified.
Tz is the point where all power supplies are below 300mV. After TZ, the device is powered off.
Table 5 - Power Supply Conditions for Power-off
Between...
Applicable Conditions
VDD1 must be greater than VDD2
TX and TZ
VDD2 must be greater than VDDQ - 200mV
Notes
1. The voltage difference between any of VSS, VSSQ pins must not exceed 100mV
1.3.3.2. Uncontrolled Power-off Sequence
When an uncontrolled power-off occurs, the following conditions must be met:
At Tx, when the power supply drops below the minimum values specified, all power supplies must be turned off and all power supply
current capacity must be at zero, except any static charge remaining in the system.
After Tz (the point at which all power supplies first reach 300mV), the device must power off. During this period the relative voltage
between power supplies is uncontrolled. VDD1 and VDD2 must decrease with a slope lower than 0.5V/μs between Tx and Tz.
An uncontrolled power-off sequence can occur a maximum of 400 times over the life of the device.
Table 6 - Timing Parameters for Power-off
Symbol
tPOFF
Value
Min
Max
2
Rev 1.2 / Mar. 2020 / SK hynix Confidential
Unit
Comment
s
Maximum Power-off ramp time
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4. Mode Register Definition
Table below shows the mode registers for LPDDR4 SDRAM. Each register is denoted as "R" if it can be read but not written, "W" if it
can be written but not read, and "R/W" if it can be read and written. A Mode Register Read command is used to read a mode register. A Mode Register Write command is used to write a mode register.
Table 7 - Mode Register Assignment
MR#
MA
Function
Access
OP7
OP6
OP5
0
00H
Device Information
R
Reserved
RFU
SingleEnded
Mode
1
01H
Device Feature 1
W
RPST
2
02H
Device Feature 2
W
WR Lev
WLS
WL
DBIRD
PDDS
Thermal Offset
PPRE
3
03H
IO Configuration 1
W
DBIWR
4
04H
Refresh Rate
R/W
TUF
OP4
OP3
RZQI
RDPRE
nWR (for AP)
OP2
OP1
OP0
Link
RFU
Latency
Mode
Refresh
Mode
MR0
WRPRE
BL
MR1
RL
PPRP
SR Abort
MR2
WR-PST
PU-CAL
Refresh Rate
MR3
MR4
5
05H
Basic Configuration 1
R
LPDDR4 Manufacturer ID
MR5
6
06H
Basic Configuration 2
R
Revision ID-1
MR6
7
07H
Basic Configuration 3
R
8
08H
Basic Configuration 4
R
Revision ID-2
IO Width
MR7
Density
9
09H
Test Mode
W
10
0AH
ZQ Reset
W
11
0BH
ODT Feature
W
RFU
R/W
CBT Mode
for Byte
Mode
VR(CA)
Type
MR8
Vendor Specific Test Mode
MR9
RFU
CA ODT
ZQ Reset
RFU
DQ ODT
MR10
MR11
12
0CH
VREF(CA) R0
VREF(CA)
13
0DH
Functional options
W
FSP-OP
FSP-WR
14
0EH
VREF(DQ)
R/W
RFU
VR(DQ)
15
0FH
Invert Register 0
W
Lower Byte Invert for DQ Calibration
MR15
16
10H
PASR Bank
W
PASR Bank Mask
MR16
DMD
RRO
VRCG
MR12
VRO
RPT
VREF(DQ)
CBT
MR13
MR14
17
11H
PASR Segment
W
PASR Segment Mask
MR17
18
12H
DQS Oscillator 1
R
DQS Oscillator Count - LSB
MR18
19
13H
DQS Oscillator 2
R
DQS Oscillator Count - MSB
MR19
20
14H
Invert Register 1
W
Upper Byte Invert for DQ Calibration
MR20
21
15H
Vendor Specific
N/A
RFU
22
16H
SOC ODT Feature
W
ODTD for x8 2ch
Byte Mode
23
17H
DQS Oscillator Run Time
W
24
18H
TRR
R/W
25
19H
PPR Resource
R
Post Package Repair Resources
MR25
26
1AH
RFU
N/A
Reserved for Future Use
MR26
27
1BH
RFU
N/A
Reserved for Future Use
MR27
28
1CH
RFU
N/A
Reserved for Future Use
MR28
29
1DH
RFU
N/A
Reserved for Future Use
MR29
30
1EH
RFU
N/A
Reserved for Future Use
MR30
Rev 1.2 / Mar. 2020 / SK hynix Confidential
LS CA
buffer
RFU
ODTD-CA ODTE-CS ODTE-CK
MR21
SOC ODT
DQS Oscillator Interval Timer Run Time Setting
TRR
TRR Bank Address
U-MAC
MAC Value
MR22
MR23
MR24
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
MR#
MA
Function
Access
31
1FH
RFU
N/A
32
20H
DQ Calibration
- Pattern A
OP7
OP6
OP5
OP4
OP3
Byte Mode
Vref Selection
OP2
OP1
OP0
Link
RFU
MR31
W
See DQ Calibration section
MR32
DNU
N/A
Do Not Use
DQ Calibration
- Pattern B
W
See DQ Calibration section
41:47 29H:2FH
DNU
N/A
48:50 30H:32H
RFU
N/A
Single Ended Mode
W
RFU
N/A
33:39 21H:27H
40
51
28H
33H
52:63 34H:3FH
MR40
Do Not Use
Reserved for Future Use
RFU
S/E
Clock
S/E
WDQS
S/E RDQS
RFU
Reserved for Future Use
Notes
1. RFU bits should be set to ‘0’ during mode register writes
2. RFU bits should be read as ‘0’ during mode register reads
3. All mode registers that are specified as RFU or Write-only shall return undefined data when read and DQS_t/DQS_c shall be toggled
4. All mode registers that are specified as RFU shall not be written
5. See vendor device datasheet for details on vendor-specific mode registers
6. Writes to Read-only registers shall have no effect on the functionality of the device
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.1. MR0 Register Information (MA[5:0] = 00H)
OP[7]
OP[6]
OP[5]
Reserved
RFU
Single-Ended
Mode
Function
Register
Type
Operand
OP[4]
OP[3]
RZQI
OP[2]
OP[1]
OP[0]
RFU
Latency
Mode
Refresh
Mode
Data
Refresh Mode
OP[0]
0B: Both legacy & modified refresh mode supported
1B: Only modified refresh mode supported
Latency Mode
OP[1]
0B: Device supports normal latency
1B: Device supports byte mode latency
Read-only
RZQI
(Built-in Self-Test for RZQ)
Single Ended Mode
OP[4:3]
OP[5]
00B: RZQ Self-Test Not Supported
01B: ZQ pin may connect to VSSQ or float
10B: ZQ-pin may short to VDDQ
11B: ZQ-pin Self-Test Completed, no error condition detected
(ZQ-pin may not connect to VSSQ or float, nor short to VDDQ)
0B: No Support For Single Ended Mode
1B: Support For Single Ended Mode
Notes
6,7
1,2,3,4
8
Notes
1. RZQI MR value, if supported, will be valid after the following sequence:
a. Completion of MPC ZQCAL Start command to either channel.
b. Completion of MPC ZQCAL Latch command to either channel then tZQLAT is satisfied. RZQI value will be lost after Reset.
2. If the ZQ-pin is connected to VSSQ to set default calibration, OP[4:3] shall be set to 01B. If the ZQ-pin is not connected to VSSQ, either OP[4:3]
= 01B or OP[4:3] = 10B might indicate might indicate a ZQ-pin assembly error. It is recommended that the assembly error is corrected.
3. In the case of possible assembly error, the LPDDR4-SDRAM device will default to factory trim settings for RON, and will ignore ZQ Calibration
commands. In either case, the device may not function as intended.
4. If ZQ Self-Test returns OP[4:3] = 11B, the device has detected a resistor connected to the ZQ-pin. However, this result cannot be used to validate
the ZQ resistor value or that the ZQ resistor tolerance meets the specified limits (i.e. 240Ω ± 1%).
5. CATR functionality may not provide right information whether CA termination is turned on or not. However, CA termination is required to be
decided with the combination of MR22 OP[5] and MR11 OP[6:4] which shows CA ODT values. It is recommended for user to have CATR information
with the combination ODT_PAD and MR11 OP[6:4]. MR0 OP[7] indicate 1’B only when MR22 OP[5] is high and MR11 OP[6:4] is not 000’b.
6. For the byte mode LPDDR4 SDRAM device, longer latency is required.
The LPDDR4 SDRAM device will set MR0 OP[1]=1 to indicate which latencies are supported. See section for byte-mode latency for the details.
7. Devices not intended to be combined with byte mode devices are not required to support byte mode latency.
8. Support for Single Ended Mode is optional. If supported, single ended write DQS, read DQS, and CK can be enabled in MR51.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.2. MR1 Register Information (MA[5:0] = 01H)
OP[7]
RPST
Function
OP[6]
OP[5]
OP[4]
nWR (for AP)
Register Type
BL
(Burst Length)
OP[3]
OP[2]
RD-PRE
WR-PRE
OP[1]
Operand
OP[1:0]
OP[0]
BL
Data
00B: BL=16 Sequential (default)
01B: BL=32 Sequential
10B: BL=16 or 32 Sequential (on-the-fly)
All Others: Reserved
Notes
1,5,6
WR-PRE
(WR Pre-amble Length)
OP[2]
0B: Reserved
1B: WR Pre-amble = 2nCK (default)
5,6
RD-PRE
(RD Pre-amble Type)
OP[3]
0B: RD Pre-amble = Static (default)
1B: RD Pre-amble = Toggle
3,5,6
For x16 Mode
000B: nWR =
001B: nWR =
010B: nWR =
011B: nWR =
100B: nWR =
101B: nWR =
110B: nWR =
111B: nWR =
Write-only
nWR
(Write-Recovery for Auto
Precharge commands)
OP[6:4]
RPST
(RD Post-amble Length)
OP[7]
6 (default)
10
16
20
24
30
34
40
2,5,6
For Byte(x8) Mode
000B: nWR = 6 (default)
001B: nWR = 12
010B: nWR = 16
011B: nWR = 22
100B: nWR = 28
101B: nWR = 32
110B: nWR = 38
111B: nWR = 44
0B: RD Post-amble = 0.5*tCK (default)
1B: RD Post-amble = 1.5*tCK
4,5,6
Notes
1. Burst length on-the-fly can be set to either BL=16 or BL=32 by setting the “BL” bit in the command operands. See the Command Truth Table.
2. The programmed value of nWR is the number of clock cycles the LPDDR4-SDRAM device uses to determine the starting point of an internal
Pre-charge operation after a Write burst with AP (auto-pre-charge) enabled.
See Table, Read and Write Latencies (Frequency Ranges for RL, WL, and n WR Settings) later in this section
3. For Read operations this bit must be set to select between a “toggling” pre-amble and a “Non-toggling” pre-amble. See the preamble section
for a drawing of each type of preamble.
4. OP[7] provides an optional READ post-amble with an additional rising and falling edge of DQS_t. The optional postamble cycle is provided for
the benefit of certain memory controllers.
5. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers for the set
point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address.
6. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will operate only
according to the values stored in the registers for the active set point, i.e., the set point determined by the state of the FSP-OP bit (MR13 OP[7]).
The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.2.1. Burst Sequence
Table 8 - Burst Sequence for Read
Burst
Length
16
32
Burst
Type
SEQ
SEQ
Burst Cycle Number and Burst Address Sequence
C4
C3
C2
C1
Co
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
0
0
0
0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
V
0
1
0
0
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
V
1
0
0
0
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
V
1
1
0
0
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
0
0
1
0
0
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
0
1
0
0
0
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
0
1
1
0
0
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
1
0
0
0
0
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
0
1
2
3
4
5
6
7
1
0
1
0
0
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
10
11
12
13
4
5
6
7
8
9
A
B
1
1
0
0
0
18
19
1A
1B
1C
1D
1E
1F
10
11
12
13
14
15
16
17
8
9
A
B
C
D
E
F
1
1
1
0
0
1C
1D
1E
1F
10
11
12
13
14
15
16
17
18
19
1A
1B
C
D
E
F
0
1
2
3
17
18
19
20
21
22
F
10
3
14
23
24
11
12
13
14
15
16
17
15
16
17
18
19
1A
1B
18
19
1A
1B
1C
1D
1E
1F
1C
1D
1E
1F
10
11
12
13
25
26
27
28
29
30
31
32
18
19
1A
1B
1C
1D
1E
1F
1C
1D
1E
1F
10
11
12
13
10
11
12
13
14
15
16
17
14
15
16
17
18
19
1A
1B
8
9
A
B
C
D
E
F
C
D
E
F
0
1
2
3
0
1
2
3
4
5
6
7
4
5
6
7
8
9
A
B
Notes
1. C0-C1 are assumed to be ‘0’ , and are not transmitted on the command bus
2. The starting address is on 64-bit (4n) boundaries.
Table 9 - Burst Sequence for Write
Burst Cycle Number and Burst Address Sequence
Burst
Length
Burst
Type
C4
C3
C2
C1
Co
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
16
SEQ
V
0
0
0
0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
32
SEQ
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Notes
1. C0-C1 are assumed to be ‘0’ , and are not transmitted on the command bus
2. The starting address is on 256-bit (16n) boundaries for Burst length 16.
3. The starting address is on 512-bit (32n) boundaries for Burst length 32.
4. C2-C3 shall be set to ‘0’ for all Write operations.
5. C4=1 for Write is supported in SK hynix device.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
24
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.3. MR2 Register Information (MA[5:0] = 02H)
OP[7]
OP[6]
WR Lev
WLS
OP[5]
OP[4]
WL
OP[3]
OP[2]
OP[1]
OP[0]
RL
Standard LPDDR4
Function
Register Type
Operand
Data
Notes
OP[2:0]
DBI Disable (MR3 OP[6]=0B)
000B: RL= 6 & nRTP = 8 (Default)
001B: RL= 10 & nRTP = 8
010B: RL= 14 & nRTP = 8
011B: RL= 20 & nRTP = 8
100B: RL= 24 & nRTP = 10
101B: RL= 28 & nRTP = 12
110B: RL= 32 & nRTP = 14
111B: RL= 36 & nRTP = 16
DBI Enable (MR3 OP[6]=1B)
000B: RL= 6 & nRTP = 8
001B: RL= 12 & nRTP = 8
010B: RL= 16 & nRTP = 8
011B: RL= 22 & nRTP = 8
100B: RL= 28 & nRTP = 10
101B: RL= 32 & nRTP = 12
110B: RL= 36 & nRTP = 14
111B: RL= 40 & nRTP = 16
1,3,4
OP[5:3]
Set “A” (MR2 OP[6]=0B)
000B: WL=4 (Default)
001B: WL=6
010B: WL=8
011B: WL=10
100B: WL=12
101B: WL=14
110B: WL=16
111B: WL=18
Set “B” (MR2 OP[6]=1B)
000B: WL=4
001B: WL=8
010B: WL=12
011B: WL=18
100B: WL=22
101B: WL=26
110B: WL=30
111B: WL=34
1,3,4
WLS
(Write latency set)
OP[6]
0B: WL Set “A” (default)
1B: WL Set “B”
1,3,4
WR Lev
(Write Leveling)
OP[7]
0B: Disabled (default)
1B: Enabled
RL
(Read latency)
Write only
WL
(Write latency)
2
Notes
1. See Latency Code Frequency Table for allowable frequency ranges for RL/WL/nWR/nRTP.
2. After a MRW to set the Write Leveling Enable bit (OP[7]=1B), the LPDDR4-SDRAM device remains in the MRW state until another MRW command
clears the bit (OP[7]=0B). No other commands are allowed until the Write Leveling Enable bit is cleared.
3. There are two physical registers assigned to each bit of this MR operand, designated set point 0 and set point 1. Only the registers for the set
point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address.
4. There are two physical registers assigned to each bit of this MR operand, designated set point 0 and set point 1. The device will operate only
according to the values stored in the registers for the active set point, i.e., the set point determined by the state of the FSP-OP bit (MR13 OP[7]).
The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.3.1. Read and Write Latencies (Frequency Ranges for RL, WL, and nWR Settings)
For x8 Mode
Read Latency
Write Latency
nWR
nRTP
Freq. limit
(Greater than)
Freq. limit
(Same or less than)
4
6
8
10
266
6
8
12
8
266
533
18
8
12
16
8
533
800
22
24
10
18
22
8
800
1066
26
30
12
22
28
10
1066
1333
32
36
14
26
32
12
1333
1600
36
40
16
30
38
14
1600
1866
40
44
18
34
44
16
1866
2133
nCK
nCK
nCK
nCK
nCK
nCK
MHz
MHz
No DBI
w/ DBI
Set “A”
Set “B”
6
6
4
10
12
16
Notes
1,2,3,4
,5,6
Notes
1. The LPDDR4-SDRAM device should not be operated at a frequency above the Upper Frequency Limit, or below the Lower Frequency Limit,
shown for each RL, WL, nRTP, or nWR value.
2. DBI for Read operations is enabled in MR3-OP[6]. When MR3-OP[6]=0, then the “No DBI” column should be used for Read Latency.
When MR3-OP[6]=1, then the “w/DBI” column should be used for Read Latency.
3. Write Latency Set “A” and Set “B” is determined by MR2-OP[6]. When MR2-OP[6]=0, then Write Latency Set “A” should be used.
When MR2-OP[6]=1, then Write Latency Set “B” should be used.
4. The programmed value of nWR is the number of clock cycles the LPDDR4-SDRAM device uses to determine the starting point of an internal
Pre-charge operation after a Write burst with AP (auto-pre-charge) enabled. It is determined by RU(tWR/tCK).
5. The programmed value of nRTP is the number of clock cycles the LPDDR4-SDRAM device uses to determine the starting point of an internal
Pre-charge operation after a Read burst with AP (auto-pre-charge) enabled. It is determined by RU(tRTP/tCK).
6. nRTP shown in this table is valid for BL16 only. For BL32, the SDRAM will add 8 clocks to the nRTP value before starting a pre-charge.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
26
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.4. MR3 Register Information (MA[5:0] = 03H)
OP[7]
OP[6]
DBI-WR
DBI-RD
Function
OP[5]
Register Type
OP[4]
OP[3]
PDDS
OP[2]
OP[1]
OP[0]
PPRP
WR PST
PU-CAL
Operand
Data
PU-CAL
(Pull-up Calibration Point)
OP[0]
0B: VDDQ*0.6
1B: VDDQ*0.5 (default)
WR-PST
(Write Post-amble length)
OP[1]
0B: WR Post-amble = 0.5*tCK (default)
1B: WR Post-amble = 1.5*tCK (Vendor Specific)
Post Package Repair
Protection
OP[2]
0B: PPR Protection Disabled (Default)
1B: PPR Protection Enabled
PDDS
(Pull-down Drive Strength)
Write-only
OP[5:3]
000B:
001B:
010B:
011B:
100B:
101B:
110B:
111B:
Notes
1,4
2,3,5
6
RFU
RZQ/1
RZQ/2
RZQ/3
RZQ/4
RZQ/5
RZQ/6 (default)
Reserved
1,2,3
DBI-RD
(DBI-Read Enable)
OP[6]
0B: Disabled (default)
1B: Enabled
2,3,7
DBI-WR
(DBI-WR Enable)
OP[7]
0B: Disabled (default)
1B: Enabled
2,3
Notes
1. All values are “typical”. The actual value after calibration will be within the specified tolerance for a given voltage and temperature.
Re-calibration may be required as voltage and temperature vary.
2. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.
Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR
address.
3. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.
The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of
the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without
affecting device operation.
4. PU-CAL setting is required as the same value for both Ch.A and Ch.B before ZQCAL start command.
5. SK hynix 8Gb LPDDR4 doesn’t require 1.5*tCK apply => 1.6GHz clock.
6. If MR3 OP[2] is set to 1b then PPR protection mode is enabled. The PPR Protection bit is a sticky bit and can only be set to 0b by power on
reset. MR4 OP[4] controls entry to PPR Mode. If PPR protection is enabled then DRAM will not allow writing of 1 to MR4 OP[4].
7. DBI-RD is supported up to 3733Mbps.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
27
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.5. MR4 Register Information (MA[5:0] = 04H)
OP[7]
TUF
Function
OP[6]
OP[5]
Thermal Offset
Register Type
OP[4]
OP[3]
PPRE
SR Abort
OP[2]
Operand
OP[1]
Refresh Rate
Data
000B:
001B:
010B:
011B:
100B:
101B:
110B:
111B:
SDRAM Low temperature operating limit exceeded
4x refresh
2x refresh
1x refresh (default)
0.5x refresh
0.25x refresh, no de-rating
0.25x refresh, with de-rating
SDRAM High temperature operating limit exceeded
Refresh Rate
Read
OP[2:0]
Self Refresh Abort
Write
OP[3]
0B: Disabled (default)
1B: Enabled
PPRE
(Post-package repair entry/exit)
Write
OP[4]
0B: Exit PPR mode (default)
1B: Enter PPR mode
Thermal Offset
Write
OP[6:5]
TUF
(Temperature Update Flag)
Read
OP[7]
OP[0]
00B:
01B:
10B:
11B:
Notes
1,2,3,4,
7,8,9
9
5,9
No offset, 0-5oC gradient (default)
5oC offset, 5-10oC gradient
10oC offset, 10-15oC gradient
Reserved
0B: No change in OP[2:0] since last MR4 read (default)
1B: Change in OP[2:0] since last MR4 read
6,7,8
Notes
1. The refresh rate for each MR4-OP[2:0] setting applies to tREFI, tREFIpb, and tREFW. If OP[2]=0B, the device temperature is less or equal to
85’C. Other values require either a longer (2x, 4x) refresh interval at lower temperatures, or a shorter (0.5x,0.25x) refresh interval at higher
temperatures. If OP[2]=1, the device temperature is greater than 85’C.
2. At higher temperatures (>85’C), AC timing de-rating may be required. If de-rating is required the LPDDR4-SDRAM will set OP[2:0]=110B.
See de-rating timing requirements in the AC timing Parameters section.
3. DRAM vendors may or may not report all of the possible settings over the operating temperature range of the device.
Each vendor guarantees that their device will work at any temperature within the range using the refresh interval requested by their device.
4. The device may not operate properly when OP[2:0]=000B or 111B.
5. Post-package repair can be entered or exited by writing to OP[4].
6. When OP[7]=1, the refresh rate reported in OP[2:0] has changed since the last MR4 read. A mode register read from MR4 will reset OP[7] to ‘0’.
7. OP[7]=0 at power-up. OP[2:0] bits are undefined at power-up.
8. See the section on Temperature Sensor for information on the recommended frequency of reading MR4.
9. OP[6:3] bits are that can be written in this register. All other bits will be ignored by the DRAM during a MRW to this register
Rev 1.2 / Mar. 2020 / SK hynix Confidential
28
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.6. MR5 Register Information (MA[5:0] = 05H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
LPDDR4 Manufacturer ID
Function
Register Type
Operand
LPDDR4 Manufacturer ID
Read-only
OP[7:0]
Data
Notes
00000110B : SK hynix
1.4.7. MR6 Register Information (MA[5:0] = 06H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Revision ID-1
Function
Register Type
Operand
LPDDR4 Revision ID-1
Read-only
OP[7:0]
Data
Notes
00000000B: A-version
00000001B: B-version
1
Notes
1. Please contact SK hynix office for MR6 code for this device.
1.4.8. MR7 Register Information (MA[5:0] = 07H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Revision ID-2
Function
Register Type
Operand
LPDDR4 Revision ID-2
Read-only
OP[7:0]
Data
00000000B: A-version
00000001B: B-version
Notes
1
Notes
1. Please contact SK hynix office for MR7 code for this device.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
29
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.9. MR8 Register Information (MA[5:0] = 08H)
OP[7]
OP[6]
OP[5]
OP[4]
IO Width
Function
OP[2]
OP[1]
Density
Register Type
Read-only
IO Width
OP[0]
Type
Operand
Type
Density
OP[3]
Data
Notes
OP[1:0]
00B: S16 SDRAM (16n pre-fetch)
01B: Low VDDQ(0.6V) Support
All Others: Reserved
OP[5:2]
0000B: 4Gb per die (2Gb per channel)
0001B: 6Gb per die (3Gb per channel)
0010B: 8Gb per die (4Gb per channel)
0011B: 12Gb per die (6Gb per channel)
0100B: 16Gb per die (8Gb per channel)
0101B: 24Gb per die (12Gb per channel)
0110B: 32Gb per die (16Gb per channel)
1100B: 2Gb per die (1Gb per channel)
All Others: Reserved
OP[7:6]
00B: x16 (per channel)
01B: x8 (per channel)
All Others: Reserved
1.4.10. MR9 Register Information (MA[5:0] = 09H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Vendor Specific Test Register
Notes
1. Only 00H should be written to this register.
1.4.11. MR10 Register Information (MA[5:0] = 0AH)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
RFU
Function
Register Type
Operand
ZQ Reset
Write-only
OP[0]
OP[0]
ZQ Reset
Data
OB: Normal Operation (Default)
1B: ZQ Reset
Notes
1,2
Notes
1. See the AC Timing Parameters tables for calibration latency and timing
2. If the ZQ-pin is connected to VDDQ through RZQ, either the ZQ calibration function or default calibration (via ZQ-Reset) is supported.
If the ZQ-pin is connected to VSS, the device operates with default calibration, and ZQ calibration commands are ignored. In both cases, the ZQ
connection shall not change after power is applied to the device.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
30
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.12. MR11 Register Information (MA[5:0] = 0BH)
OP[7]
OP[6]
RFU
Function
OP[5]
OP[4]
CA ODT
Register Type
DQ ODT
(DQ Bus Receiver On-Die-Termination)
OP[3]
RFU
OP[1]
OP[0]
DQ ODT
Operand
Data
OP[2:0]
000B:
001B:
010B:
011B:
100B:
101B:
110B:
111B:
OP[6:4]
0000B:
0001B:
0010B:
0011B:
0100B:
0101B:
0110B:
0111B:
Write-only
CA ODT
(CA Bus Receiver On-Die-Termination)
OP[2]
Disable (Default)
RZQ/1
RZQ/2
RZQ/3
RZQ/4
RZQ/5
RZQ/6
RFU
Disable (Default)
RZQ/1
RZQ/2
RZQ/3
RZQ/4
RZQ/5
RZQ/6
RFU
Notes
1,2,3
1,2,3
Notes
1. All values are “typical”. The actual value after calibration will be within the specified tolerance for a given voltage and temperature.
Re-calibration may be required as voltage and temperature vary.
2. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.
Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR
address.
3. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.
The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of
the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without
affecting device operation.
4. ODT for non-target DRAM is optional.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
31
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.13. MR12 Register Information (MA[5:0] = 0CH)
OP[7]
OP[6]
CBT Mode for
Byte Mode
VR-CA
Function
VREF(CA)
(VREF(CA) Setting)
OP[5]
OP[3]
OP[2]
OP[1]
OP[0]
VREF(CA)
Register Type
Operand
Notes
1,2,3,5,
6
OP[6]
0B: VREF(CA) Range[0] enabled
1B: VREF(CA) Range[1] enabled (default)
1,2,4,5,
6
OP[7]
0B: Mode1 (Default)
1B: Mode2
Read/Write
Write-Only
Data
000000B:
-- Thru –
110010B: See table below
All Others: Reserved
OP[5:0]
VREF(CA) Range
CBT Mode for Byte Mode
OP[4]
7
Notes
1. This register controls the VREF(CA) levels for Frequency-Set-Point[1:0]. Values from either VR(ca)[0] or VR(ca)[1] may be selected by setting
OP[6] appropriately.
2. A read to this register places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ’s shall be set to ‘0’.
See the Figure Mode Register Operation.
3. A write to OP[5:0] sets the internal VREF(CA) level for FSP[0] when MR13 OP[6]=0B, or sets FSP[1] when MR13 OP[6]=1B.
The time required for VREF(CA) to reach the set level depends on the step size from the current level to the new level.
See the section on VREF(CA) training for more information.
4. A write to OP[6] switches the LPDDR4-SDRAM between two internal VREF(CA) ranges. The range (Range[0] or Range[1]) must be selected
when setting the VREF(CA) register. The value, once set, will be retained until overwritten, or until the next power-on or RESET event.
5. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.
Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR
address, or read from with an MRR command to this address.
6. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.
The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of
the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without
affecting device operation.
7. This field (MR12 OP[7]) is only available in Byte-mode Package and its mixed package (x8 2ch device)
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
Table 10 - VREF Settings for Range[0] and Range[1]
Function
VREF
Settings
for MR12
Operand
OP[5:0]
Range[0] Values (% of VDDQ)
000000B:
000001B:
000010B:
000011B:
000100B:
000101B:
000110B:
000111B:
001000B:
001001B:
001010B:
001011B:
001100B:
001101B:
001110B:
001111B:
010000B:
010001B:
010010B:
010011B:
010100B:
010101B:
010110B:
010111B:
011000B:
011001B:
15.0%
15.6%
16.2%
16.8%
17.4%
18.0%
18.6%
19.2%
19.8%
20.4%
21.0%
21.6%
22.2%
22.8%
23.4%
24.0%
24.6%
25.1%
25.7%
26.3%
26.9%
27.5%
28.1%
28.7%
29.3%
29.9%
011010B: 30.5%
011011B: 31.1%
011100B: 31.7%
011101B: 32.3%
011110B: 32.9%
011111B: 33.5%
100000B: 34.1%
100001B: 34.7%
100010B: 35.3%
100011B: 35.9%
100100B: 36.5%
100101B: 37.1%
100110B: 37.7%
100111B: 38.3%
101000B: 38.9%
101001B: 39.5%
101010B: 40.1%
101011B: 40.7%
101100B: 41.3%
101101B: 41.9%
101110B: 42.5%
101111B: 43.1%
110000B: 43.7%
110001B: 44.3%
110010B: 44.9%
All Others: Reserved
Range[1] Values (% of VDDQ)
000000B:
000001B:
000010B:
000011B:
000100B:
000101B:
000110B:
000111B:
001000B:
001001B:
001010B:
001011B:
001100B:
001101B:
001110B:
001111B:
010000B:
010001B:
010010B:
010011B:
010100B:
010101B:
010110B:
010111B:
011000B:
011001B:
32.9%
33.5%
34.1%
34.7%
35.3%
35.9%
36.5%
37.1%
37.7%
38.3%
38.9%
39.5%
40.1%
40.7%
41.3%
41.9%
42.5%
43.1%
43.7%
44.3%
44.9%
45.5%
46.1%
46.7%
47.3%
47.9%
011010B: 48.5%
011011B: 49.1%
011100B: 49.7%
011101B: 50.3%
011110B: 50.9%
011111B: 51.5%
100000B: 52.1%
100001B: 52.7%
100010B: 53.3%
100011B: 53.9%
100100B: 54.5%
100101B: 55.1%
100110B: 55.7%
100111B: 56.3%
101000B: 56.9%
101001B: 57.5%
101010B: 58.1%
101011B: 58.7%
101100B: 59.3%
101101B: 59.9%
101110B: 60.5%
101111B: 61.1%
110000B: 61.7%
110001B: 62.3%
110010B: 62.9%
All Others: Reserved
Notes
1,2,3
Notes
1. These values may be used for MR12 OP[5:0] to set the VREF(CA) levels in the LPDDR4-SDRAM.
2. The range may be selected in the MR12 register by setting OP[6] appropriately.
3. The MR12 registers represents either FSP[0] or FSP[1]. Two frequency-set-points each for CA and DQ are provided to allow for
faster switching between terminated and un-terminated operation, or between different high-frequency setting which may use
different terminations values.
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.14. MR13 Register Information (MA[5:0] = 0DH)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
FSP-OP
FSP-WR
DMD
RRO
VRCG
VRO
RPRE-TR
CBT
Function
Register Type
Operand
Data
Notes
CBT
(Command Bus Training)
OP[0]
0B: Normal Operation (default)
1B: Command Bus Training mode enabled
RPT
(Read Preamble Training)
OP[1]
0B: Normal Operation (default)
1B: Read Preamble Training mode enabled
VRO
(Vref Output)
OP[2]
0B: Normal Operation (default)
1B: Output the VREF(CA) value on DQ[0] and
the VREF(DQ) value on DQ[1]
2
OP[3]
0B: Normal Operation (default)
1B: VREF Fast Response (high current) mode
3
RRO
(Refresh Rate Option)
OP[4]
0B: Disable codes 001 and 010 in MR4 OP[2:0]
1B: Enable MR4 OP[2:0]
DMD
(Data Mask Disable)
OP[5]
0B: Data Mask Operation Enabled (default)
1B: Data Mask Operation Disabled
6
FSP-WR
(Frequency Set Point Write Enable)
OP[6]
0B: Frequency-Set-Point[0] (default)
1B: Frequency-Set-Point[1]
7
FSP-OP
(Frequency Set Point Operation Mode)
OP[7]
0B: Frequency-Set-Point[0] (default)
1B: Frequency-Set-Point[1]
8
VRCG
(VREF Current Generator)
Write-Only
1
4,5
Notes
1. A write to set OP[0]=1 causes the LPDDR4-SDRAM to enter the Command bus training mode. When OP[0]=1 and CKE goes LOW, commands
are ignored and the contents of CA[5:0] are mapped to the DQ bus. CKE must be brought HIGH before doing a MRW to clear this bit (OP[0]=0)
and return to normal operation. See the VREF(CA) training section for more information.
2. When set, the LPDDR4-SDRAM will output the VREF(CA) voltage on DQ[0] and the VREF(DQ) voltage on DQ[1]. Only the “active” frequencyset-point, as defined by MR13 OP[7], will be output on the DQ pins. This function allows an external test system to measure the internal VREF
levels.
3. When OP[3]=1, the VREF circuit uses a high-current mode to improve VREF settling time.
4. MR13 OP4 RRO bit is valid only when MR0 OP0 = 1. For LPDDR4 devices with MR0 OP0 = 0, MR4 OP[2:0] bits are not dependent on MR13 OP4.
5. When OP[4] = 0, only 001b and 010b in MR4 OP[2:0] are disabled. LPDDR4 devices must report 011b instead of 001b or 010b in this case.
Controller should follow the refresh mode reported by MR4 OP[2:0], regardless of RRO setting. TCSR function does not depend on RRO setting.
6. When enabled (OP[5]=0B) data masking is enabled for the device. When disabled (OP[5]=1B), Masked Write Command is not allowed and it
is illegal. See the Data Mask section for more information.
7. FSP-WR determines which frequency-set-point registers are accessed with MRW commands for the following functions: VREF(CA) Setting,
VREF(CA) Range, VREF(DQ) Setting, VREF(DQ) Range, CA ODT Enable, CA ODT value, DQ ODT Enable, DQ ODT value, DQ Calibration Point, WL,
RL, nWR, Read and Write Preamble, Read postamble, and DBI Enables.
8. FSP-OP determines which frequency-set-point register values are currently used to specify device operation for the following functions: VREF(CA)
Setting, VREF(CA) Range, VREF(DQ) Setting, VREF(DQ) Range, CA ODT Enable, CA ODT value, DQ ODT Enable, DQ ODT value, DQ Calibration
Point, WL, RL, nWR, Read and Write Preamble, Read postamble, and DBI Enables.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.15. MR14 Register Information (MA[5:0] = 0EH)
Function
VREF(DQ) Setting
for Set Point[0]
OP[7]
OP[6]
RFU
VR(DQ)
OP[5]
Register Type
OP[4]
OP[2]
OP[1]
OP[0]
VREF(DQ)
Operand
OP[5:0]
Read / Write
VREF(DQ) Range
OP[3]
OP[6]
Data
Notes
000000B:
-- Thru –
110010B: See table below
All Others: Reserved
1,2,3,4,
5,6
0B: VREF(DQ) Range[0] enabled
1B: VREF(DQ) Range[1] enabled (default)
1,2,3,4,
5,6
Notes
1. This register controls the VREF(DQ) levels for Frequency-Set-Point[1:0]. Values from either VR(DQ)[0] or VR(DQ)[1] may be selected by setting
OP[6] appropriately.
2. A read (MRR) to this register places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ’s shall be set to ‘0’.
See the section on Mode Register Read Operation.
3. A write to OP[5:0] sets the internal VREF(DQ) level for FSP[0] when MR13 OP[6]=0B, or sets FSP[1] when MR13 OP[6]=1B.
The time required for VREF(DQ) to reach the set level depends on the step size from the current level to the new level.
See the section on VREF(DQ) training for more information.
4. A write to OP[6] switches the LPDDR4-SDRAM between two internal VREF(DQ) ranges. The range (Range[0] or Range[1]) must be selected
when setting the VREF(DQ) register. The value, once set, will be retained until overwritten, or until the next power-on or RESET event.
5. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.
Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this
MR address, or read from with an MRR command to this address.
6. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.
The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of
the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without
affecting device operation.
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
Table 11 - VREF Settings for Range[0] and Range[1]
Function
VREF
Settings
for MR14
Operand
OP[5:0]
Range[0] Values (% of VDDQ)
000000B:
000001B:
000010B:
000011B:
000100B:
000101B:
000110B:
000111B:
001000B:
001001B:
001010B:
001011B:
001100B:
001101B:
001110B:
001111B:
010000B:
010001B:
010010B:
010011B:
010100B:
010101B:
010110B:
010111B:
011000B:
011001B:
15.0%
15.6%
16.2%
16.8%
17.4%
18.0%
18.6%
19.2%
19.8%
20.4%
21.0%
21.6%
22.2%
22.8%
23.4%
24.0%
24.6%
25.1%
25.7%
26.3%
26.9%
27.5%
28.1%
28.7%
29.3%
29.9%
011010B: 30.5%
011011B: 31.1%
011100B: 31.7%
011101B: 32.3%
011110B: 32.9%
011111B: 33.5%
100000B: 34.1%
100001B: 34.7%
100010B: 35.3%
100011B: 35.9%
100100B: 36.5%
100101B: 37.1%
100110B: 37.7%
100111B: 38.3%
101000B: 38.9%
101001B: 39.5%
101010B: 40.1%
101011B: 40.7%
101100B: 41.3%
101101B: 41.9%
101110B: 42.5%
101111B: 43.1%
110000B: 43.7%
110001B: 44.3%
110010B: 44.9%
All Others: Reserved
Range[1] Values (% of VDDQ)
000000B:
000001B:
000010B:
000011B:
000100B:
000101B:
000110B:
000111B:
001000B:
001001B:
001010B:
001011B:
001100B:
001101B:
001110B:
001111B:
010000B:
010001B:
010010B:
010011B:
010100B:
010101B:
010110B:
010111B:
011000B:
011001B:
32.9%
33.5%
34.1%
34.7%
35.3%
35.9%
36.5%
37.1%
37.7%
38.3%
38.9%
39.5%
40.1%
40.7%
41.3%
41.9%
42.5%
43.1%
43.7%
44.3%
44.9%
45.5%
46.1%
46.7%
47.3%
47.9%
011010B: 48.5%
011011B: 49.1%
011100B: 49.7%
011101B: 50.3%
011110B: 50.9%
011111B: 51.5%
100000B: 52.1%
100001B: 52.7%
100010B: 53.3%
100011B: 53.9%
100100B: 54.5%
100101B: 55.1%
100110B: 55.7%
100111B: 56.3%
101000B: 56.9%
101001B: 57.5%
101010B: 58.1%
101011B: 58.7%
101100B: 59.3%
101101B: 59.9%
101110B: 60.5%
101111B: 61.1%
110000B: 61.7%
110001B: 62.3%
110010B: 62.9%
All Others: Reserved
Notes
1,2,3
Notes
1. These values may be used for MR14 OP[5:0] to set the VREF(DQ) levels in the LPDDR4-SDRAM.
2. The range may be selected in the MR14 register by setting OP[7,6] appropriately.
3. The MR14 registers represents either FSP[0] or FSP[1]. Two frequency-set-points each for CA and DQ are provided to allow for
faster switching between terminated and un-terminated operation, or between different high-frequency setting which may use
different terminations values.
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.16. MR15 Register Information (MA[5:0] = 0FH)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Lower Byte Invert Register for DQ Calibration
Function
Register Type
Operand
Data
Notes
The following values may be written for any operand OP[7:0],
and will be applied to the corresponding DQ locations DQ[7:0]
within a byte lane:
Lower Byte Invert
for DQ Calibration
Write-Only
OP[7:0]
1,2,3
0B: Do not invert
1B: Invert the DQ Calibration patterns in MR32 and MR40
Default value for OP[7:0]=55H
Notes
1. This register will invert the DQ Calibration pattern found in MR32 and MR40 for any single DQ, or any combination of DQ’s.
Example: If MR15 OP[7:0]=00010101B, then the DQ Calibration patterns transmitted on DQ[7,6,5,3,1] will not be inverted,
but the DQ Calibration patterns transmitted on DQ[4,2,0] will be inverted.
2. DMI[0] is not inverted, and always transmits the “true” data contained in MR32/MR40.
3. No Data Bus Inversion (DBI) function is enacted during DQ Read Calibration, even if DBI is enabled in MR3-OP[6].
Table 12 - MR15 Invert Register Pin Mapping
Pin
DQ0
DQ1
DQ2
DQ3
DMI0
DQ4
DQ5
DQ6
DQ7
MR15
OP0
OP1
OP2
OP3
No-invert
OP4
OP5
OP6
OP7
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.17. MR16 Register Information (MA[5:0] = 10H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
PASR Bank Mask
Function
Register Type
Operand
Bank[7:0] Mask
Write-Only
OP[7:0]
Data
0B: Bank Refresh enabled (default) : Unmasked
1B: Bank Refresh disabled : Masked
OP[n]
Bank Mask
8-Bank SDRAM
0
xxxxxxx1
Bank 0
1
xxxxxx1x
Bank 1
2
xxxxx1xx
Bank 2
3
xxxx1xxx
Bank 3
4
xxx1xxxx
Bank 4
5
xx1xxxxx
Bank 5
6
x1xxxxxx
Bank 6
7
1xxxxxxx
Bank 7
Notes
1
Notes
1. When a mask bit is asserted (OP[n]=1), refresh to that bank is disabled.
2. PASR bank-masking is on a per-channel basis. The two channels on the die may have different bank masking.
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.18. MR17 Register Information (MA[5:0] = 11H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
PASR Segment Mask
Function
Register Type
Operand
PASR Segment Mask
Write-only
OP[7:0]
Segment
OP[n]
Segment
Mask
Data
Notes
0B: Segment Refresh enabled (default)
1B: Segment Refresh disabled
1
2Gb
4Gb
6Gb
8Gb
12Gb
16Gb
24Gb
32Gb
R12:R10
R13:R11
R14:R12
R14:R12
R15:R13
R15:R13
R16:R14
R16:R14
TBD
TBD
Not
Allowed
110B
R13:R11
R14:R12
R15:R13
R15:R13
R16:R14
R16:R14
(Byte Mode)
(Byte Mode)
(Byte Mode)
(Byte Mode)
(Byte Mode)
(Byte Mode)
0
0
xxxxxxx1
000B
1
1
xxxxxx1x
001B
2
2
xxxxx1xx
010B
3
3
xxxx1xxx
011B
4
4
xxx1xxxx
100B
5
5
xx1xxxxx
101B
6
6
x1xxxxxx
110B
110B
7
7
1xxxxxxx
111B
111B
Not
Allowed
110B
111B
Not
Allowed
110B
111B
111B
Notes
1. This table indicates the range of row addresses in each masked segment. “X” is don’t care for a particular segment.
2. PASR segment-masking is on a per-channel basis. The two channels on the die may have different segment masking.
3. For 6Gb, 12Gb, and 24Gb densities, OP[7:6] must always be LOW (=00B).
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.19. MR18 Register Information (MA[5:0] = 12H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
DQS Oscillator Count - LSB
Function
Register Type
Operand
Data
Notes
DQS Oscillator
(WR Training DQS Oscillator)
Read-only
OP[7:0]
0:255 LSB DRAM DQS Oscillator Count
1,2,3
Notes
1. MR18 reports the LSB bits of the DRAM DQS Oscillator count. The DRAM DQS Oscillator count value is used to train DQS to the
DQ data valid window. The value reported by the DRAM in this mode register can be used by the memory controller to
periodically adjust the phase of DQS relative to DQ.
2. Both MR18 and MR19 must be read (MRR) and combined to get the value of the DQS Oscillator count.
3. A new MPC [Start DQS Oscillator] should be issued to reset the contents of MR18/MR19.
1.4.20. MR19 Register Information (MA[5:0] = 13H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
DQS Oscillator Count - MSB
Function
DQS Oscillator
(WR Training DQS Oscillator)
Register Type
Operand
Data
Notes
Read-only
OP[7:0]
0:255 MSB DRAM DQS Oscillator Count
1,2,3
Notes
1. MR19 reports the MSB bits of the DRAM DQS Oscillator count. The DRAM DQS Oscillator count value is used to train DQS to the
DQ data valid window. The value reported by the DRAM in this mode register can be used by the memory controller to
periodically adjust the phase of DQS relative to DQ.
2. Both MR18 and MR19 must be read (MRR) and combined to get the value of the DQS Oscillator count.
3. A new MPC [Start DQS Oscillator] should be issued to reset the contents of MR18/MR19.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.21. MR20 Register Information (MA[5:0] = 14H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Upper Byte Invert Register for DQ Calibration
Function
Register Type
Operand
Data
Notes
The following values may be written for any operand OP[7:0],
and will be applied to the corresponding DQ locations DQ[15:8]
within a byte lane:
Upper Byte Invert for
DQ Calibration
Write-Only
OP[7:0]
1,2
0B: Do not invert
1B: Invert the DQ Calibration patterns in MR32 and MR40
Default value for OP[7:0]=55H
Notes
1. This register will invert the DQ Calibration pattern found in MR32 and MR40 for any single DQ, or any combination of DQ’s.
Example: If MR20 OP[7:0]=00010101B, then the DQ Calibration patterns transmitted on DQ[15,14,13,11,9] will not be inverted, but the DQ
Calibration patterns transmitted on DQ[12,10,8] will be inverted.
2. DMI[1] is not inverted, and always transmits the “true” data contained in MR32/MR40.
3. No Data Bus Inversion (DBI) function is enacted during DQ Read Calibration, even if DBI is enabled in MR3-OP[6].
Table 13 - MR20 Invert Register Pin Mapping
Pin
DQ8
DQ9
DQ10
DQ11
DMI1
DQ12
DQ13
DQ14
DQ15
MR20
OP0
OP1
OP2
OP3
No-invert
OP4
OP5
OP6
OP7
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.22. MR21 Register Information (MA[5:0] = 15H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
Low Speed
CA Buffer
RFU
OP[2]
OP[1]
OP[0]
RFU
Function
Register Type
Operand
Low Speed CA Buffer
Write-Only
OP[5]
Data
0B: Normal CA buffer (Default)
1B: Low Speed CA buffer
Notes
1,2,3,4,5
,6,7,8
Notes
1. Support for the Low Speed CA Buffer feature enabled by MR21 OP[5] is optional..
2. Low Speed CA Buffer feature can enable lower power for some manufacturers' designs. The maximum clock speed for this mode is 800 MHz.
3. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.
Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR
address.
4. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.
The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of
the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without
affecting device operation.
5. Low Power CA Buffer cannot be enabled prior to full device initialization (completion of Step 9 in power up sequence)
6. Low speed CA buffer is allowed to be enabled only when CA ODT is disabled.
7. Devices not supporting Low Speed CA Buffer will ignore MR21 OP[5] setting.
8. MR21 OP bits other than OP[5] is highly recommended to set “0” since the other OP can be used with DRAM internal purpose.
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.23. MR22 Register Information (MA[5:0] = 16H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
x8 ODTD
[15:8]
x8 ODTD
[7:0]
ODTD-CA
ODTE-CS
ODTE-CK
Function
Register
Type
SoC ODT
(Controller ODT Value for
VOH calibration
ODTE-CK
(CK ODT enabled for nonterminating rank)
OP[2]
Operand
OP[2:0]
OP[1]
OP[0]
SOC ODT
Data
000B:
001B:
010B:
011B:
100B:
101B:
110B:
111B:
Disable (Default)
RZQ/1(illegal if MR3
RZQ/2
RZQ/3(illegal if MR3
RZQ/4
RZQ/5(illegal if MR3
RZQ/6(illegal if MR3
RFU
Notes
OP[0]=0B)
OP[0]=0B)
1,2,3
OP[0]=0B)
OP[0]=0B)
OP[3]
ODT bond PAD is ignored
0B: ODT-CK Enable (Default)
1B: ODT-CK Disable
2,3,4
ODTE-CS
(CS ODT enable for nonterminating rank)
OP[4]
ODT bond PAD is ignored
0B: ODT-CS Enable (Default)
1B: ODT-CS Disable
2,3,4
ODTD-CA
(CA ODT termination disable)
OP[5]
ODT bond PAD is ignored
0B: ODT-CA Enable (Default)
1B: ODT-CA Disable
2,3,4
OP[6]
Byte mode device (x8 only), lower[7:0] byte selected device
0B: ODT-CS/CA/CLK follows MR11 OP[6:4]& MR22
OP[5:3] (default)
1B: ODT-CS/CA/CLK Disabled
4,5,7
OP[7]
Byte mode device (x8 only), upper[15:8] byte selected device
0B: ODT-CS/CA/CLK follows MR11 OP[6:4]& MR22
OP[5:3] (default)
1B: ODT-CS/CA/CLK Disabled
4,6,7
Write
x8 ODTD[7:0]
(CA/CLK ODT termination
disable
[7:0] Lower byte select)
x8 ODTD[15:8]
(CA/CLK ODT termination
disable
[15:8] upper byte select)
Notes
1. All values are “typical”.
2. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.
Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR
address, or read from with an MRR command to this address.
3. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.
The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of
the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without
affecting device operation.
4. The ODT_CA pin is ignored by LPDDR4X devices. The ODT_CA pin shall be connected to either VDD2 or VSS. CA/ CS/ CK ODT is fully controlled
through MR11 and MR22. Before enabling CA termination via MR11, all ranks should have appropriate MR22 termination settings programmed.
5. To ensure proper operation for x8_2ch devices, OP[6] disabled CS/CA/CLK ODT of lower byte selected device regardless and MR22 OP[5:0]
settings.
6. To ensure proper operation for x8_2ch devices, OP[7] disabled CS/CA/CLK ODT of upper byte selected device regardless MR11 and MR22
OP[5:0] settings.
7. Upper [15:8] and lower [7:0] bytes are assigned by the manufacturer and cannot be assigned by the application.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
Table 14 - LPDDR4X Byte Mode Device (MR11 OP[6:4] ≠ 000B Case)
MR22
LPD4X
ODTD
byte mode
ODT
CA
ODT
CS
ODT
CK
ODT PAD Ignore
CA
CS
CK
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
0B
1B
0B
1B
0Bz
1B
0
0
0
0
0
T
T
T
T
T
T
0
0
0
0
1
T
T
T
T
0
0
0
1
0
T
T
T
T
0
0
0
1
1
T
T
0
0
1
0
0
T
T
T
T
0
0
1
0
1
T
T
0
0
1
1
0
T
T
0
0
1
1
1
0
1
0
0
0
T
T
0
1
0
0
1
T
T
0
1
0
1
0
T
0
1
0
1
1
T
0
1
1
0
0
T
0
1
1
0
1
T
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
T
T
1
0
0
0
1
T
T
1
0
0
1
0
T
1
0
0
1
1
T
1
0
1
0
0
T
1
0
1
0
1
T
1
0
1
1
0
1
0
1
1
1
T
T
T
T
T
T
T
T
Notes
1. T means “terminated” condition. Blank is “un-terminated”
Rev 1.2 / Mar. 2020 / SK hynix Confidential
44
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.24. MR23 Register Information (MA[5:0] = 17H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
DQS oscillator run time setting
Function
DQS
oscillator
run time
Register Type
Operand
Data
Notes
DQS timer stops via MPC Command (Default)
DQS timer stops automatically at 16th clocks after timer start
DQS timer stops automatically at 32nd clocks after timer start
DQS timer stops automatically at 48th clocks after timer start
DQS timer stops automatically at 64th clocks after timer start
-------------- Thru ---------------------00111111B: DQS timer stops automatically at (63X16)th clocks after timer
start
01XXXXXXB: DQS timer stops automatically at 2048th clocks after timer start
10XXXXXXB: DQS timer stops automatically at 4096th clocks after timer start
11XXXXXXB: DQS timer stops automatically at 8192nd clocks after timer start
1, 2
00000000B:
00000001B:
00000010B:
00000011B:
00000100B:
Write-Only
OP[7:0]
Notes
1. MPC command with OP[6:0]=1001101B (Stop DQS Interval Oscillator) stops DQS interval timer in case of MR23 OP[7:0] =
00000000B.
2. MPC command with OP[6:0]=1001101B (Stop DQS Interval Oscillator) is illegal with non-zero values in MR23 OP[7:0].
Rev 1.2 / Mar. 2020 / SK hynix Confidential
45
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.25. MR24 Register Information (MA[5:0] = 18H)
OP[7]
TRR Mode
Function
OP[6]
OP[5]
OP[4]
MAC Value
Operand
TRR Mode BAn
Data
OP[3]
0B: OP[2:0] define MAC value
1B: Unlimited MAC value (note 2, note 3)
Write-Only
OP[7]
000B:
001B:
010B:
011B:
100B:
101B:
110B:
111B:
Bank
Bank
Bank
Bank
Bank
Bank
Bank
Bank
OP[0]
MAC Value
OP[2:0]
OP[6:4]
TRR Mode
OP[1]
000B: Unknown when bit OP3 =0 (note 1)
Unlimited when bit OP3=1 (note 2)
001B: 700K
010B: 600K
011B: 500K
100B: 400K
101B: 300K
110B: 200K
111B: Reserved
Read-Only
Unlimited MAC
OP[2]
Unlimited
MAC
TRR Mode Bank Address
Register Type
OP[3]
Notes
0
1
2
3
4
5
6
7
0B: Disabled (default)
1B: Enabled
Notes
1. Unknown means that the device is not tested for tMAC and pass/fail value in unknown.
2. There is no restriction to number of activates.
3. MR24 OP [2:0] is set to zero.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.26. MR25 Register Information (MA[5:0] = 19H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Bank 0
Function
Register Type
Operand
PPR Resource
Read-only
OP[7:0]
Data
Notes
0B: PPR Resource is not available
1B: PPR Resource is available
1.4.27. MR26:30 Register Information (MA[5:0] = 1AH:1FH)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Reserved
1.4.28. MR31 Register Information (MA[5:0] = 1AH:1FH)
OP[7]
OP[6]
OP[5]
OP[4]
Byte mode Vref Selection
Function
Byte mode Vref Selection
Lower Byte
Byte mode Vref Selection
Upper Byte
Register Type
OP[3]
OP[2]
OP[1]
OP[0]
RFU
Operand
Data
Notes
OP[6]
0B : x16 device and no Byte mode selection (Default)
1B : Disable to updated MR12/MR14 for lower byte
1,2,3
OP[7]
OB : x16 device and no Byte mode selection (Default)
1B : Disable to updated MR12/MR14 for upper byte
1,2,3
Write-only
Notes
1. The Byte mode Vref selection is optional. Please consult with vendors for the availability to support feature.
2. When Byte mode Vref selection in applied, the non-targeted byte is required to disable to updated VrefCA and VrefDQ setting, assigned in MR12
and MR14 OP[6L0], for the other targeted byte.
- In order to update MR12/MR14 setting only for upper byte, it is required to disable byte mode selection on lower byte,
as applying MR31 OP[7:6] = 01B.
- In order to update MR12/MR14 setting only for lower byte, it is required to disable byte mode selection on upper byte,
as applying MR31 OP[7:6] = 10B.
- When OP[7:6] = 00B is applied, both lower byte and upper byte will be updated.
3. When the configuration is not composed of byte mode device, MR31 OP[7:6] shall be the default value, 00B.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
47
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.29. MR32 Register Information (MA[5:0] = 20H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
DQ Calibration Pattern “A” (default = 5AH)
Function
Return DQ Calibration
Pattern MR32 + MR40
Register Type
Write-Only
Operand
Data
Notes
OP[7:0]
XB: An MPC command with OP[6:0]=0000011B causes
the device to return the DQ Calibration Pattern contained
in this register and (followed by) the contents of MR40. A
default pattern “5AH” is loaded at power-up or RESET, or
the pattern may be overwritten with a MRW to this
register. The contents of MR15 and MR20 will invert the
data pattern for a given DQ
(See MR15 for more information)
1.4.30. MR33:39 Register Information (MA[5:0] = 21H:27H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[2]
OP[1]
OP[0]
Do Not Use
1.4.31. MR40 Register Information (MA[5:0] = 28H)
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[0]
DQ Calibration Pattern “B” (default = 3CH)
Function
Register Type
Operand
Data
Notes
Return DQ Calibration
Pattern MR32 + MR40
Write-Only
OP[7:0]
XB: A default pattern “3CH” is loaded at power-up or RESET, or
the pattern may be overwritten with a MRW to this register.
See MR32 for more information.
1,2,3,4
Notes
1. The pattern contained in MR40 is concatenated to the end of MR32 and transmitted on DQ[15:0] and DMI[1:0] when DQ Read
Calibration is initiated via a MPC command. The pattern transmitted serially on each data lane, organized “little endian” such
that the low-order bit in a byte is transmitted first. If the data pattern in MR40 is 27H, then the first bit transmitted with be a
‘1’, followed by ‘1’, ‘1’, ‘0’, ‘0’, ‘1’, ‘0’, and ‘0’. The bit stream will be 00100111B.
2. MR15 and MR20 may be used to invert the MR32/MR40 data patterns on the DQ pins. See MR15 and MR22 for more information.
Data is never inverted on the DMI[1:0] pins.
3. The data pattern is not transmitted on the DMI[1:0] pins if DBI-RD is disabled via MR3-OP[6].
4. No Data Bus Inversion (DBI) function is enacted during DQ Read Calibration, even if DBI is enabled in MR3-OP[6].
Rev 1.2 / Mar. 2020 / SK hynix Confidential
48
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
1.4.32. MR51 Register Information (MA[5:0] = 33H)
OP[7]
OP[6]
OP[5]
RFU
Function
Register Type
Single-Ended RDQS
Single-Ended WDQS
Write-Only
Single-Ended Clock
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Single-Ended
Clock
Single-Ended
WDQS
Single-Ended
RDQS
RFU
Operand
Data
Notes
OP[1]
0B: Differential Read DQS (Default)
1B: Single Ended Read DQS
1,2,3,4,5
OP[2]
0B: Differential Write DQS (Default)
1B: Single Ended Write DQS
1,2,3,4,6
OP[3]
0B: Differential Clock : CK_t/CK_c (Default)
1B: Single Ended Clock : CK_t only
1,2,3,4,7
Notes
1. The features described in MR51 are optional. Please check the vendor for the availability.
2. Device support for single ended mode features (MR51 OP[3:1]) is indicated in MR0 OP[5].
3. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.
Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this
MR address.
4. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.
The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state
of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without
affecting device operation.
5. When single ended RDQS mode is enabled (MR51 OP[1] =1b), DRAM drives Read DQSB low or Hi-Z.
6. When single ended WDQS mode is enabled (MR51 OP[2] =1b), Write DQSB is required to be at a valid logic level. A valid Write DQSB signal
will meet this requirement.
7. When single ended Clock mode is enabled (MR51 OP[3] =1b), CK_c is required to be at a valid logic level. A valid CK_c signal will meet this
requirement.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
2. Command Definitions and Timing Diagrams
2.1. Activate Command
The ACTIVATE command is composed of two consecutive commands, Activate-1 command and Activate-2. Activate-1 command is
issued by holding CS HIGH, CA0 HIGH and CA1 LOW at the first rising edge of the clock and Activate-2 command issued by holding
CS HIGH, CA0 HIGH and CA1 HIGH at the first rising edge of the clock. The bank addresses BA0, BA1 and BA2 are used to select
desired bank. Row addresses are used to determine which row to activate in the selected bank. The ACTIVATE command must be
applied before any READ or WRITE operation can be executed. The device can accept a READ or WRITE command at tRCD after the
ACTIVATE command is issued. After a bank has been activated it must be precharged before another ACTIVATE command can be
applied to the same bank. The bank active and precharge times are defined as tRAS and tRP respectively. The minimum time interval
between ACTIVATE commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval
between ACTIVATE commands to different banks is tRRD.
CK_t
CK_c
CS
CA0-5
Bank A
RowAddrRowAddrRowAddrRowAddr
Valid
Valid
Bank A
Bank B
RowAddrRowAddrRowAddrRowAddr Col Addr Col Addr Col Addr Col Addr
Valid
Valid
Bank A
Bank
Addr.
tRRD
Valid
Valid
Valid
Valid
Bank A
RowAddrRowAddrRowAddrRowAddr
tRP
tRCD
CMD
Activate-1
Activate-2
Valid
Activate-1
Activate-2
Read-1
CAS-2
Valid
Precharge
Valid
Valid
Activate-1
Activate-2
tRC
tRAS
Figure 4 - Activate Command Timing Example
Notes
1. A PRECHARGE command uses tRPab timing for all-bank PRECHARGE and tRPpb timing for single-bank PRECHARGE. In this figure,
tRP is used to denote either all-bank PRECHARGE or a single-bank PRECHARGE.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
2.2. 8-Bank Device Operation
Certain restrictions on operation of the 8-bank LPDDR4 devices must be observed. There are two rules: One rule restricts the number
of sequential ACTIVATE commands that can be issued; the other provides more time for RAS precharge for a PRECHARGE ALL command. The rules are as follows:
8 bank device Sequential Bank Activation Restriction: No more than 4 banks may be activated (or refreshed, in the case of
REFpb) in a rolling tFAW window. The number of clocks in a tFAW period is dependent upon the clock frequency, which may vary. If
the clock frequency is not changed over this period, converting clocks is done by dividing tFAW[ns] by tCK[ns], and rounding up to
the next integer value. As an example of the rolling window, if RU(tFAW/tCK) is 10 clocks, and an ACTIVATE command is issued in
clock n, no more than three further ACTIVATE commands can be issued at or between clock n + 1 and n + 9. REFpb also counts as
bank activation for purposes of tFAW. If the clock frequency is changed during the tFAW period, the rolling tFAW window may be calculated in clock cycles by adding up the time spent in each clock period. The tFAW requirement is met when the previous n clock
cycles exceeds the tFAW time.
The 8-Bank Device Precharge-All Allowance: tRP for a PRECHRGE ALL command must equal tRPab, which is greater than
tRPpb.
CK_t
CK_c
CS
CA0-5
CMD
Bank A
RowAddrRowAddrRowAddrRowAddr VALID
Activate-1
Activate-2
VALID
VALID
Bank B
VALID
RowAddrRowAddrRowAddrRowAddr
Activate-1
Activate-2
Bank C
VALID RowAddr
RowAddrRowAddrRowAddr VALID
VALID
Activate-1
Bank D
VALID RowAddr
RowAddrRowAddrRowAddr VALID
VALID
Activate-2
Activate-1
Activate-2
Bank E
VALID RowAddr
RowAddrRowAddrRowAddr
VALID
Activate-1
Activate-2
tRRD
tRRD
tRRD
tRRD
tFAW
Figure 5 - tFAW Timing Example
Rev 1.2 / Mar. 2020 / SK hynix Confidential
51
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
2.3. Read and Write Access Operations
After a bank has been activated, a read or write command can be executed. This is accomplished by asserting CKE asynchronously,
with CS and CA[5:0] set to the proper state (see Command Truth Table) at a rising edge of CK.
The LPDDR4-SDRAM provides a fast column access operation. A single Read or Write command will initiate a burst read or write
operation, where data is transferred to/from the DRAM on successive clock cycles. Burst interrupts are not allowed, but the optimal
burst length may be set on the fly (see Command Truth Table).
Rev 1.2 / Mar. 2020 / SK hynix Confidential
52
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
2.4. Read Preamble and Postamble
The DQS strobe for the LPDDR4-SDRAM requires a pre-amble prior to the first latching edge (the rising edge of DQS_t with DATA
"valid"), and it requires a post-amble after the last latching edge. The pre-amble and post-amble lengths are set via mode register
writes (MRW).
For READ operations the pre-amble is 2*tCK, but the pre-amble is static (no-toggle) or toggling, selectable via mode register.
LPDDR4 will have a DQS Read post-amble of 0.5*tCK (or extended to 1.5*tCK). Standard DQS postamble will be 0.5*tCK driven by
the DRAM for Reads. A mode register setting instructs the DRAM to drive an additional (extended) one cycle DQS Read post-amble.
The drawings below show examples of DQS Read post-amble for both standard (tRPST) and extended (tRPSTE ) post-amble operation.
T0
T1
RD-1
RD-1
T2
T3
T4
Ta0
Ta1
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
Tb6
Tc0
Tc1
Tc2
Tc3
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Tc4
CK_c
CK_t
COMMAND
CAS-2 CAS-2
RL
DES
tDQSCK
tRPRE
DQS_c
DQS_t
tDQSQ
DQ
Note
tRPST
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n10 n11 n12 n13 n14 m15
Figure 6 - DQS Read Preamble and Postamble: Toggling Preamble and 0.5nCK Postamble
Notes.
1. BL = 16, Preamble = Toggling, Postamble = 0.5nCK
2. DQS and DQ terminated VSSQ.
3. DQS_t/DQS_c is “don’t care” prior to the start of tRPRE.
No transition of DQS is impliend, as DQS_t/DQS_c can be HIGH, LOW or Hi-z prior to tRPRE.
T0
T1
RD-1
RD-1
T2
T3
T4
Ta0
Ta1
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
Tb6
Tc0
Tc1
Tc2
Tc3
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Tc4
CK_c
CK_t
COMMAND
CAS-2 CAS-2
RL
tDQSCK
DES
Extended tCK
Postamble
tRPRE
DQS_c
DQS_t
tDQSQ
tRPSTE
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n10 n11 n12 n13 n14 m15
DQ
Figure 7 - DQS Read Preamble and Postamble: Static Preamble and 1.5nCK Postamble
Notes.
1. BL = 16, Preamble = Toggling, Postamble = 1.5nCK (Extended)
2. DQS and DQ terminated VSSQ.
3. DQS_t/DQS_c is “don’t care” prior to the start of tRPRE. No transition of DQS is impliend, as DQS_t/DQS_c can be HIGH, LOW or Hi-z prior to
tRPRE.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
53
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
2.5. Burst Read Operation
A burst Read command is initiated with CKE, CS, and CA[5:0] asserted to the proper state at the rising edge of CK, as defined by the
Command Truth Table. The command address bus inputs determine the starting column address for the burst. The two low-order
address bits are not transmitted on the CA bus and are implied to be “0”, so that the starting burst address is always a multiple of
four (ex. 0x0, 0x4, 0x8, 0xC). The read latency (RL) is defined from the last rising edge of the clock that completes a read command
(Ex: the second rising edge of the CAS-2 command) to the rising edge of the clock from which the tDQSCK delay is measured. The
first valid data is available RL * tCK + tDQSCK + tDQSQ after the rising edge of Clock that completes a read command. The data
strobe output is driven tRPRE before the first valid rising strobe edge. The first data-bit of the burst is synchronized with the first
valid (i.e. post-preamble) rising edge of the data strobe. Each subsequent data out appears on each DQ pin, edge-aligned with the
data strobe. At the end of a burst the DQS signals are driven for another half cycle post-amble, or for a 1.5-cycle postamble if the
programmable post-amble bit is set in the mode register. The RL is programmed in the mode registers. Pin timings for the data
strobe are measured relative to the cross-point of DQS_t and DQS_c.
CK_t
CK_c
CA0-5
tCCD
tCCD
Read1
BL
Bank
Col AP
CAS2
Col
Col
Valid
Valid
Read1
BL
Bank
Col AP
CAS2
Col
Col
Valid
Valid
RL
CMD
Read-1
Bank0
CAS-2
Col A
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
RL
Read-1
Bank0
Valid
CAS-2
Col B
Valid
Valid
Valid
Valid
Valid
Valid
Valid
tDQSCK
Valid
Valid
Valid
tDQSCK
DQS_t
DQS_c
tRPSTE
tRPRE
DQ[15:0]
/DMI[1:0]
VAL
VAL
VAL
VAL
VAL
VAL BANK0,
VAL VAL
VAL VAL Col-A
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL BANK0,
VAL
VAL
VAL VAL Col-B
VAL
VAL
VAL
VAL
VAL
VAL
Figure 8 - Burst Read Timing. BL=16, Toggling tRPRE, Extended tRPST
Notes
1. DES commands are shown for ease of illustration; other commands may be valid at these times.
CK_t
CK_c
CA0-5
Read1
BL
Bank
Col AP
CAS2
Col
Col
Valid
Valid
Valid
Valid
Valid
Valid
Write1
BL
Bank
Col AP
CAS2
Col
Col
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
BL/2
RL
WL
CMD
Read-1
CAS-2
Valid
Valid
Valid
Write or
Masked Write
CAS-2
Valid
Valid
Valid
Valid
Valid
tDQSCK
tDQSS
DQS_t
DQS_c
tRPSTE
tRPRE
DQ[15:0]
/DMI[1:0]
D out
VAL
VAL
VAL
VAL
VAL
D inVAL
VAL
VAL
Figure 9 - Burst Read followed by Burst Write. BL=16, Non-toggling tRPRE, Extended tRPST
Notes
1. DES commands are shown for ease of illustration; other commands may be valid at these times.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
54
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
The minimum time from a Burst Read command to a Write or MASK WRITE command is defined by the read latency (RL) and the burst length (BL). Minimum READ-to-WRITE
or MASK WRITE latency is defined with tRTW paramter and it is as following equation:
DQ ODT Disabled case; MR11 OP[2:0]=000b
tRTW = RL + RU(tDQSCK(max)/tCK) + BL/2 - WL + tWPRE + RD(tRPST)
DQ ODT Enabled case; MR11 OP[2:0]≠000b
tRTW = RL + RU(tDQSCK(max)/tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon,min/tCK) + 1
CK_t
CK_c
CA0-5
Read1 Bank
Col AP
BL
CAS2
Col
Col
Valid
Valid
Read1 Bank CAS2
Col AP Col
BL
Col
Read-1
Bank0
CAS-2
Col A
Valid
Valid
Valid
RL
CMD
tCCD
tCCD
tCCD
Read1 Bank
Col AP
BL
CAS2
Col
Col
RL
Read-1
Bank0
CAS-2
Col B
Valid
Valid
Valid
Read1 Bank
Col AP
BL
Col
Valid
Read-1
Bank1
CAS-2
Col A
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
RL
RL
Read-1
Bank1
CAS-2
Col B
Valid
tDQSCK
tDQSCK
tDQSCK
CAS2
Col
Valid
Valid
Valid
Valid
Valid
Valid
tDQSCK
DQS_t
DQS_c
tRPRE
DQ[15:0]
/DMI[1:0]
tRPSTE
VAL
VAL
VAL
VAL
VAL BANK0,
VAL VAL Col-A
VAL VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VALBANK0,
VAL VAL
VAL
Col-B
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL BANK1,
VAL VAL Col-A
VAL VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL BANK1,
VAL VAL Col-B
VAL VAL
VAL
VAL
VAL
Figure 10 - Seamless Burst Read. BL=16, Toggling tRPRE, Extended tRPST
The seamless Burst READ operation is supported by placing a READ command at every tCCD(min) interval for BL16 (or every 2 x tCCD for BL32). The seamless Burst READ can
access any open bank.
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2.6. Read Timing
The read timing is shown in following figure:
T0
T1
RD-1
RD-1
T2
T3
T4
Ta0
Ta1
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
Tb6
Tb7
Tc0
Tc1
Tc2
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Tc3
CK_c
CK_t
COMMAND
CAS-2 CAS-2
DES
tHZ(DQS)
RL
tDQSCK
tLZ(DQS)
tRPRE
DQS_c
DQS_t
tHZ(DQ)
tDQSQ
tRPST
tLZ(DQ)
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n10 n11 n12 n13 n14 n15
DQ
DMI
Figure 11 - Read Timing
Notes
1. BL = 16, Preamble = Toggling, Postamble = 0.5nCK
2. DQS and DQ terminated VSSQ.
3. Output driver does not turn on before an end point of tLZ(DQS) and tLZ(DQ).
4. Output driver does not turn off before an end point of tHZ(DQS) and tHZ(DQ).
2.6.1. tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation
tHZ and tLZ transitions occur in the same time window as valid data transitions. These parameters are referenced to a specific voltage level that specifies when the device output is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ).
This section shows a method to calculate the point when the device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving
tLZ(DQS), tLZ(DQ), by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long
as the calculation is consistent. The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single ended.
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2.6.2. tLZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment)
CK_t - CK_c crossing at 2nd CAS-2 of Read Command
CK_t
CK_c
tLZ(DQS)
VOH
DQS_c
Vsw2
0.5 x VOH
Vsw1
End point: Extrapolated point
0V
Figure 12 - tLZ(DQS) method for calculating transitions and end point
Notes
1. Conditions for Calibration: Pull Down Driver Ron = 40ohm. VOH = VDDQ/3
2. Termination condition for DQS_t and DQS_c = 50ohm to VSSQ.
3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual VOH Value for tHZ and tLZ
measurements.
CK_t - CK_c crossing at 2nd CAS-2 of Read Command
CK_t
CK_c
tHZ(DQS)
End point: Extrapolated point
VOH
Vsw2
0.5 x VOH
Vsw1
DQS_c
0V
Figure 13 - tHZ(DQS) method for calculating transitions and end point
Notes
1. Conditions for Calibration: Pull Down Driver Ron = 40ohm. VOH = VDDQ/3
2. Termination condition for DQS_t and DQS_c = 50ohm to VSSQ.
3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual VOH Value for tHZ and tLZ
measurements.
Table 15 - Reference voltage for tLZ(DQS), tHZ(DQS) Timing Measurements
Measured Parameter
Symbol
Vsw1 [V]
Vsw2 [V]
DQS_c low-impedance time from CK_t, CK_c
tLZ(DQS)
0.4 x VOH
0.6 x VOH
DQS_c high impedance time from CK_t, CK_c
tHZ(DQS)
0.4 x VOH
0.6 x VOH
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
2.6.3. tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment)
CK_t - CK_c crossing at 2nd CAS-2 of Read Command
CK_t
CK_c
tLZ(DQ)
VOH
DQs
Vsw2
0.5 x VOH
Vsw1
End point: Extrapolated point
Figure 14 - tLZ(DQ) method for calculating transitions and end point
Notes
1. Conditions for Calibration: Pull Down Driver Ron = 40ohm. VOH = VDDQ/3
2. Termination condition for DQ and DMI = 50ohm to VSSQ.
3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances.
Use the actual VOH Value for tHZ and tLZ measurements.
CK_t - CK_c crossing at 2nd CAS-2 of Read Command
CK_t
CK_c
tHZ(DQ)
End point: Extrapolated point
VOH
Vsw2
0.5 x VOH
Vsw1
DQs
0V
Figure 15 - tHZ(DQ) method for calculating transitions and end point
Notes
1. Conditions for Calibration: Pull Down Driver Ron = 40ohm. VOH = VDDQ/3
2. Termination condition for DQ and DMI = 50ohm to VSSQ.
3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances.
Use the actual VOH Value for tHZ and tLZ measurements.
Table 16 - Reference voltage for tLZ(DQS), tHZ(DQS) Timing Measurements
Measured Parameter
Symbol
Vsw1 [V]
Vsw2 [V]
DQ low-impedance time from CK_t, CK_c
tLZ(DQ)
0.4 x VOH
0.6 x VOH
DQ high impedance time from CK_t, CK_c
tHZ(DQ)
0.4 x VOH
0.6 x VOH
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2.6.4. tRPRE Calculation for ATE (Automatic Test Equipment)
Figure 16 - Method for calculating tRPRE transitions and endpoints
Notes
1. Conditions for Calibration: Pull Down Driver Ron = 40ohm, VOH = VDDQ/3
2. Termination condition for DQS_t, DQS_c, DQ and DMI = 50ohm to VSSQ.
3. Preamble = Static
Figure 17 - Method for calculating tRPRE transitions and endpoints 2
Table 17 - Reference Voltage for tRPRE Timing Measurements
Measured Parameter
Measured Parameter Symbol
Vsw1 [V]
Vsw2 [V]
DQS_t, DQS_c differential Read Preamble
tRPRE
0.4 x VOH
0.6 x VOH
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2.6.5. tRPST Calculation for ATE (Automatic Test Equipment)
Figure 18 - Method for calculating tRPST transitions and endpoints
Notes
1. Conditions for Calibration: Pull Down Driver Ron = 40ohm, VOH = VDDQ/3
2. Termination condition for DQS_t, DQS_c, DQ and DMI = 50ohm to VSSQ.
3. Read Postamble: 0.5tCK
4. The method for calculating differential pulse widths for 1.5tCK Postamble is same as 0.5tCK Postamble.
Table 18 - Reference Voltage for tRPST Timing Measurements
Measured Parameter
Measured Parameter Symbol
Vsw1 [V]
Vsw2 [V]
DQS_t, DQS_c differential Read Preamble
tRPST
-(0.7xVOH)
-(0.3xVOH)
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2.7. Write Preamble and Postamble
The DQS strobe for the LPDDR4-SDRAM requires a pre-amble prior to the first latching edge (the rising edge of DQS_t with DATA
"valid"), and it requires a post-amble after the last latching edge. The pre-amble and post-amble lengths are set via mode register
writes (MRW).
For WRITE operations, a 2*tCK pre-amble is required at all operating frequencies.
LPDDR4 will have a DQS Write post-amble of 0.5*tCK or extended to 1.5*tCK. Standard DQS post-amble will be 0.5*tCK driven by
the memory controller for Writes. A mode register setting instructs the DRAM to drive an additional (extended) one cycle DQS Write
post-amble. The drawings below show examples of DQS Write post-amble for both standard (tWPST) and extended (tWPSTE ) postamble operation.
T0
T1
T2
T3
Valid
Valid
Valid
Valid
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
Tb6
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Tb7
CK_c
CK_t
CKE
CS
CA
COMMAND
Write-1
CAS-2
WL
tDQSS
tWPRE
DES
tWPST
tDQS2DQ
Din
n0
Din
n1
BL/2
Din
n2
Din
n3
Din
n8
Din
n9
Din
n10
Din
n11
Din
n12
Din
n13
Din
n14
Din
n15
Figure 19 - DQS Write Preamble and Postamble; 0.5nCK Postamble
Notes
1. BL = 16, Postamble = 0.5nCK
2. DQS and DQ terminated VSSQ
3. DQS_t/DQS_c is “don’t care” prior to the start of tWPRE.
No transition of DQS is implied, as DQS_t/DQS_c can be HIGH, LOW or Hi-Z prior to tWPRE.
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T0
T1
T2
T3
Valid
Valid
Valid
Valid
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Tb0
Tb1
Tb2
DES
DES
DES
DES
DES
DES
DES
DES
DES
Tb3
Tb4
Tb5
Tb6
DES
DES
DES
DES
Tb7
CK_c
CK_t
CKE
CS
CA
COMMAND
Write-1
CAS-2
DES
WL
tDQSS
tWPRE
DES
tWPST
tDQS2DQ
Din
n0
Din
n1
BL/2
Din
n2
Din
n3
Din
n8
Din
n9
Din
n10
Din
n11
Din
n12
Din
n13
Din
n14
Din
n15
Figure 20 - DQS Write Preamble and Postamble: 1.5nCK Postamble
Notes
1. BL = 16, Postamble = 1.5nCK
2. DQS and DQ terminated VSSQ
3. DQS_t/DQS_c is “don’t care” prior to the start of tWPRE.
No transition of DQS is implied, as DQS_t/DQS_c can be HIGH, LOW or Hi-Z prior to tWPRE.
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2.8. Burst Write Operation
A burst WRITE command is initiated with CKE, CS, and CA[5:0] asserted to the proper state at the rising edge of CK, as defined by
the Command Truth Table. Column addresses C[3:2] should be driven LOW for Burst WRITE commands, and column addresses
C[1:0] are not transmitted on the CA bus (and are assumed to be zero), so that the starting column burst address is always aligned
with a 32B boundary. The write latency (WL) is defined from the last rising edge of the clock that completes a write command (Ex:
the second rising edge of the CAS-2 command) to the rising edge of the clock from which tDQSS is measured. The first valid “latching” edge of DQS must be driven WL * tCK + tDQSS after the rising edge of Clock that completes a write command.
The LPDDR4-SDRAM uses an un-matched DQS-DQ path for lower power, so the DQS-strobe must arrive at the SDRAM ball prior to
the DQ signal by the amount of tDQS2DQ. The DQS-strobe output is driven tWPRE before the first valid rising strobe edge. The
tWPRE, write pre-amble, is required to be 2 x tCK. The DQS-strobe must be trained to arrive at the DQ pad center-aligned with the
DQ-data. The DQ-data must be held for tDIVW (data input valid window) and the DQS must be periodically trained to stay centered
in the tDIVW window to compensate for timing changes due to temperature and voltage variation. Burst data is captured by the
SDRAM on successive edges of DQS until the 16 or 32 bit data burst is complete. The DQS-strobe must remain active (toggling) for
tWPST (WRITE post-amble) after the completion of the burst WRITE. After a burst WRITE operation, tWR must be satisfied before a
PRECHARGE command to the same bank can be issued. Pin input timings are measured relative to the crosspoint of DQS_t and
DQS_c.
T0
T1
T2
T3
BL
BA0,
CA, AP
CA
CA
T4
Ta1
Ta0
Ta2
Ta3
Ta5
Ta4
Ta6
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Valid
BA0
Tc3
Tc4
Td0
Td1
Td2
Td3
Tb4
Td5
RA
BA0,
RA
RA
RA
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
DES
DES
DES
WL
DES
DES
DES
DES
DES
DES
BL/2 + 1 Clock
tDQSS (Min)
tWPRE
Precharge
DES
tWR
tDSS
DES
DES
DES
DES
ACT-1
ACT-2
tRP
tDSH
tDSS
DQS_c
DES
tDSH
tWPST
DQS_t
tDQS2DQ
Din Din Din Din Din Din Din Din Din Din
n0 n1 n2 n3 n4 n5 n12 n13 n14 n15
DQ
tWPRE
tDQSS (Max)
DQS_c
DQS_t
DQ
N t
tDQS2DQ
Din Din Din Din Din Din Din Din Din Din
n0 n1 n2 n3 n4 n11 n12 n13 n14 n15
Figure 21 - Burst Write Operation
Notes
1. BL=16, Write Postamble = 0.5nCK, DQ/DQS: VSSQ termination
2. Din n = data-in to columnm.n
3. The minimum number of clock cycles from the burst write command to the burst read command for any bank is [WL + 1 + BL/2 + RU(tWR/tCK)].
4. tWR starts at the rising edge of CK after the last latching edge of DQS.
5. DES commands are shown for ease of illustration; other commands may be valid at these times.
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T0
T1
T2
T3
BL
BA0,
CA, AP
CA
CA
T4
Ta1
Ta0
Ta2
Ta3
Ta4
Ta5
Ta6
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
BL
BA0,
CA, AP
CA
CA
Tc7
Tc8
Tc9
Tc10
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
DES
DES
DES
WL
DES
DES
DES
DES
DES
DES
BL/2 + 1 Clock
tDQSS (Min)
tWPRE
DQS_c
DES
DES
DES
DES
Read-1
CAS-2
tWTR
tDSS
RL
tDSH
tDSS
tDSH
tWPST
DQS_t
tDQS2DQ
Din Din Din Din Din Din Din Din Din Din
n0 n1 n2 n3 n4 n5 n12 n13 n14 n15
DQ
Figure 22 - Burst Write Followed by Burst Read
Notes
1. BL=16, Write Postamble = 0.5nCK, DQ/DQS: VSSQ termination
2. Din n = data-in to column m,n.
3. The minimum number of clock cycles from the burst write command to the burst read command for any bank is
[WL + 1 + BL/2 + RU(tWTR/tCK)].
4. tWTR starts at the rising edge of CK after the last latching edge of DQS.
5. DES commands are shown for ease of illustration; other commands may be valid at these times.
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2.9. Write Timing
The write timing is shown in the following figure
T0
T1
T2
T3
BL
BA0,
CA, AP
CA
CA
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
DES
DES
DES
DES
DES
DES
DES
DES
Tb0
Tb1
Tb2
Tb3
Tb4
DES
DES
DES
DES
DES
Tb5
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
WL
tDQSS (Min)
tWPRE
tDSS
tDSH
tDSS
DQS_c
tDSH
tWPST
DQS_t
tDQS2DQ
Din Din Din Din Din Din Din Din Din Din
n0 n1 n2 n3 n4 n5 n12 n13 n14 n15
DQ
tDQSS (Max)
tWPRE
tDQSH
tDQSL
DQS_c
DQS_t
DQ
tDQS2DQ
Din Din Din Din Din Din Din Din Din Din
n0 n1 n2 n3 n4 n11 n12 n13 n14 n15
Figure 23 - Write Timing
Notes
1. BL = 16, Write Postamble = 0.5nCK
2. Din n = data-in to column m,n.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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2.9.1. tWPRE Calculation for ATE (Automated Test Equipment)
The method for calculating differential pulse widths for tWPRE is shown in the following figure.
CK_t
VrefCA
CK_c
Resulting differential signal
relevant for tWPRE specification
Vsw2
Vsw1
DQS_t - DQS_c
0V
Begin point:
Extrapolated point
tWPRE
Figure 24 - Method for calculating tWPRE transitions and endpoints
Notes
1. Termination condition for DQS_t, DQS_c, DQ and DMI = 50ohm to VSSQ.
Table 19 - Reference Voltage for tWPRE Timing Measurements
Measured Parameter
Symbol
Vsw1 [V]
Vsw2 [V]
DQS_t, DQS_c differential Write Preamble
tWPRE
VIHL_AC x 0.3
VIHL_AC x 0.7
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2.9.2. tWPST Calculation for ATE (Automatic Test Equipment)
The method for calculating differential pulse widths for tWPST is shown in the following figure.
CK_t
VrefCA
CK_c
Resulting differential signal
relevant for tWPST specification
0V
Vsw2
Vsw1
DQS_t - DQS_c
End point: Extrapolated point
tWPST
Figure 25 - Method for calculating tWPST transitions and endpoints
Notes
1. Termination condition for DQS_t, DQS_c, DQ and DMI = 50ohm to VSSQ.
2. Write Postamble; 0.5tCK
3. The method for calculating differential pulse widths for 1.5 tCK Postamble is same as 0.5 tCK Postamble.
Table 20 - Reference Voltage for tWPRE Timing Measurements
Measured Parameter
Symbol
Vsw1 [V]
Vsw2 [V]
DQS_t, DQS_c differential Write Preamble
tWPST
- (VIHL_AC x 0.7)
- (VIHL_AC x 0.3)
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2.10. Postamble and Preamble merging behavior
The DQS strobe for the device requires a preamble prior to the first latching edge (the rising edge of DQS_t with data valid), and it
requires a postamble after the last latching edge. The preamble and postamble options are set via Mode Register Write commands.
In Read to Read or Write to Write operations with tCCD=BL/2, postamble for 1st command and preamble for 2nd command will disappear to create consecutive DQS latching edge for seamless burst operations.
But in the case of Read to Read or Write to Write operations with command interval of tCCD+1,tCCD+2, etc., they will not completely
disappear because it’s not seamless burst operations.
Timing diagrams in this material describe Postamble and Preamble merging behavior in Read to Read or Write to Write operations
with tCCD+n.
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2.10.1. Read to Read Operation
T0
T1
T2
T3
BA0,
CA, AP CAn
CAn
T4
T7
T8
T9
T10
T11
BA0,
CA, AP CAm
CAm
T12
T13
T14
T15
T16
T17
T18
T19
T20
T26
T27
T28
T29
T30
T31
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
BL
Read-1
CAS-2
BL
DES
DES
Read-1
CAS-2
tCCD = 8
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPST
tRPRE
DQS_c
Hi-Z
DQS_t
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 m0 m1 m12 m13 m14 m15
BL/2 = 8
Hi-Z
BL/2 = 8
Figure 26 - Seamless Reads Operation: tCCD = Min, Preamble = Toggle, 1.5nCK Postamble
Notes
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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T0
T1
T2
T3
BA0,
CA, AP CAn
CAn
T4
T7
T8
T9
T10
T11
T12
BA0,
CA, AP CAm
CAm
T13
T14
T15
T16
T17
T18
T19
T20
T21
T26
T27
T28
T29
T30
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
BL
Read-1
CAS-2
BL
DES
DES
DES
Read-1
CAS-2
tCCD = 9
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPST
DQS_c
Hi-Z
DQS_t
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
BL/2 = 8
Hi-Z
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
Hi-Z
BL/2 = 8
Figure 27 - Consecutive Reads Operation: tCCD = Min+1, Preamble=Toggle, 1.5nCK Postamble
Notes
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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T0
T1
T2
T3
BA0,
CA, AP CAn
CAn
T4
T7
T8
T9
T10
T11
T12
BA0,
CA, AP CAm
CAm
T13
T14
T15
T16
T17
T18
T19
T20
T21
T26
T27
T28
T29
T30
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
BL
Read-1
CAS-2
BL
DES
DES
DES
Read-1
CAS-2
tCCD = 9
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST tRPRE
DQS_c
Hi-Z
DQS_t
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
BL/2 = 8
N t
Hi-Z
tRPST
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
Hi-Z
BL/2 = 8
Figure 28 - Consecutive Reads Operation: tCCD=Min+1, Preamble=Toggle, 0.5nCK Postamble
Notes
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 0.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
71
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BA0,
CA, AP CAn
CAn
T4
T7
T8
T9
T10
T11
T12
BA0,
CA, AP CAm
CAm
T13
T14
T15
T16
T17
T18
T19
T20
T21
T26
T27
T28
T29
T30
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
BL
Read-1
CAS-2
BL
DES
DES
DES
Read-1
CAS-2
tCCD = 9
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPST
DQS_c
Hi-Z
DQS_t
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Hi-Z Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
BL/2 = 8
Hi-Z
BL/2 = 8
Figure 29 - Consecutive Reads Operation: tCCD = Min +1, Preamble = Static, 1.5nCK Postamble
Notes
1. BL = 16 for column n and column m, RL = 6, Preamble = static, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
72
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BA0,
CA, AP CAn
CAn
T4
T7
T8
T9
T10
T11
T12
BA0,
CA, AP CAm
CAm
T13
T14
T15
T16
T17
T18
T19
T20
T21
T26
T27
T28
T29
T30
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
BL
Read-1
CAS-2
BL
DES
DES
DES
Read-1
CAS-2
tCCD = 9
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPRE
tRPST
DQS_c
Hi-Z
DQS_t
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Hi-Z Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
BL/2 = 8
N t
Hi-Z
BL/2 = 8
Figure 30 - Consecutive Reads Operation: tCCD = Min +1, Preamble = Static, 0.5nCK Postamble
Notes
1. BL = 16 for column n and column m, RL = 6, Preamble = static, Postamble = 0.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
73
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BA0,
CA, AP CAn
CAn
T4
T7
T8
T9
T10
T11
T12
T13
BA0,
CA, AP CAm
CAm
T14
T15
T16
T17
T18
T19
T20
T21
T22
T28
T29
T30
T31
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
BL
Read-1
CAS-2
BL
DES
DES
DES
DES
Read-1
CAS-2
tCCD = 10
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPRE
tRPST
DQS_c
Hi-Z
DQS_t
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
Hi-Z
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
BL/2 = 8
Hi-Z
BL/2 = 8
Figure 31 - Consecutive Reads Operation: tCCD = Min +2, Preamble = Toggle, 1.5nCK Postamble
Notes
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
74
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BA0,
CA, AP CAn
CAn
T4
T7
T8
T9
T10
T11
T12
T13
BA0,
CA, AP CAm
CAm
T14
T15
T16
T17
T18
T19
T20
T21
T22
T28
T29
T30
T31
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
BL
Read-1
CAS-2
BL
DES
DES
DES
DES
Read-1
CAS-2
tCCD = 10
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPRE
tRPST
DQS_c
Hi-Z
DQS_t
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
Hi-Z
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
BL/2 = 8
Hi-Z
BL/2 = 8
Figure 32 - Consecutive Reads Operation: tCCD = Min +2, Preamble = Toggle, 0.5nCK Postamble
Notes
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 0.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
75
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BA0,
CA, AP CAn
CAn
T4
T7
T8
T9
T10
T11
T12
T13
BA0,
CA, AP CAm
CAm
T14
T15
T16
T17
T18
T19
T20
T21
T22
T28
T29
T30
T31
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
BL
Read-1
CAS-2
BL
DES
DES
DES
DES
Read-1
CAS-2
tCCD = 10
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPRE
tRPST
DQS_c
Hi-Z
DQS_t
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
Hi-Z
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
BL/2 = 8
Hi-Z
BL/2 = 8
Figure 33 - Consecutive Reads Operation: tCCD = Min +2, Preamble = Static, 1.5nCK Postamble
Notes
1. BL = 16 for column n and column m, RL = 6, Preamble = static, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
76
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BA0,
CA, AP CAn
CAn
T4
T7
T8
T9
T10
T11
T12
T13
BA0,
CA, AP CAm
CAm
T14
T15
T16
T17
T18
T19
T20
T21
T22
T28
T29
T30
T31
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
BL
Read-1
CAS-2
BL
DES
DES
DES
DES
Read-1
CAS-2
tCCD = 10
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPRE
tRPST
DQS_c
Hi-Z
DQS_t
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
Hi-Z
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
BL/2 = 8
Hi-Z
BL/2 = 8
Figure 34 - Consecutive Reads Operation: tCCD = Min +2, Preamble = Static, 0.5nCK Postamble
Notes
1. BL = 16 for column n and column m, RL = 6, Preamble = static, Postamble = 0.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
77
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BA0,
CA, AP CAn
CAn
T4
T7
T8
T9
T10
T11
T13
T14
BA0,
CA, AP CAm
CAm
T12
T15
T16
T17
T18
T19
T20
T21
T22
T23
T29
T30
T31
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
BL
Read-1
CAS-2
BL
DES
DES
DES
DES
DES
Read-1
CAS-2
tCCD = 11
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPRE
tRPST
DQS_c
Hi-Z
DQS_t
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
Hi-Z
BL/2 = 8
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
Hi-Z
BL/2 = 8
Figure 35 - Consecutive Reads Operation: tCCD = Min +3, Preamble = Toggle, 1.5nCK Postamble
Notes
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
78
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BA0,
CA, AP CAn
CAn
T4
T7
T8
T9
T10
T11
T13
T14
BA0,
CA, AP CAm
CAm
T12
T15
T16
T17
T18
T19
T20
T21
T22
T23
T29
T30
T31
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
BL
Read-1
CAS-2
BL
DES
DES
DES
DES
DES
Read-1
CAS-2
tCCD = 11
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPRE
tRPST
DQS_c
Hi-Z
DQS_t
Hi-Z
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
Hi-Z
BL/2 = 8
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
Hi-Z
BL/2 = 8
Figure 36 - Consecutive Reads Operation: tCCD = Min +3, Preamble = Toggle, 0.5nCK Postamble
Notes
1. BL = 16 for column n and column m, RL = 6, Preamble = Toggle, Postamble = 0.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
79
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BA0,
CA, AP CAn
CAn
T4
T7
T8
T9
T10
T11
T13
T14
BA0,
CA, AP CAm
CAm
T12
T15
T16
T17
T18
T19
T20
T21
T22
T23
T29
T30
T31
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
BL
Read-1
CAS-2
BL
DES
DES
DES
DES
DES
Read-1
CAS-2
tCCD = 11
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPRE
tRPST
DQS_c
Hi-Z
DQS_t
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
Hi-Z
BL/2 = 8
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
Hi-Z
BL/2 = 8
Figure 37 - Consecutive Reads Operation: tCCD = Min +3, Preamble = Static, 1.5nCK Postamble
Notes
1. BL = 16 for column n and column m, RL = 6, Preamble = Static, Postamble = 1.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
80
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BA0,
CA, AP CAn
CAn
T4
T7
T8
T9
T10
T11
T13
T14
BA0,
CA, AP CAm
CAm
T12
T15
T16
T17
T18
T19
T20
T21
T22
T23
T29
T30
T31
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
BL
Read-1
CAS-2
BL
DES
DES
DES
DES
DES
Read-1
CAS-2
tCCD = 11
RL = 6
RL = 6
tDQSCK
tDQSCK
tRPRE
tRPST
tRPRE
tRPST
DQS_c
Hi-Z
DQS_t
Hi-Z
Hi-Z
tDQSQ
Hi-Z
DQ
tDQSQ
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
Hi-Z
BL/2 = 8
Dout Dout Dout Dout Dout Dout
m0 m1 m12 m13 m14 m15
Hi-Z
BL/2 = 8
Figure 38 - Consecutive Reads Operation: tCCD = Min +3, Preamble = Static, 0.5nCK Postamble
Notes
1. BL = 16 for column n and column m, RL = 6, Preamble = Static, Postamble = 0.5nCK
2. Dout n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
81
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
2.10.2. Write to Write operation
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T5
T6
T7
T8
T9
T10
T11
BL
BA0,
CA
CAm
CAm
T12
T13
T14
T15
T16
T17
T18
T23
T24
T25
T26
T27
T28
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
DES
DES
Write-1
CAS-2
tCCD = 8
WL = 4
WL = 4
tDQSS
tDQSS
tWPST
tWPRE
DQS_c
DQS_t
DQ
Don’t Care
Don’t Care
Don’t Care
tDQS2DQ
tDQS2DQ
Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 m0 m1 m2 m3 m12 m13 m14 m15
BL/2 = 8
Note
Don’t Care
BL/2 = 8
Figure 39 - Seamless Writes Operation: tCCD = Min, 0.5nCK Postamble
Notes
1. BL = 16, Write Postamble = 0.5nCK
2. Din n/m = data-in from column n and column m.
3. The minimum number of clock cycles from the burst write command to the burst write command for any bank is BL/2.
4. DES commands are shown for ease of illustration; other commands may be valid at these times.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
82
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T7
T8
T9
T10
T11
BL
BA0,
CA
CAm
CAm
T12
T13
T14
T15
T16
T17
T23
T24
T25
T31
T32
T33
T34
T35
T36
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
Write-1
DES
CAS-2
tCCD = 8
WL = 12
WL = 12
tDQSS
tDQSS
tWPST
tWPRE
DQS_c
DQS_t
DQ
Don’t Care
Don’t Care
tDQS2DQ
tDQS2DQ
Din Din Din Din Din Din Din Din Din Din Din Din
n0 n1 n2 n13 n14 n15 m0 m1 m2 m13 m14 m15
Don’t Care
ODTLon = 6
DRAM RTT
tODTon.Max
BL/2 = 8
ODT Hi-Z
Don’t Care
BL/2 = 8
ODT On
ODTLoff = 22
ODT Hi-Z
tODToff.Min
Figure 40 - Seamless Writes Operation: tCCD = Min, 1.5nCK Postamble,
533MHz < Clock Freq. ≤ 800MHz, ODT Worst Timing Case
Notes
1. Clock Frequency = 800MHz, tCK(AVG) = 1.25ns
2. BL = 16, Write Postamble = 1.5nCK
3. Din n/m = data-in to column n and column m.
4. The minimum number of clock cycles from the burst write command to the burst write command for any bank is BL/2.
5. DES commands are shown for ease of illustration; other commands may be valid at these times.
Rev 1.2 / Mar. 2020 / SK hynix Confidential
83
H9HCNNNFAMMLXR
LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T7
T8
T9
T10
T11
BL
BA0,
CA
CAm
CAm
T12
T15
T16
T17
T18
T19
T25
T26
T27
T33
T34
T35
T36
T37
T38
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
Write-1
tCCD = 8
CAS-2
WL = 14
WL = 14
tDQSS
tDQSS
tWPST
tWPRE
DQS_c
DQS_t
DQ
Don’t Care
Don’t Care
Don’t Care
tDQS2DQ
tDQS2DQ
Din Din Din Din Din Din Din Din Din Din Din Din
n0 n1 n2 n13 n14 n15 m0 m1 m2 m13 m14 m15
BL/2 = 8
Don’t Care
BL/2 = 8
Figure 41 - Seamless Writes Operation: tCCD = Min, 1.5nCK Postamble
Notes
1. BL = 16, Write Postamble = 1.5nCK
2. Din n/m = data-in from column n and column m.
3. The minimum number of clock cycles from the burst write command to the burst write command for any bank is BL/2.
4. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T8
T9
T10
T11
T12
BL
BA0,
CA
CAm
CAm
T13
T14
T15
T16
T17
T23
T24
T25
T26
T32
T33
T34
T35
T36
T36
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
Write-1
CAS-2
tCCD = 9
WL = 12
WL = 12
tDQSS
tDQSS
tWPST
tWPRE
DQS_c
DQS_t
DQ
Don’t Care
Don’t Care
tDQS2DQ
tDQS2DQ
Din Din Din Din Din Din Dont’ Care Din Din Din Din Din Din
m0 m1 m2 m13 m14 m15
n0 n1 n2 n13 n14 n15
Don’t Care
BL/2 = 8
Don’t Care
BL/2 = 8
Figure 42 - Consecutive Writes Operation: tCCD = Min + 1, 0.5nCK Postamble
Notes
1. BL = 16, Write Postamble = 0.5nCK
2. Din n/m = data-in from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T8
T9
T10
T11
T12
BL
BA0,
CA
CAm
CAm
T13
T14
T15
T16
T17
T23
T24
T25
T26
T32
T33
T34
T35
T36
T36
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
Write-1
CAS-2
tCCD = 9
WL = 12
WL = 12
tDQSS
tDQSS
tWPST
tWPRE
DQS_c
DQS_t
DQ
Don’t Care
Don’t Care
tDQS2DQ
tDQS2DQ
Din Din Din Din Din Din Dont’ Care Din Din Din Din Din Din
m0 m1 m2 m13 m14 m15
n0 n1 n2 n13 n14 n15
Don’t Care
BL/2 = 8
Don’t Care
BL/2 = 8
Figure 43 - Consecutive Writes Operation: tCCD = Min + 1, 1.5nCK Postamble
Notes
1. BL = 16, Write Postamble = 1.5nCK
2. Din n/m = data-in from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T9
T10
T11
T12
T13
BL
BA0,
CA
CAm
CAm
T14
T15
T16
T17
T23
T24
T25
T26
T27
T33
T34
T35
T36
T37
T38
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
Write-1
CAS-2
tCCD = 10
WL = 12
WL = 12
tDQSS
tDQSS
tWPRE
tWPST
tWPRE
DQS_c
DQS_t
Don’t Care
Don’t Care
tDQS2DQ
DQ
Din Din Din Din Din Din
n0 n1 n2 n13 n14 n15
Don’t Care
BL/2 = 8
Note
tWPST
Don’t Care
tDQS2DQ
Din Din Din Din Din Din
m0 m1 m2 m13 m14 m15
Don’t Care
BL/2 = 8
Figure 44 - Consecutive Writes Operation: tCCD = Min + 2, 0.5nCK Postamble
Notes
1. BL = 16, Write Postamble = 0.5nCK
2. Din n/m = data-in from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T9
T10
T11
T12
T13
BL
BA0,
CA
CAm
CAm
T14
T15
T16
T17
T23
T24
T25
T26
T27
T33
T34
T35
T36
T37
T38
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
Write-1
CAS-2
tCCD = 10
WL = 12
WL = 12
tDQSS
tDQSS
tWPRE
tWPST
tWPRE
DQS_c
DQS_t
Don’t Care
Don’t Care
tDQS2DQ
DQ
Din Din Din Din Din Din
n0 n1 n2 n13 n14 n15
Don’t Care
BL/2 = 8
Note
tWPST
tDQS2DQ
Don’t Care
Din Din Din Din Din Din
m0 m1 m2 m13 m14 m15
Don’t Care
BL/2 = 8
Figure 45 - Consecutive Writes Operation: tCCD = Min + 2, 1.5nCK Postamble
Notes
1. BL = 16, Write Postamble = 1.5nCK
2. Din n/m = data-in from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T9
T10
T11
T12
T13
T14
BL
BA0,
CA
CAm
CAm
T15
T16
T17
T23
T24
T25
T26
T27
T28
T34
T35
T36
T37
T38
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
DES
Write-1
CAS-2
tCCD = 11
WL = 12
WL = 12
tDQSS
tDQSS
tWPRE
tWPST
tWPRE
DQS_c
DQS_t
Don’t Care
tDQS2DQ
DQ
Don’t Care
Dont’ Care
Din Din Din Din Din Din
n0 n1 n2 n13 n14 n15
Don’t Care
tWPST
tDQS2DQ
Don’t Care
Din Din Din Din Din Din
m0 m1 m2 m13 m14 m15
BL/2 = 8
Note
Don’t Care
BL/2 = 8
Figure 46 - Consecutive Writes Operation: tCCD = Min + 3, 0.5nCK Postamble
Notes
1. BL = 16, Write Postamble = 1=0.5nCK
2. Din n/m = data-in from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T9
T10
T11
T12
T13
T14
BL
BA0,
CA
CAm
CAm
T15
T16
T17
T23
T24
T25
T26
T27
T28
T34
T35
T36
T37
T38
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
DES
Write-1
CAS-2
tCCD = 11
WL = 12
WL = 12
tDQSS
tDQSS
tWPRE
tWPST
tWPRE
DQS_c
DQS_t
Don’t Care
Don’t Care
tDQS2DQ
DQ
tWPST
Din Din Din Din Din Din
n0 n1 n2 n13 n14 n15
Don’t Care
tDQS2DQ
Don’t Care
Din Din Din Din Din Din
m0 m1 m2 m13 m14 m15
BL/2 = 8
N t
Don’t Care
BL/2 = 8
Figure 47 - Consecutive Writes Operation: tCCD = Min + 3, 1.5nCK Postamble
Notes
1. BL = 16, Write Postamble = 1.5nCK
2. Din n/m = data-in from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
T9
T10
T11
T12
T13
T14
BL
BA0,
CA
CAm
CAm
T15
T16
T17
T23
T24
T25
T26
T27
T28
T29
T35
T36
T37
T38
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
DES
Write-1
CAS-2
tCCD = 12
WL = 12
WL = 12
tDQSS
tDQSS
tWPRE
tWPST
tWPRE
DQS_c
DQS_t
Dont’ Care
Don’t Care
tDQS2DQ
DQ
tWPST
Din Din Din Din Din Din
n0 n1 n2 n13 n14 n15
Don’t Care
tDQS2DQ
Don’t Care
BL/2 = 8
N t
Don’t Care
Din Din Din Din Din Din
m0 m1 m2 m13 m14 m15
Don’t Care
BL/2 = 8
Figure 48 - Consecutive Writes Operation: tCCD = Min + 4, 1.5nCK Postamble
Notes
1. BL = 16, Write Postamble = 1.5nCK
2. Din n/m = data-in from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
2.11. Masked Write Operation
The LPDDR4-SDRAM requires that Write operations which include a byte mask anywhere in the burst sequence must use the Masked
Write command. This allows the DRAM to implement efficient data protection schemes based on larger data blocks. The Masked
Write-1 command is used to begin the operation, followed by a CAS-2 command. A Masked Write command to the same bank cannot
be issued until tCCDMW is met, to allow the LPDDR4-SDRAM to finish the internal Read-Modify-Write. One Data Mask-Invert (DMI)
pin is provided per byte lane, and the Data Mask-Invert timings match data bit (DQ) timing. See the section on Data Mask Invert for
more information on the use of the DMI signal.
CK_c
CK_t
CA
Bank 0
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Bank 0
Valid
Valid
Valid
tCCDMW
CMD
Masked Write
CAS-2
Valid
Valid
Valid
WL
tDQSS
Valid
Masked Write
CAS-2
DQS_c
DQS_t
tWPRE
tDQS2DQ
DQ[15:0]
DMI[1:0]
tWPST
Valid
Valid
Valid
Valid
Valid
Valid
Figure 49 - Masked Write Command - Same Bank (Shown with BL16, 2tCK Preamble)
Notes
1. Masked Write supports only BL16 operations. For BL32 configuration, the system needs to insert only 16 bit wide data for
masked write operation.
CK_c
CK_t
CA
Bank 0
tCCD
tCCD
Bank 1
Bank 2
tCCDMW
tCCD
tCCD
Bank 3
Bank 0
WL
CMD
Mask Write
CAS-2
Mask Write
CAS-2
Mask Write
CAS-2
Mask Write
CAS-2
Mask Write
CAS-2
tDQSS
tWPST
DQS_c
DQS_t
tWPRE
Q[15:0]
DM[1:0]
tDQS2DQ
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Figure 50 - Masked Write Command - Different Bank (shown with BL16, 2tCK Preamble)
Notes
1. Masked Write supports only BL16 operations. For BL32 configuration, the system needs to insert only 16 bit wide data for
masked write operation.
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2.11.1. Masked Write Timing constraints
Table 21 - Masked Write Timing constraints - Same bank : DQ ODT is Disabled
Next CMD
Current CMD
Activate
Read
(BL16 or 32)
Write
(BL16 or 32)
Masked Write
Precharge
Activate
Illegal
RU(tRCD/tCK)
RU(tRCD/tCK)
RU(tRCD/tCK)
RU(tRAS/tCK)
Read (BL16)
Illegal
81)
RL+
RL+
RU(tDQSCK(max)/tCK)+ RU(tDQSCK(max)/tCK)+
BL/2+
BL/2-WL+
BL/2-WL+
max{(8,RU(tRTP/tCK)}-8
tWPRE+RD(tRPST)
tWPRE+RD(tRPST)
RL+
RL+
RU(tDQSCK(max)/tCK)+ RU(tDQSCK(max)/tCK)+
BL/2+
BL/2-WL+
BL/2-WL+
max{(8,RU(tRTP/tCK)}-8
tWPRE+RD(tRPST)
tWPRE+RD(tRPST)
Read (BL32)
Illegal
162)
Write (BL16)
Illegal
WL+1+BL/2+
RU(tWTR/tCK)
81)
tCCDMW3)
WL+ 1 + BL/2+
RU(tWR/tCK)
Write (BL32)
Illegal
WL+1+BL/2+
RU(tWTR/tCK)
162)
tCCDMW + 84)
WL+ 1 + BL/2+
RU(tWR/tCK)
Masked Write
Illegal
WL+1+BL/2+
RU(tWTR/tCK)
tCCD
tCCDMW3)
WL+ 1 + BL/2+
RU(tWR/tCK)
Precharge
RU(tRP/tCK),
RU(tRPab/tCK)
Illegal
Illegal
Illegal
4
Notes
1. In the case of BL = 16, tCCD is 8*tCK.
2. In the case of BL = 32, tCCD is 16*tCK.
3. tCCDMW = 32*tCK (4*tCCD at BL=16)
4. Write with BL=32 operation has 8*tCK longer than BL =16.
5. tRPST values depend on MR1-OP[7] respectively.
Table 22 - Masked Write Timing constraints - Same bank : DQ ODT is Enabled
Next CMD
Activate
Current CMD
Read (BL16)
Read (BL32)
Illegal
Illegal
Read
(BL16 or 32)
Write
(BL16 or 32)
Masked Write
Precharge
81)
RL+
RL+
RU(tDQSCK(max)/tCK) + RU(tDQSCK(max)/tCK) +
BL/2+RD(tRPST)-ODTLon BL/2+RD(tRPST)-ODTLon
-RD(tODTon,min.tCK)
-RD(tODTon,min.tCK)
BL/2+
max{(8,RU(tRTP/tCK)}-8
162)
RL+
RL+
RU(tDQSCK(max)/tCK) + RU(tDQSCK(max)/tCK) +
BL/2+RD(tRPST)-ODTLon BL/2+RD(tRPST)-ODTLon
-RD(tODTon,min.tCK)
-RD(tODTon,min.tCK)
BL/2+
max{(8,RU(tRTP/tCK)}-8
Notes
1. In the case of BL = 16, tCCD is 8*tCK.
2. In the case of BL = 32, tCCD is 16*tCK.
3. The rest of the timing is same as DQ ODT is Disable case
4. tRPST values depend on MR1-OP[7] respectively.
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Table 23 - Masked Write Timing constraints - Different bank : DQ ODT is Disabled
Next CMD
Current
CMD
Activate
Read
(BL16 or 32)
Write
(BL16 or 32)
Masked Write
(BL16)
Precharge
Activate
RU(tRRD/tCK)
4
4
4
2
81)
RL+
RU(tDQSCK(max)/tCK)+
BL/2-WL+
tWPRE+RD(tRPST)
RL+
RU(tDQSCK(max)/tCK)+
BL/2-WL+
tWPRE+RD(tRPST)
2
RL+
RU(tDQSCK(max)/tCK)+
BL/2-WL+
tWPRE+RD(tRPST)
RL+
RU(tDQSCK(max)/tCK)+
BL/2-WL+
tWPRE+RD(tRPST)
2
Read (BL16)
4
2)
Read (BL32)
4
Write (BL16)
4
WL+1+BL/2+
RU(tWTR/tCK)
81)
81)
2
Write (BL32)
4
WL+1+BL/2+
RU(tWTR/tCK)
162)
162)
2
Masked Write
4
WL+1+BL/2+
RU(tWTR/tCK)
81)
81)
2
Precharge
4
4
4
4
4
16
Notes
1. In the case of BL = 16, tCCD is 8*tCK.
2. In the case of BL = 32, tCCD is 16*tCK.
3. tRPST values depend on MR1-OP[7] respectively
Table 24 - Masked Write Timing constraints - Different bank : DQ ODT is Enabled
Next CMD
Current
CMD
Read (BL16)
Read (BL32)
Activate
4
4
Read
(BL16 or 32)
Write
(BL16 or 32)
Masked Write
(BL16)
Precharge
81)
RL+
RU(tDQSCK(max)/tCK)+
BL/2+RD(tRPST)ODTLon-RD(tODTon,min/tCK)
RL+
RU(tDQSCK(max)/tCK)+
BL/2+RD(tRPST)ODTLon-RD(tODTon,min/tCK)
2
RL+
RU(tDQSCK(max)/tCK)+
BL/2+RD(tRPST) ODTLon-RD(tODTon,min/tCK)
RL+
RU(tDQSCK(max)/tCK)+
BL/2+RD(tRPST)ODTLon-RD(tODTon,min/tCK)
2
2)
16
Notes
1. In the case of BL = 16, tCCD is 8*tCK.
2. In the case of BL = 32, tCCD is 16*tCK.
3. The rest of the timing is same as DQ ODT is Disable case
4. tRPST values depend on MR1-OP[7] respectively.
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2.12. LPDDR4 Data Mask (DM) and Data Bus Inversion (DBIdc) Function
LPDDR4 SDRAM supports the function of Data Mask and Data Bus inversion. Its details are shown below.
• LPDDR4 device supports Data Mask (DM) function for Write operation.
• LPDDR4 device supports Data Bus Inversion (DBIdc) function for Write and Read operation.
• LPDDR4 supports DM and DBIdc function with a byte granularity.
• DBIdc function during Write or Masked Write can be enabled or disabled through MR3 OP[7].
• DBIdc function during Read can be enabled or disabled through MR3 OP[6].
• DM function during Masked Write can be enabled or disabled through MR13 OP[5].
• LPDDR4 device has one Data Mask Inversion (DMI) signal pin per byte; total of 2 DMI signals per channel.
• DMI signal is a bi-directional DDR signal and is sampled along with the DQ signals for Read and Write or Masked Write
operation.
There are eight possible combinations for LPDDR4 device with DM and DBIdc function. Table below describes the functional behavior
for all combinations.
Table 25 - Function Behavior of DMI Signal During Write, Masked Write and Read Operation
DMI Signal
DMI Signal DMI Signal
during
DMI Signal DMI Signal DMI Signal
during MPC
during
Masked
during
during MPC during MPC
[DQ Read
MRR
Write
Read
[WR FIFO] [RD FIFO]
calibration] Command
Command
DM
Fuction
Write
DBIdc
Fuction
Read
DBIdc
Fuction
DMI Signal
during
Write
Command
Disable
Disable
Disable
Note: 1
Note: 1, 3
Note: 2
Note: 1
Note: 2
Note: 2
Disable
Enable
Disable
Note: 4
Note: 3
Note: 2
Note: 9
Note: 10
Note: 11
Note: 2
Disable
Disable
Enable
Note: 1
Note: 3
Note: 5
Note: 9
Note: 10
Note: 11
Note: 12
Disable
Enable
Enable
Note: 4
Note: 3
Note: 5
Note: 9
Note: 10
Note: 11
Note: 12
Enable
Disable
Disable
Note: 6
Note: 7
Note: 2
Note: 9
Note: 10
Note: 11
Note: 2
Enable
Enable
Disable
Note: 4
Note: 8
Note: 2
Note: 9
Note: 10
Note: 11
Note: 2
Enable
Disable
Enable
Note: 6
Note: 7
Note: 5
Note: 9
Note: 10
Note: 11
Note: 12
Enable
Enable
Enable
Note: 4
Note: 8
Note: 5
Note: 9
Note: 10
Note: 11
Note: 12
Note: 2
Notes
1.DMI input signal is a don’t care. DMI input receivers are turned OFF.
2.DMI output drivers are turned OFF.
3.Masked Write Command is not allowed and is considered an illegal command as DM function is disabled.
4.DMI signal is treated as DBI signal and it indicates whether DRAM needs to invert the Write data received on DQs within a byte.
The LPDDR4 device inverts Write data received on the DQ inputs in case DMI was sampled HIGH, or leaves the Write data non-inverted in case
DMI was sampled LOW. The total count of ‘1’ data bits on DQ[2:7] or DQ[10:15] (for Lower Byte or Upper Byte respectively) should be less than
or equal to four during Write DBI is enabled.
5.The LPDDR4 DRAM inverts Read data on its DQ outputs associated within a byte and drives DMI signal HIGH when the number of ‘1’ data bits
within a given byte lane is greater than four; otherwise the DRAM does not invert the read data and drives DMI signal LOW.
6.The LPDDR4 DRAM does not perform any mask operation when it receives Write command. During the Write burst associated with Write
command, DMI signal must be driven LOW.
7.The LPDDR4 DRAM requires an explicit Masked Write command for all masked write operations. DMI signal is treated as DM signal and it indicates
\ which bit time within the burst is to be masked. When DMI signal is HIGH, DRAM masks that bit time across all DQs associated within a byte.
All DQ input signals within a byte are don’t care (either HIGH or LOW) when DMI signal is HIGH. When DMI signal is LOW, the LPDDR4 DRAM
does not perform mask operation and data received on DQ input is written to the array.
8.The LPDDR4 DRAM requires an explicit Masked Write command for all masked write operations. The LPDDR4 device masks the Write data
received on the DQ inputs if the total count of ‘1’ data bits on DQ[2:7] or DQ[10:15] (for Lower Byte or Upper Byte respectively) is equal to or
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LPDDR4X 64Gb (x8, 2Channel, 2CS)
greater than five and DMI signal is LOW. Otherwise the LPDDR4 DRAM does not perform mask operation and treats it as a legal DBI pattern; DMI
signal is treated as DBI signal and data received on DQ input is written to the array.
9. DMI signal is treated as a training pattern. The LPDDR4 SDRAM does not perform any mask operation and does not invert Write data received
on the DQ inputs.
10. DMI signal is treated as a training pattern. The LPDDR4 SDRAM returns DMI pattern written in WR-FIFO.
11. DMI signal is treated as a training pattern. For more details, see MPC RD DQ Calibration session.
12. DBI may apply or may not apply during normal MRR. It's vendor specific. If read DBI is enable with MRS and vendor cannot support the DBI
during MRR, DBI pin status should be low. If read DBI is enable with MRS and vendor can support the DBI during MRR, the LPDDR4 DRAM inverts
Mode Register Read data on its DQ outputs associated within a byte and drives DMI signal HIGH when the number of ‘1’ data bits within a given
byte lane is greater than four; otherwise the DRAM does not invert the read data and drives DMI signal LOW.
CK_c
CK_t
CKE
CS
CA
Bank 0
CMD
Valid
Masked Write
Valid
Valid
CAS-2
Valid
Valid
Valid
WL
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
tDQSS
DQS_c
DQS_t
tWPRE
DQ[7:0]
tDQS2DQ
tWPST
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
N
N
I
I
M
N
I
N
N
M
N
N
DMI[0]
Valid
Input data is written to DRAM cell.
Valid
Input data is inverted, then written to DRAM cell.
Valid
Input data is masked. The total count on DQ[7:2] is equal or greater than five.
Figure 51 - Masked Write Operation w/ Write DBI Enabled; DM Enabled
Notes
1. Data Mask (DM) is Enabled; MR13 OP[5] = 1, Data Bus Inversion (DBI) Write is Enabled; MR3 OP[7] = 1.
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CK_c
CK_t
CKE
CS
CA
CMD
Bank 0
Valid
Masked Write
Valid
Valid
CAS-2
Valid
Valid
Valid
WL
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
tDQSS
DQS_c
DQS_t
tWPRE
DQ[7:0]
tDQS2DQ
tWPST
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
N
N
I
I
N
N
I
N
Valid
Valid
N N
Valid
Valid
N N
DMI[0]
Valid
Input data is written to DRAM cell.
Valid
Input data is inverted, then written to DRAM cell.
Figure 52 - Write Command w/ Write DBI Enabled; DM Disabled
Notes
1. Data Mask (DM) is Disabled; MR13 OP[5] = 0, Data Bus Inversion (DBI) Write is Enabled; MR3 OP[7] = 1.
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2.13. Precharge Operation
The PRECHARGE command is used to precharge or close a bank that has been activated. The PRECHARGE command is initiated with
CS, and CA[5:0] in the proper state as defined by the Command Truth Table. The PRECHARGE command can be used to precharge
each bank independently or all banks simultaneously. The AB flag and the bank address bit are used to determine which bank(s) to
precharge. The precharged bank(s) will be available for subsequent row access tRPab after an all-bank PRECHARGE command is
issued, or tRPpb after a single-bank PRECHARGE command is issued.
To ensure that LPDDR4 devices can meet the instantaneous current demands, the row-precharge time for an all-bank PRECHARGE
(tRPab) is longer than the perbank precharge time (tRPpb).
Table 26 - Precharge Bank Selection
AB
(CA[5], R1)
BA2
(CA[2], R2)
BA1
(CA[1], R2)
BA0
(CA[0], R2)
Precharged
Bank(s)
0
0
0
0
Bank 0 Only
0
0
0
1
Bank 1 Only
0
0
1
0
Bank 2 Only
0
0
1
1
Bank 3 Only
0
1
0
0
Bank 4 Only
0
1
0
1
Bank 5 Only
0
1
1
0
Bank 6 Only
0
1
1
1
Bank 7 Only
1
Valid
Valid
Valid
All banks
Rev 1.2 / Mar. 2020 / SK hynix Confidential
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2.13.1. Burst Read Operation followed by Precharge
The PRECHARGE command can be issued as early as BL/2 clock cycles after a READ command, but PRECHARGE cannot be issued
until after tRAS is satisfied. A new bank ACTIVATE command can be issued to the same bank after the row PRECHARGE time (tRP)
has elapsed. The minimum READ-to-PRECHARGE time must also satisfy a minimum analog time from the 2nd rising clock edge of the
CAS-2 command. tRTP begins BL/2 . 8 clock cycles after the READ command. For LPDDR4 READ-to-PRECHARGE timings see Table
Timing Between Commands (Precharge and Auto-Precharge) - DQ ODT is Disabled, Timing Between Commands (Precharge and
Auto-Precharge) - DQ ODT is Enabled
CK_t
CK_c
CA[5:0]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CAS-2
Read - 1
Valid
Valid
Valid
Valid
tRP
tRTP
CMD
Valid
Valid
Valid
Precharge
Valid
Valid
ACT1
Valid
ACT2
DQS_t
DQS_c
DQ[15:0]
DMI[1:0]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Figure 53 - Burst Read followed by Precharge (BL16, Toggling Preamble)
CK_t
CK_c
CA[5:0]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Read - 1
CAS-2
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
tRP
tRTP
8 Clocks
CMD
Valid
Valid
Precharge
Valid
Valid
Valid
ACT1
ACT2
DQS_t
DQS_c
DQ[15:0]
DMI[1:0]
Valid Valid Valid
Valid
Valid
Valid
Valid Valid
Valid Valid Valid
Valid
Valid
Valid
Valid Valid
Figure 54 - Burst Read followed by Precharge (BL32, Toggling Preamble)
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2.13.2. Burst Write followed by Precharge
A Write Recovery time (tWR) must be provided before a PRECHARGE command may be issued. This delay is referenced from the
next rising edge of CK_t after the last latching DQS clock of the burst.
LPDDR4-SDRAM devices write data to the memory array in prefetch multiples (prefetch=16). An internal WRITE operation can only
begin after a prefetch group has been clocked, so tWR starts at the prefetch boundaries. The minimum WRITE-to-PRECHARGE time
for commands to the same bank is WL + BL/2 + 1 + RU(tWR/tCK) clock cycles.
CK_t
CK_c
CA0-5
WR
WR
CAS
CAS
Valid
Valid
Valid
Valid
Valid
CMD
Write
CAS-2
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
BL/2 + 1 Clock
WL
Valid
Valid
Valid
Valid
Valid
tDQSS(max)
tWR
PRECHARGE
ACT-1
Valid
ACT-2
tRP
DQS_t
DQS_c
tDQS2DQ
DQ[15:0]
/DMI[1:0]
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
Figure 55 - Burst Write followed by Precharge (BL16, 2tCK Preamble)
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2.13.3. Auto-Precharge operation
Before a new row can be opened in an active bank, the active bank must be precharged using either the PRECHARGE command or
the Auto-PRECHARGE function. When a READ, WRITE or Masked Write command is issued to the device, the AP bit (CA5) can be set
to enable the active bank to automatically begin precharge at the earliest possible moment during the burst READ, WRITE or Masked
Write cycle.
If AP is LOW when the READ, WRITE or Masked Write command is issued, then the normal READ, WRITE or Masked Write burst
operation is executed and the bank remains active at the completion of the burst.
If AP is HIGH when the READ, WRITE or Masked Write command is issued, the Auto-PRECHARGE function is engaged. This feature
enables the PRECHARGE operation to be partially or completely hidden during burst READ cycles (dependent upon READ or WRITE
latency), thus improving system performance for random data access.
Read with Auto Precharge or Write/Mask Write with Auto Precharge commands may be issued after tRCD has been satisfied. The
LPDDR4 SDRAM RAS Lockout feature will schedule the internal precharge to assure that tRAS is satisfied.
tRC needs to be satisfied prior to issuing subsequent Activate commands to the same bank.
The figure below shows example of RAS lock function.
Figure 56 - Command Input Timing with RAS lock
Note
1. tCK(AVG) = 0.938ns, Data Rate = 2133Mbps, tRCD(Min) = Max(18ns, 4nCK), tRAS(Min) = Max(42ns, 3nCK), nRTP = 8nCK,
BL = 32
2. tRCD = 20nCK comes from Roundup(18ns/0.938ns)
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
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2.13.3.1. Burst Read with Auto-Precharge
If AP is HIGH when a READ command is issued, the READ with Auto-PRECHARGE function is engaged. An internal precharge procedure starts a following delay time after the READ command. And this delay time depends on BL setting.
BL = 16: tRTP
BL = 32: 8tCK + tRTP
For LPDDR4 Auto-PRECHARGE calculations, see table Timing Between Commands (Precharge and Auto-Precharge) - DQ ODT is Disabled, Timing Between Commands (Precharge and Auto-Precharge) - DQ ODT is Enabled. Following an Auto-PRECHARGE operation,
an ACTIVATE command can be issued to the same bank if the following two conditions are both satisfied:
a. The RAS precharge time (tRP) has been satisfied from the clock at which the Auto-PRECHARGE began, or
b. The RAS cycle time (tRC) from the previous bank activation has been satisfied.
CK_t
CK_c
CA[5:0]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
READ-1
w/ AP
CAS-2
Valid
Valid
Valid
Valid
Valid
tRPpb
nRTP
CMD
Valid
Valid
Valid
Valid
Valid
ACT1
Valid
ACT2
DQS_t
DQS_c
DQ[15:0]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Figure 57 - Burst Read with Auto-Precharge (BL16, Toggling preamble)
CK_t
CK_c
CA[5:0]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CMD
CAS-2
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
tRPpb
nRTP
8 Clocks
Read - 1
w/ AP
Valid
Precharge
Valid
Valid
Valid
ACT1
ACT2
DQS_t
DQS_c
DQ[15:0]
Valid Valid Valid
Valid
Valid
Valid
Valid Valid
Valid Valid Valid
Valid
Valid
Valid
Valid Valid
Figure 58 - Burst Read with Auto-Precharge (BL32, Toggling preamble)
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2.13.3.2. Burst Write with Auto-Precharge
If AP is HIGH when a WRITE command is issued, the WRITE with Auto-PRECHARGE function is engaged. The device starts an AutoPRECHARGE on the rising edge tWR cycles after the completion of the Burst WRITE.
Following a WRITE with Auto-PRECHARGE, an ACTIVATE command can be issued to the same bank if the following conditions are
met:
a. The RAS precharge time (tRP) has been satisfied from the clock at which the Auto-PRECHARGE began, and
b. The RAS cycle time (tRC) from the previous bank activation has been satisfied.
CK_t
CK_c
CA0-5
WR
WR
CAS
CAS
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
WL
CMD
Write
CAS-2
Valid
Valid
Valid
Valid
Valid
Valid
tDQSS(max)
Valid
ACT-1
Valid
tWR
ACT-2
tRP
DQS_t
DQS_c
tDQS2DQ
DQ[15:0]
/DMI[1:0]
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
Figure 59 - Burst Write with Auto-Precharge (BL16, 2tCK preamble)
Table 27 - Timing Between Commands (Precharge and Auto-Precharge) - DQ ODT is Disabled
From
Command
Read
(BL16)
Read
(BL32)
Read
w/AP
(BL16)
To Command
Minimum Delay between
“From Command” and “To Command”
Unit
Notes
Precharge
(to same bank as Read)
tRTP
tCK
1,6
Precharge All
tRTP
tCK
1,6
Precharge
(to same bank as Read)
8*tCK + tRTP
tCK
1,6
Precharge All
8*tCK + tRTP
tCK
1,6
Precharge
(to same bank as Read w/AP)
nRTP
tCK
1,10
Precharge All
nRTP
tCK
1,10
Activate
(to same bank as Read w/AP)
nRTP + tRPpb
tCK
1,8,10
Write or Write w/ AP
(same bank)
Illegal
-
3
Masked Write or Masked Write w/AP
(same bank)
Illegal
-
Write or Write w/AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+
BL/2+RD(tRPST)-WL+tWPRE
tCK
3,4,5
Masked Write or Masked Write w/AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+
BL/2+RD(tRPST)-WL+tWPRE
tCK
3,4,5
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From
Command
Read
w/AP
(BL16)
Read
w/AP
(BL32)
Write
(BL16 &
BL32)
Masked Write
Write
w/AP
To Command
Minimum Delay between
“From Command” and “To Command”
Unit
Read or Read w/AP
(same bank)
Illegal
-
Read or Read w/AP
(different bank)
BL/2
tCK
3
Precharge
(to same bank as Read w/AP)
8*tCK + nRTP
tCK
1,10
Precharge All
8*tCK + nRTP
tCK
1,10
Activate
(to same bank as Read w/AP)
8*tCK + nRTP + tRPpb
tCK
1,8,10
Write or Write w/AP
(same bank)
Illegal
-
Masked Write or Masked Write w/AP
(same bank)
Illegal
-
Write or Write w/ AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+
BL/2+RD(tRPST)-WL+tWPRE
tCK
3,4,5
Masked Write or Masked Write w/AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+
BL/2+RD(tRPST)-WL+tWPRE
tCK
3,4,5
Read or Read w/AP
(same bank)
Illegal
-
Read or Read w/AP
(different bank)
BL/2
tCK
3
Precharge
(to same bank as Masked Write)
WL + BL/2 + tWR + 1
tCK
1,7
Precharge All
WL + BL/2 + tWR + 1
tCK
1,7
Precharge
(to same bank as Masked Write)
WL + BL/2 + tWR + 1
tCK
1,7
Precharge All
WL + BL/2 + tWR + 1
tCK
1,7
Precharge
(to same bank as Write w/AP)
WL + BL/2 + nWR + 1
tCK
1,11
Precharge All
WL + BL/2 + nWR + 1
tCK
1,11
Activate
(to same bank as Write w/AP)
WL + BL/2 + nWR + 1 + tRPpb
tCK
1,8,11
Write or Write w/AP
(same bank)
Illegal
-
Write or Write w/AP
(different bank)
BL/2
tCK
3
Masked-Write or Masked-Write w/AP
(different bank)
BL/2
tCK
3
Read or Read w/AP (same bank)
Illegal
-
Read or Read w/AP (different bank)
WL + BL/2 + tWTR + 1
tCK
Rev 1.2 / Mar. 2020 / SK hynix Confidential
Notes
3,9
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From
Command
Masked Write
w/AP
Precharge
Precharge All
To Command
Minimum Delay between
“From Command” and “To Command”
Unit
Notes
Precharge
(to same bank as Masked Write w/AP)
WL + BL/2 + nWR + 1
tCK
1,11
Precharge all
WL + BL/2 + nWR + 1
tCK
1,11
Activate
(to same bank as Masked Write w/AP)
WL + BL/2 + nWR + 1 + tRPpb
tCK
1,8,11
Write or Write w/ AP
(same bank)
Illegal
-
Masked Write or Masked Write w/AP
(same bank)
Illegal
-
Write or Write w/AP
(different bank)
BL/2
tCK
3
Masked Write or Masked Write w/AP
(differenet bank)
BL/2
tCK
3
Read or Read w/AP (same bank)
Illegal
-
Read or Read w/AP (different bank)
WL + BL/2 + tWTR + 1
tCK
3,9
Precharge
(to same bank as Precharge)
4
tCK
1
Precharge All
4
tCK
1
Precharge
4
tCK
1
Precharge All
4
tCK
1
Notes
1. For a given bank, the precharge period should be counted from the latest precharge command, whether per-bank or all-bank,= issued to that
bank. The precharge period is satisfied tRP after that latest precharge command.
2. Any command issued during the minimum delay time as specified in above the table is illegal.
3. After READ w/AP, seamless read operations to different banks are supported. After WRITE w/AP or Masked Write w/AP, seamless write
operations to different banks are supported. READ, WRITE, and Masked Write operations may not be truncated or interrupted.
4. tRPST values depend on MR1 OP[7] repectively
5. tWPRE values depend on MR1 OP[2] respectively
6. Minimum Delay between "From Command" and "To Command" in clock cycle is calculated by dividing tRTP(in ns) by tCK(in ns) and rounding
up to the next integer: Minimum Delay[cycles] = Roundup(tRTP[ns] / tCK[ns])
7. Minimum Delay between "From Command" and "To Command" in clock cycle is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up
to the next integer: Minimum Delay[cycles] = Roundup(tWR[ns] / tCK[ns])
8. Minimum Delay between "From Command" and "To Command" in clock cycle is calculated by dividing tRPpb(in ns) by tCK(in ns) and rounding
up to the next integer: Minimum Delay[cycles] = Roundup(tRPpb[ns] / tCK[ns])
9. Minimum Delay between "From Command" and "To Command" in clock cycle is calculated by dividing tWTR(in ns) by tCK(in ns) and rounding
up to the next integer: Minimum Delay[cycles] = Roundup(tWTR[ns] / tCK[ns])
10. For Read w/AP the value is nRTP which is defined in Mode Register 2.
11. For Write w/AP the value is nWR which is defined in Mode Register 1.
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Table 28 - Timing Between Commands (Precharge and Auto-Precharge) - DQ ODT is Enabled
From
Command
Read w/AP
(BL16)
Read w/AP
(BL32)
To Command
Minimum Delay between
“From Command” and “To Command”
Unit
Notes
Write or Write w/AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+BL/2+RD(tRPST)ODTLon-RD(tODTon,min/tCK)+1
tCK
2,3
Masked Write or Masked Write w/AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+BL/2+RD(tRPST)ODTLon-RD(tODTon,min/tCK)+1
tCK
2,3
Write or Write w/AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+BL/2+RD(tRPST)ODTLon-RD(tODTon,min/tCK)+1
tCK
2,3
Masked Write or Masked Write w/AP
(different bank)
RL+RU(tDQSCK(max)/tCK)+BL/2+RD(tRPST)ODTLon-RD(tODTon,min/tCK)+1
tCK
2,3
Notes
1. The rest of Precharge and Auto-Precharge timings are as same as DQ ODT disabled case.
2. After READ w/AP, seamless read operations to different banks are supported. READ, WRITE, and Masked Write operations may
not be truncated or interrupted.
3. tRPST values depend on MR1 OP[7] respectively.
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2.14. Auto-Precharge operation
Before a new row can be opened in an active bank, the active bank must be precharged using either the PRECHARGE command or
the Auto-PRECHARGE function. When a READ, WRITE or Masked Write command is issued to the device, the AP bit (CA5) can be set
to enable the active bank to automatically begin precharge at the earliest possible moment during the burst READ, WRITE or Masked
Write cycle.
If AP is LOW when the READ, WRITE or Masked Write command is issued, then the normal READ, WRITE or Masked Write burst
operation is executed and the bank remains active at the completion of the burst.
If AP is HIGH when the READ, WRITE or Masked Write command is issued, the Auto-PRECHARGE function is engaged. This feature
enables the PRECHARGE operation to be partially or completely hidden during burst READ cycles (dependent upon READ or WRITE
latency), thus improving system performance for random data access.
2.14.1. Delay Time from Write to Read with Auto-Precharge
In the case of write command followed by read with auto-precharge, controller must satisfy tWR for the write command before initiating the DRAM internal auto-precharge. It means that (tWTR + nRTP) should be equal or longer than (tWR) when BL setting is 16,
as well as (tWTR + nRTP +8nCK) should be equal or longer than (tWR) when BL setting is 32. Refer to the following figure for
details.
Figure 60 - Delay time from write to Read with Auto-Precharge
Notes
1. Burst Length at Read = 16
2. DES commands are shown for ease of illustration; other commands may be valid at these times.
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2.15. Write and Masked Write operation DQS controls (WDQS Control)
LPDDR4-SDRAMs support write and masked write operations with the following DQS controls. Before and after Write and Masked
Write operations are issued, DQS_t/DQS_c is required to have a sufficient voltage gap to make sure the write buffers operating normally without any risk of metastability.
The LPDDDR4-SDRAM is supported by either of two WDQS control modes below.
Mode 1 : Read Based Control
Mode 2 : WDQS_on / WDQS_off definition based control
Regardless of ODT enable / disable, WDQS related timing described here does not allow any change of existing command timing
constraints for all read / write operation. In case of any conflict or ambiguity on the command timing constraints caused by the spec
here, the spec defined in section Multi-Purpose Command (MPC), in Table below (or WDQS Control Mode 1 - Read Based Control and
WDQS Control Mode 2 - WDQS_on/off) should have higher priority than WDQS control requirements.
Some legacy products may not provide WDQS control described below. However, in order to prevent the write preamble related failure, it is strongly recommended to support either of two WDQS controls to LPDDR4-SDRAMs. In the case of legacy SoC which may
not provide WDQS control modes, it is required to consult DRAM vendors to guarantee the write / masked write operation appropriately.
Table 29 - Timing Constraints for Training Commands
Previous Command
WR/MWR
RD/MRR
MPC
[WR FIFO]
MPC
[RD FIFO]
Next Command
Minimum Delay
Unit
Notes
MPC [WR FIFO]
tWRWTR
nCK
1
MPC [RD FIFO]
Not Allowed
-
2
MPC [RD DQ Calibration]
WL+RU(tDQSS(max)/tCK)+BL/2+RU(tWTR/tCK)
nCK
MPC [WR FIFO]
tRTRRD
nCK
MPC [RD FIFO]
Not Allowed
MPC[RD DQ Calibration]
tRTRRD
WR/MWR
Not Allowed
MPC [WR FIFO]
tCCD
RD/MRR
Not Allowed
MPC [RD FIFO]
WL+RU(tDQSS(max)/tCK)+BL/2+RU(tWTR/tCK)
MPC [RD DQ Calibration]
Not Allowed
WR/MWR
tRTRRD
nCK
3
MPC [WR FIFO]
tRTW
nCK
4
RD/MRR
tRTRRD
nCK
3
MPC [RD FIFO]
tCCD
nCK
MPC [RD DQ Calibration]
tRTRRD
nCK
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2
nCK
3
2
nCK
2
nCK
2
3
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Previous Command
MPC
[RD DQ Calibration]
Next Command
Minimum Delay
Unit
Notes
WR/MWR
tRTRRD
nCK
3
MPC [WR FIFO]
tRTRRD
nCK
3
RD/MRR
tRTRRD
nCK
3
MPC [RD FIFO]
Not Allowed
MPC [RD DQ Calibration]
tCCD
2
nCK
Notes
1. tWRWTR = WL + BL/2 + RU(tDQSS(max)/tCK) + max(RU(7.5ns/tCK), 8nCK)
2. No commands are allowed between MPC [WR FIFO] and MPC [RD FIFO] except MRW commands related to training parameters.
3. tRTRRD = RL + RU(tDQSCK(max)/tCK) + BL/2 + RD(tRPST) + max(RU(7.5ns/tCK),8nCK)
4. tRTW(DQ ODT Disabled case; MR11 OP[2:0]=000b) = RL + RU(tDQSCK(max)/tCK) + BL/2 - WL + tWPRE + RD(tRPST)
tRTW(DQ ODT Enabled case; MR11 OP[2:0]≠000b)=RL + RU(tDQSCK(max)/tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon,min/tCK) + 1
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2.15.1. WDQS Control Mode 1 - Read Based Control
The LPDDR4-SDRAM needs to be guaranteed the differential WDQS, but the differential WDQS can be controlled as described below.
WDQS control requirements here can be ignored while differential read DQS is operated or while DQS hands over from Read to Write
and vice versa.
1. At the time a write / masked write command is issued, SoC makes the transition from driving DQS_c high to
driving differential DQS_t/DQS_c, followed by normal differential burst on DQS pins.
2. At the end of post amble of write /masked write burst, SoC resumes driving DQS_c high through the subsequent
states except for DQS toggling and DQS turn around time of WT-RD and RD-WT as long as CKE is high.
3. When CKE is low, the state of DQS_t and DQS_c is allowed to be “Don’t Care”.
WT
CMD
WT BURST
Following states from WT BURST
CKE
DQS_c
Don't Care
Don't Care
DQS_t
2.15.2. WDQS Control Mode 2 - WDQS_on/off
After write / masked write command is issued, DQS_t and DQS_c required to be differential from WDQS_on, and DQS_t and DQS_c
can be “Don’t Care” status from WDQS_off of write / masked write command. When ODT is enabled, WDQS_on and WDQS_off timing is located in the middle of the operations. When host disables ODT, WDQS_on and WDQS_off constraints conflict with tRTW. The
timing does not conflict when ODT is enabled because WDQS_on and WDQS_off timing is covered in ODTLon and ODTLoff. However,
regardless of ODT on/off, WDQS_on/off timing below does not change any command timing constraints for all read and write operations. In order to prevent the conflict, WDQS_on/off requirement can be ignored where WDQS_on/off timing is overlapped with read
operation period including Read burst period and tRPST or overlapped with turn-around time (RD-WT or WT-RD). In addition, the
period during DQS toggling caused by Read and Write can be counted as WDQS_on/off.
Parameters
• WDQS_on : the max delay from write / masked write command to differential DQS_t and DQS_c
• WDQS_off : the min delay for DQS_t and DQS_c differential input after the last write / masked write command.
• WDQS_Exception : the period where WDQS_on and WDQS_off timing is overlapped with read operation or with
DQS trun-around (RD-WT, WT-RD)
- WDQS_Exception @ ODT disable = max (WL-WDQS_on+tDQSTA- tWPRE - n*tCK, 0 tCK) where RD to WT
comand gap = tRTW(min)@ODT disable + n*tCK
- WDQS_Exception @ ODT enable = tDQSTA
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Table 30 - WDQS_on / WDQS_off Definition
RL
WL
nWR
nRTP
Set A Set B Set A Set B
WDQS_on
(max)
WDQS_off
(min)
Set A
Set B
Set A
Set B
Lower Clock Freq Upper Clock Freq
limit (>)
limit ( Low
CKE Low -> High
Exit CA Bus
Training
Switch to High
Speed Mode
FSP-OP=0
FSP-WR=1
Freq = Boot
FSP-OP=1
FSP-WR=1
Freq = High
Prepare for CBT
of FSP[0] for
Med. Frequency
FSP-WR=0
Freq = High
CKE High -> Low
CA Bus Training
FSP-OP[0]
FSP-WR=0
Freq = Med
Exit CBT
CKE Low -> High
FSP-OP=1
FSP-WR=0
Freq = High
Operate at
High Speed
Figure 112 - Training Two Frequency Set Points
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Once both Frequency Set Points have been trained, switching between points can be performed by a single MRW followed by waiting
for tFC (Figure below).
State n-1: FSP-OP=1
MRW Command
State n: FSP-OP=0
Operate at
High Speed
State n-1: FSP-OP=0
MRW Command
State n: FSP-OP=1
tFC
Operate at
Middle Speed
tFC
Operate at
High Speed
Figure 113 - Switching between two trained Frequency Set Points
Switching to a third (or more) Set-Point can be accomplished if the memory controller has stored the previously-trained values (in
particular the Vref-CA calibration value) and re-writes these to the alternate Set-Point before switching FSP-OP (Figure below).
Operate at
High Speed
State n-1: FSP-OP=1
State n: FSP-OP=0
State n-1: FSP-WR=1
State n: FSP-WR=0
tFC
tFC
MRW Vref(ca)
CA-ODT, DQ-ODT,
RL, WL, Vref(dq), etc
Operate at
Third Speed
Figure 114 - Switching to a third trained Frequency Set Point
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2.27. Mode Register Write-WR Leveling Mode
To improve signal-integrity performance, the LPDDR4 SDRAM provides a write-leveling feature to compensate CK-to-DQS timing
skew affecting timing parameters such as tDQSS, tDSS, and tDSH. The DRAM samples the clock state with the rising edge of DQS
signals, and asynchronously feeds back to the memory controller. The memory controller references this feedback to adjust the
clock-to-data strobe signal relationship for each DQS_t/DQS_c signal pair.
All data bits (DQ[7:0] for DQS_t/DQS_c[0], and DQ[15:8] for DQS_t/DQS_c[1]) carry the training feedback to the controller. Both
DQS signals in each channel must be leveled independently. Write-leveling entry/exit is independent between channels.
The LPDDR4 SDRAM enters into write-leveling mode when mode register MR2-OP[7] is set HIGH. When entering write-leveling
mode, the state of the DQ pins is undefined. During write-leveling mode, only DESELECT commands are allowed, or a MRW command to exit the write-leveling operation. Depending on the absolute values of tQSL and tQSH in the application, the value of tDQSS
may have to be better than the limits provided in the chapter “AC Timing Parameters” in order to satisfy the tDSS and tDSH specification. Upon completion of the write-leveling operation, the DRAM exits from write-leveling mode when MR2-OP[7] is reset LOW.
Write Leveling should be performed before Write Training (DQS2DQ Training).
2.27.1. Write Leveling Procedure:
1. Enter into Write-leveling mode by setting MR2-OP[7]=1,
2. Once entered into Write-leveling mode, DQS_t must be driven LOW and DQS_c HIGH after a delay of tWLDQSEN.
3. Wait for a time tWLMRD before providing the first DQS signal input. The delay time tWLMRD(MAX) is controller-dependent.
4. DRAM may or may not capture first rising edge of DQS_t due to an unstable first risign edge. Hence provide at least
consecutive 2 pulses of DQS signal input is required in every DQS input signal during Write Training Mode. The captured clock
level by each DQS edges are overwritten at any time and the DRAM provides asynchronous feedback on all the DQ bits after time
tWLO.
5. The feedback provided by the DRAM is referenced by the controller to increment or decrement the DQS_t and or DQS_c delay
settings.
6. Repeat step 4 through step 5 until the proper DQS_t/DQS_c delay is established.
7. Exit from Write-leveling mode by setting MR2-OP[7]=0.
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A Write Leveling timing example is shown in Figure below.
T0
T1
T2
T3
T4
MRW
MA
MRW
MA
MRW
OP
MRW
OP
DES
Ta0 Ta1 Tb0 Tb1 Tc0 Tc1
Td0 Td1 Td2 Td3 Te0 Te1 Tf0
Tf1 Tf2 Tf3 Tf4
Tg0 Tg1 Tg2 Tg3 Tg4
CK_t
CK_c
CS
CKE
CA
CMD
MRW-1
WR Leveling
MRW-2
WR Leveling
DES
Deselect
DES
DES
Deselect
DES
DES
Deselect
DES
DES
Deselect
DES
DES
Deselect
DES
DES
DES
Deselect
DES
Deselect
MRW
MA
MRW
MA
MRW
OP
MRW-1
WR Lev Exit
MRW
OP
MRW-2
WR Lev Exit
DES
DES
Valid
Deselect
Valid
Valid
Valid
Valid
Valid
tDQSH
tWLDQSEN
tDQSL
tWLWPRE
DQS_c
DQS_t
tWLMRD
tWLO
tWLO
tMRD
tWLO
DQ
Figure 115 - Write Leveling Timing, tDQSL (max)
T0
T1
T2
T3
T4
MRW
MA
MRW
MA
MRW
OP
MRW
OP
DES
Ta0 Ta1 Tb0 Tb1 Tc0 Tc1
Td0 Td1 Td2 Td3 Te0 Te1 Tf0
Tf1 Tf2 Tf3 Tf4
Tg0 Tg1 Tg2 Tg3
CK_t
CK_c
CS
CKE
CA
CMD
MRW-1
WR Leveling
MRW-2
WR Leveling
DES
Deselect
DES
DES
Deselect
DES
DES
Deselect
tDQSH
tWLDQSEN
DES
DES
Deselect
DES
DES
Deselect
DES
DES
DES
Deselect
DES
Deselect
MRW
MA
MRW
MA
MRW-1
WR Lev Exit
MRW
OP
MRW
OP
MRW-2
WR Lev Exit
DES
DES
Valid
Valid
Deselect
Valid
Valid
Valid
Valid
tDQSL
tWLWPRE
DQS_c
DQS_t
tWLMRD
tWLO
tWLO
tMRD
DQ
Figure 116 - Write Leveling Timing, tDQSL (min)
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2.27.2. Input Clock Frequency Stop and Change
The input clock frequency can be stopped or changed from one stable clock rate to another stable clock rate during Write Leveling
mode.
The Frequency stop or change timing is shown in Figure below
T0
T1
T2
T3
T4
Ta0
Ta1
Tb0 Tb1
Tb2
Tc0
Td0
Te0
Te1 Te2
Te3
Te4
Tf0
DES
DES
DES
Tf1
Tf2
Tf3
CK_t
CK_c
tCKPSTDQS
tCKPRDQS
CS
CKE
CA
CMD
MRW
MA
MRW
MA
MRW-1
WR Leveling
MRW
OP
MRW
OP
MRW-2
WR Leveling
DES
DES
DES
Deselect
Deselect
tWLDQSEN
DES
DES
DES
DES
DES
Deselect
DES
Deselect
DES
DES
Deselect
Deselect
DES
Deselect
DES
DES
Deselect
tDQSH
tDQSL
tWLWPRE
DQS_c
DQS_t
tWLMRD
tWLO
tWLO
tWLO
tWLO
DQ
Figure 117 - Clock Stop and Timing during Write Leveling
Notes
1. CK_t is held LOW and CK_c is held HIGH during clock stop.
2. CS shall be held LOW during clock clock stop.
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2.28. RD DQ Calibration
2.28.1. RD DQ Calibration for x16 mode
LPDDR4 devices feature a RD DQ Calibration training function that outputs a 16-bit user-defined pattern on the DQ pins. RD DQ Calibration is initiated by issuing a MPC [RD DQ Calibration] command followed by a CAS-2 command, cause the LPDDR4-SDRAM to
drive the contents of MR32 followed by the contents of MR40 on each of DQ[15:0] and DMI[1:0]. The pattern can be inverted on
selected DQ pins according to user-defined invert masks written to MR15 and MR20.
2.28.2. RD DQ Calibration Training Procedure
The procedure for executing RD DQ Calibration is:
• Issue MRW commands to write MR32 (first eight bits), MR40 (second eight bits), MR15 (eight-bit invert mask for
byte 0), and MR20 (eight-bit invert mask for byte 1)
o Optionally this step could be skipped to use the default patterns
• MR32 default = 5Ah
• MR40 default = 3Ch
• MR15 default = 55h
• MR20 default = 55h
• Issue an MPC [RD DQ Calibration] command followed immediately by a CAS-2 command
o Each time an MPC [RD DQ Calibration] command followed by a CAS-2 is received by the LPDDR4 SDRAM, a 16-bit data burst
will, after the currently set RL, drive the eight bits programmed in MR32 followed by the eight bits programmed in MR40 on all
I/O pins
o The data pattern will be inverted for I/O pins with a ‘1’ programmed in the corresponding invert mask mode register bit
(see Table "Invert Mask Assignments")
o Note that the pattern is driven on the DMI pins, but no data bus inversion function is enabled, even if Read DBI is enabled in
the DRAM mode register.
o The MPC-1 [RD DQ Calibration] command can be issued every tCCD seamlessly, and tRTRRD delay is required between Array
Read command and the MPC-1 [RD DQ Calibration] command as well the delay required between the MPC-1 [RD DQ Calibration]
command and an array read.
o The operands received with the CAS-2 command must be driven LOW
• DQ Read Training can be performed with any or no banks active, during Refresh, or during SREF with CKE high
Table 56 - Invert Mask Assignments
Pin
DQ8
DQ9
DQ10
DQ11
DMI1
DQ12
DQ13
DQ14
DQ15
MR20
OP0
OP1
OP2
OP3
N/A
OP4
OP5
OP6
OP7
Pin
DQ0
DQ1
DQ2
DQ3
DMI0
DQ4
DQ5
DQ6
DQ7
MR15
OP0
OP1
OP2
OP3
N/A
OP4
OP5
OP6
OP7
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T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Tb0
Tb1
Tb2
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Valid
Valid
Valid
Valid
Tc7
Td1
Td2
Td3
Td4
Td5
Td6
Te0
Te1
Te2 Te3
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES DES
CK_c
CK_t
CS
CA
COMMAND
Read-1
CAS-2
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
MPC
RD DQ Cal.
tRTRRD
RL
CAS-2
RL
tDQSCK
tDQSCK
tRPRE
tRPST
tRPRE
tRPST
DQS_c
DQS_t
Hi-Z
DQ
Hi-Z
Hi-Z
tDQSQ
Hi-Z
tDQSQ
n0 n13 n14 n15
Hi-Z
n0 n13 n14 n15
Hi-Z
Figure 118 - DQ Read Training Timing: Read to Read DQ Calibration
Notes
1. Read-1 to MPC [RD DQ Calibration] Operation is shown as an example of command-to-command timing. Timing from Read-1 to MPC [RD DQ Calibration] command is tRTRRD.
2. MPC [RD DQ Calibration] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a Read-1 command.
3. BL = 16, Read Preamble: Toggle, Read Postamble: 0.5nCK.
4. DES commands are shown for ease of illustration; other commands may be valid at these times.
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T0
T1
T2
T3
T8
T9
T10
T11
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
T12
T13
T14
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tc0
Tc1
Tc2
Tc3
Tc4
BL
BA0,
CA
CAn
CAn
Tc5
Td0
Td1
Td2
Td3
Td4
Te0 Te1
DES
DES
DES
DES
DES
DES
DES DES
CK_c
CK_t
CS
CA
COMMAND
MPC
RD DQ Cal.
CAS-2
DES
MPC
RD DQ Cal.
CAS-2
DES
DES
tCCD
RL
DES
DES
DES
DES
DES
DES
DES
DES
Read-1
CAS-2
tRTRRD
RL
tDQSCK
RL
tDQSCK
tDQSCK
tRPST
tRPRE
tRPRE
tRPST
DQS_c
DQS_t
Hi-Z
DQ
Hi-Z
Hi-Z
tDQSQ
tDQSQ
n0 n9 n10 n11 n12 n13 n14 n15 n0 n13 n14 n15
tDQSQ
Hi-Z
n0 n13 n14 n15
Figure 119 - DQ Read Training Timing: Read DQ Cal. to Read DQ Cal. / Read
Notes
1. MPC [RD DQ Calibration] to MPC [RD DQ Calibration] Operation is shown as an example of command-to-command timing.
2. MPC [RD DQ Calibration] to Read-1 Operation is shown as an example of command-to-command timing.
3. MPC [RD DQ Calibration] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a Read-1 command.
4. Seamless MPC [RD DQ Calibration] commands may be executed by repeating the command every tCCD time.
5. Timing from MPC [RD DQ Calibration] command to Read-1 is tRTRRD.
6. BL = 16, Read Preamble: Toggle, Read Postamble: 0.5nCK.
7. DES commands are shown for ease of illustration; other commands may be valid at these times.
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2.28.2.1. DQ Read Training Example
An example of MPC [RD DQ Calibration] output is shown in Table below. This shows the 16-bit data pattern that will be driven on
each DQ when one DQ Read Training command is executed. This output assumes the following mode register values are used:
• MR32 = 1CH
• MR40 = 59H
• MR15 = 55H
• MR20 = 55H
Table 57 - MPC [RD DQ Calibration] Bit Ordering and Inversion Example
Pin
DQ0
DQ1
DQ2
DQ3
DMI0
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DMI1
DQ12
DQ13
DQ14
DQ15
Bit sequence ->
Invert
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Yes
No
Yes
No
Never
Yes
No
Yes
No
Yes
No
Yes
No
Never
Yes
No
Yes
No
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
Notes
1. The patterns contained in MR32 and MR40 are transmitted on DQ[15:0] and DMI[1:0] when RD DQ Calibration is initiated via a MPC [RD DQ
Calibration] command. The pattern transmitted serially on each data lane, organized “little endian” such that the low order bit in a byte is
transmitted first. If the data pattern is 27H, then the first bit transmitted with be a ‘1’, followed by ‘1’, ‘1’, ‘0’, ‘0’, ‘1’, ‘0’, and ‘0’. The bit stream will
be 00100111.
2. MR15 and MR22 may be used to invert the MR32/MR40 data pattern on the DQ pins. See MR15 and MR20 for more information. Data is never
inverted on the DMI[1:0] pins.
3. DMI [1:0] outputs status follows in the table below
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Table 58 - MR Setting vs. DMI Status
DM Function
MR13 OP[5]
Write DBIdc Function
MR3 OP[7]
Read DBIdc Function
MR3 OP[6]
DMI Status
1: Disable
0: Disable
0: Disable
Hi-Z
1: Disable
1: Enable
0: Disable
The data pattern is transmitted
1: Disable
0: Disable
1: Enable
The data pattern is transmitted
1: Disable
1: Enable
1: Enable
The data pattern is transmitted
0: Enable
0: Disable
0: Disable
The data pattern is transmitted
0: Enable
1: Enable
0: Disable
The data pattern is transmitted
0: Enable
0: Disable
1: Enable
The data pattern is transmitted
0: Enable
1: Enable
1: Enable
The data pattern is transmitted
Notes
1. No Data Bus Inversion (DBI) function is enacted during RD DQ Calibration, even if DBI is enabled in MR3-OP[6].
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2.28.2.2. MPC of Read DQ Calibration after Power-Down Exit
Following the power-down state, an additional time, tMRRI, is required prior to issuing the MPC of Read DQ Calibration command.
This additional time (equivalent to tRCD) is required in order to be able to maximize power-down current savings by allowing more
power-up time for the Read DQ data in MR32 and MR40 data path after exit from standby, power-down mode.
T0
Ta0
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Td0
Td1
Td2
Td3
Td4
Td5 Td6
Td7
Td8
Td9
DES
DES
DES
CK_c
CK_t
tCKCKEH
CKE
tXP
tMRRI
CS
CA
COMMAND
Valid Valid Valid Valid
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
MPC
Read DQ Cal
CAS-2
DON'T CARE
TIME BREAK
Figure 120 - MPC Read DQ Calibration Following Power-Down State
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2.28.3. RD DQ Calibration for Byte (x8) mode
LPDDR4 devices feature a RD DQ Calibration training function that outputs a 8-bit user-defined pattern on the DQ pins. RD DQ Calibration is initiated by issuing a MPC [RD DQ Calibration] command followed by a CAS-2 command, cause the LPDDR4-SDRAM to
drive the contents of MR32 followed by the contents of MR40 on each of DQ[7:0] and DMI[0]. The pattern can be inverted on
selected DQ pins according to user-defined invert masks written to MR15 and MR20.
2.28.3.1. RD DQ Calibration Training Procedure
The procedure for executing RD DQ Calibration is:
• Issue MRW commands to write MR32 (first eight bits), MR40 (second eight bits), MR15 (eight-bit invert mask for
byte 0 : DQ[7:0]), and MR20 (eight-bit invert mask for byte 1 : DQ[15:8])
o Optionally this step could be skipped to use the default patterns
• MR32 default = 5Ah
• MR40 default = 3Ch
• MR15 default = 55h
• MR20 default = 55h
• Issue an MPC [RD DQ Calibration] command followed immediately by a CAS-2 command
o Each time an MPC [RD DQ Calibration] command followed by a CAS-2 is received by the LPDDR4 SDRAM,
a 16-bit data burst will, after the currently set RL, drive the eight bits programmed in MR32 followed by the
eight bits programmed in MR40 on all I/O pins
o The data pattern will be inverted for I/O pins with a ‘1’ programmed in the corresponding invert mask mode
register bit (see Table "Invert Mask Assignments")
o Note that the pattern is driven on the DMI pins, but no data bus inversion function is enabled, even if Read DBI
is enabled in the DRAM mode register.
o The MPC-1 [RD DQ Calibration] command can be issued every tCCD seamlessly, and tRTRRD delay is required
between Array Read command and the MPC-1 [RD DQ Calibration] command as well the delay required between
the MPC-1 [RD DQ Calibration] command and an array read.
o The operands received with the CAS-2 command must be driven LOW
• DQ Read Training can be performed with any or no banks active, during Refresh, or during SREF with CKE high
Table 59 - Invert Mask Assignments
Pin
DQ8
DQ9
DQ10
DQ11
DMI1
DQ12
DQ13
DQ14
DQ15
MR20
OP0
OP1
OP2
OP3
N/A
OP4
OP5
OP6
OP7
Pin
DQ0
DQ1
DQ2
DQ3
DMI0
DQ4
DQ5
DQ6
DQ7
MR15
OP0
OP1
OP2
OP3
N/A
OP4
OP5
OP6
OP7
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2.28.3.2. DQ Read Training Example Example
An example of MPC [RD DQ Calibration] output is shown in Table "MPC [RD DQ Calibration] Bit Ordering and Inversion Example". This
shows the 16-bit data pattern that will be driven on each DQ when one DQ Read Training command is executed. This output assumes
the following mode register values are used:
• MR32 = 1CH
• MR40 = 59H
• MR15 = 55H
• MR20 = 55H
Table 60 - DQ Read Calibration Bit Ordering and Inversion Example
Pin
Invert
DQ0 (DQ8)
DQ1 (DQ9)
DQ2 (DQ10)
DQ3 (DQ11)
DMI0 (DMI1)
DQ4 (DQ12)
DQ5 (DQ13)
DQ6 (DQ14)
DQ7 (DQ15)
Yes
No
Yes
No
Never
Yes
No
Yes
No
Bit sequence ->
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
Notes
1. The patterns contained in MR32 and MR40 are transmitted on lower byte select : DQ[7:0] or upper byte select : DQ[15:8], DMI[0] or DMI[1]
when RD DQ Calibration is initiated via a MPC [RD DQ Calibration] command. The pattern transmitted serially on each data lane, organized “little
endian” such that the low order bit in a byte is transmitted first. If the data pattern is 27H, then the first bit transmitted with be a ‘1’, followed by
‘1’, ‘1’, ‘0’, ‘0’, ‘1’, ‘0’, and ‘0’. The bit stream will be 00100111.
2. MR15 and MR22 may be used to invert the MR32/MR40 data pattern on the DQ pins. See MR15 and MR20 for more information. Data is never
inverted on the DMI[0] pins.
3. The data pattern is not transmitted on the DMI[0] or DMI[1] pins if DBI-RD is disabled via MR3 OP[6].
4. No Data Bus Inversion (DBI) function is enacted during RD DQ calibration, even if DBI is enabled in MR3 OP[6].
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2.29. DQS-DQ Training
The LPDDR4-SDRAM uses an un-matched DQS-DQ path to enable high speed performance and save power in the DRAM. As a result,
the DQS strobe must be trained to arrive at the DQ latch center-aligned with the Data eye. The SDRAM DQ receiver is located at the
DQ pad, and has a shorter internal delay in the SDRAM than does the DQS signal. The SDRAM DQ receiver will latch the data present
on the DQ bus when DQS reaches the latch, and training is accomplished by delaying the DQ signals relative to DQS such that the
Data eye arrives at the receiver latch centered on the DQS transition.
Two modes of training are available in LPDDR4:
- Command-based FIFO WR/RD with user patterns
- A internal DQS clock-tree oscillator, to determine the need for, and the magnitude of, required training.
The command-based FIFO WR/RD uses the MPC command with operands to enable this special mode of operation. When issuing the
MPC command, if OP6 is set LOW then the DRAM will perform a NOP command. When OP6 is set HIGH, then OP5:0 enable training
functions or are reserved for future use (RFU). MPC commands that initiate a Read FIFO, READ DQ Calibration or Write FIFO to the
SDRAM must be followed immediately by a CAS-2 command. See "Multi Purpose Command (MPC) Definition" for more information.
To perform Write Training, the controller can issue a MPC [Write DQ FIFO] command with OP[6:0] set as described in the MPC Definition section, followed immediately by a CAS-2 command (CAS-2 operands should be driven LOW) to initiate a Write DQ FIFO. Timings for MPC [Write DQ FIFO] are identical to a Write command, with WL (Write Latency) timed from the 2nd rising clock edge of the
CAS-2 command. Up to 5 consecutive MPC [Write DQ FIFO] commands with user defined patterns may be issued to the SDRAM to
store up to 80 values (BL16 x5) per pin that can be read back via the MPC [Read DQ FIFO] command. Write/Read FIFO Pointer operation is described later in this section.
After writing data to the SDRAM with the MPC [Write DQ FIFO] command, the data can be read back with the MPC [Read DQ FIFO]
command and results compared with “expect” data to see if further training (DQ delay) is needed. MPC [Read DQ FIFO] is initiated
by issuing a MPC command with OP[6:0] set as described in the MPC Definition section, followed immediately by a CAS-2 command
(CAS-2 operands must be driven LOW). Timings for the MPC [Read DQ FIFO] command are identical to a Read command, with RL
(Read Latency) timed from the 2nd rising clock edge of the CAS-2 command.
Read DQ FIFO is non-destructive to the data captured in the FIFO, so data may be read continuously until it is either overwritten by
a Write DQ FIFO command or disturbed by CKE LOW or any of the following commands; Write, Masked Write, Read, Read DQ Calibration and a MRR. If fewer than 5 Write DQ FIFO commands were executed, then unwritten registers will have un-defined (but
valid) data when read back.
The following command about MRW is only allowed from MPC [Write DQ FIFO] command to MPC [Read DQ FIFO].
Allowing MRW command is for OP[7]:FSP-OP, OP[6]:FSP-WR and OP[3]:VRCG of MR13 and MR14. And the rest of MRW command is
prohibited. For example: If 5 Write DQ FIFO commands are executed sequentially, then a series of Read DQ FIFO commands will
read valid data from FIFO[0], FIFO[1]….FIFO[4], and will then wrap back to FIFO[0] on the next Read DQ FIFO.
On the other hand, if fewer than 5 Write DQ FIFO commands are executed sequentially (example=3), then a series of Read DQ FIFO
commands will return valid data for FIFO[0], FIFO[1], and FIFO[2], but the next two Read DQ FIFO commands will return un-defined
data for FIFO[3] and FIFO[4] before wrapping back to the valid data in FIFO[0].
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2.29.1. FIFO Pointer Reset and Synchronism
The Write DQ FIFO pointer is reset under the following conditions:
- Power-up initialization
- RESET_n asserted
- Power-down entry
- Self Refresh Power-Down entry
The MPC [Write DQ FIFO] command advances the WR-FIFO pointer, and the MPC [Read DQ FIFO] advances the RD-FIFO pointer.
Also any normal (non-FIFO) Read Operation (RD, RDA) advances both WR-FIFO pointer and RD-FIFO pointer. Issuing (non-FIFO)
Read Operation command is inhibited during Write training period. To keep the pointers aligned, the SoC memory controller must
adhere to the following restriction at the end of Write training period:
b=a+(n*c)
Where:
‘a’ is the number of MPC [Write DQ FIFO] commands
‘b’ is the number of MPC [Read DQ FIFO] commands
‘c’ is the FIFO depth (=5 for LPDDR4)
‘n’ is a positive integer, ≥ 0
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T0
T1
T2
T3
BL
BA0,
CA
CAn
CAn
Ta0
T4
Ta1
Ta2
Tb0
Tb1
Tc0
Tc1
Tc2
Tc3
Tc4
Valid
Valid
Valid
Valid
Tc5
Td0
Td1
Td2
Td3
Td4
Valid
Valid
Valid
Valid
Td5
Te0
Te1
Te2
Tf0
Tf1
Tg0
Tg1
Tg2 Tg3
DES
DES
DES
DES
DES
DES
DES
DES
DES DES
CK_c
CK_t
CS
CA
COMMAND
Write-1
CAS-2
DES
DES
DES
DES
DES
DES
DES
MPC
WR FIFO
CAS-2
DES
tWRWTR
DES
MPC
WR FIFO
CAS-2
tCCD = 8
WL
WL
WL
tDQSS
tWPRE
tDQSS
tWPST
tWPRE
tDQSS
tWPST
DQS_c
DQS_t
Don’t Care
DQ
Don’t Care
Don’t Care
tDQS2DQ
Don’t Care
tDQS2DQ
n0 n13 n14 n15
Don’t Care
tDQS2DQ
n0 n13 n14 n15 n0 n13 n14 n15
Don’t Care
Figure 121 - MPC [Write DQ FIFO] Operation Timing
Notes
1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. Write-1 to MPC is shown as an example of command-to-command timing for MPC. Timing from Write-1 to MPC [WR-FIFO] is tWRWTR.
3. Seamless MPC [WR-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC [WR-FIFO] uses the same command-to-data timing relationship (WL, tDQSS, tDQS2DQ) as a Write-1 command.
5. A maximum of 5 MPC [WR-FIFO] commands may be executed consecutively without corrupting FIFO data. The 6th MPC [WR-FIFO] command will overwrite the FIFO data from the first command.
If fewer than 5 MPC [WR-FIFO] commands are executed, then the remaining FIFO locations will contain undefined data.
6. For the CAS-2 command following a MPC command, the CAS-2 operands must be driven “LOW.”
7. To avoid corrupting the FIFO contents, MPC [RD-FIFO] must immediately follow MPC [WR-FIFO]/CAS-2 without any other command disturbing FIFO pointers in-between.
FIFO pointers are disturbed by CKE Low, Write, Masked Write, Read, Read DQ Calibration and MRR.
8. BL = 16, Write Postamble = 0.5nCK
9. DES commands are shown for ease of illustration; other commands may be valid at these times.
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T0
T1
T2
T3
Valid
Valid
Valid
Valid
Ta0
T4
Ta1
Ta2
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Tc3
Tc4
Valid
Valid
Valid
Valid
Tc5
Td0
Td1
Td2
Td3
Td4
Valid
Valid
Valid
Valid
Td5
Te0
Te1
Te2
Te3
Tf0
Tf1
Tg0 Tg1
DES
DES
DES
DES
DES
DES
DES
DES DES
CK_c
CK_t
CS
CA
COMMAND
MPC
WR FIFO
CAS-2
DES
DES
DES
DES
WL
DES
DES
BL/2 + 1 Clock
DES
DES
MPC
RD FIFO
tWTR
CAS-2
DES
DES
MPC
RD FIFO
CAS-2
tCCD = 8
RL
tDQSCK
tDQSS
tWPRE
tWPST
tRPRE
tRPST
DQS_c
DQS_t
Don’t Care
Hi-Z/Don’t Care
tDQS2DQ
DQ
Don’t Care
tDQSQ
n0 n13 n14 n15
Hi-Z/Don’t Care
n0 n13 n14 n15 n0 n13 n14 n15
Figure 122 - MPC [Write FIFO] to MPC [Read FIFO] Timing
Notes
1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. MPC [WR-FIFO] to MPC [RD-FIFO] is shown as an example of command-to-command timing for MPC. Timing from MPC [WR-FIFO] to MPC [RD-FIFO] is specified in the command-to-command
timing table.
3. Seamless MPC [RD-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC [RD-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a Read-1 command.
5. Data may be continuously read from the FIFO without any data corruption. After 5 MPC [RD-FIFO] commands the FIFO pointer will wrap back to the 1st FIFO and continue advancing.
If fewer than 5 MPC [WR-FIFO] commands were executed, then the MPC [RD-FIFO] commands to those FIFO locations will return undefined data. See the Write Training section for more
information on the FIFO pointer behavior.
6. For the CAS-2 command immediately following a MPC command, the CAS-2 operands must be driven “LOW.”
7. DMI[1:0] signals will be driven if any of WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training section for more information on DMI behavior.
8. BL = 16, Write Postamble = 0.5nCK, Read Preamble: Toggle, Read Postamble: 0.5nCK
9. DES commands are shown for ease of illustration; other commands may be valid at these times.
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T0
T1
T2
T3
Valid
Valid
Valid
Valid
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Tb0
Tb1
Tb2
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
BL
BA0,
CA
CAn
CAn
Tc7
Td1
Td2
Td3
Td4
Td5
Td6
Te0
Te1
Te2 Te3
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES DES
CK_c
CK_t
CS
CA
COMMAND
MPC
RD FIFO
CAS-2
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Read-1
CAS-2
tRTRRD
RL
RL
tDQSCK
tDQSCK
tRPST
tRPRE
tRPRE
tRPST
DQS_c
DQS_t
Hi-Z
DQ
Hi-Z
Hi-Z
tDQSQ
Hi-Z
tDQSQ
n0 n13 n14 n15
Hi-Z
n0 n13 n14 n15
Hi-Z
Figure 123 - MPC [Read FIFO] to Read Timing
Notes
1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. MPC [RD-FIFO] to Read-1 Operation is shown as an example of command-to-command timing for MPC. Timing from MPC [RD-FIFO] command to Read is tRTRRD.
3. Seamless MPC [RD-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC [RD-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a Read-1 command.
5. Data may be continuously read from the FIFO without any data corruption. After 5 MPC [RD-FIFO] commands the FIFO pointer will wrap back to the 1st FIFO and continue advancing.
If fewer than 5 MPC [WR-FIFO] commands were executed, then the MPC [RD-FIFO] commands to those FIFO locations will return undefined data. See the Write Training section for more
information on the FIFO pointer behavior.
6. For the CAS-2 command immediately following a MPC command, the CAS-2 operands must be driven “LOW.”
7. DMI[1:0] signals will be driven if any of WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training section for more information on DMI behavior.
8. BL = 16, Read Preamble: Toggle, Read Postamble: 0.5nCK
9. DES commands are shown for ease of illustration; other commands may be valid at these times.
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T0
T1
T2
T3
Valid
Valid
Valid
Valid
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Tb0
Tb1
Tb2
Tb3
Tb4 Tb5
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Tb6
CK_c
CK_t
CS
CA
COMMAND
MPC
WR FIFO
CAS-2
DES
DES
WL
tDQSS
tWPST
tWPRE
DQS_c
DQS_t
Don’t Care
DQ
Don’t Care
Don’t Care
tDQS2DQ
n0 n1 n2 n13 n14 n15
ODTLon
Don’t Care
tODTon.Max
tODTon.Min
DRAM RTT
ODT Hi-Z
Transition
ODT On
Transition ODT Hi-Z
ODTLoff
tODToff.Min
tODToff.Max
Note
Figure 124 - MPC [Write FIFO] with DQ ODT Timing
Notes
1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. MPC [WR-FIFO] uses the same command-to-data/ODT timing relationship (WL, tDQSS, tDQS2DQ, ODTLon, ODTLoff, tODTon, tODToff) as a Write-1 command.
3. For the CAS-2 command immediately following a MPC command, the CAS-2 operands must be driven “LOW.”
4. BL = 16, Write Postamble = 0.5nCK
5. DES commands are shown for ease of illustration; other commands may be valid at these times.
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T0
Ta0
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Td0
Td1
Td2
Td3
Td5
Td4
Td6
Td7
Td8
Td9
CK_c
CK_t
tCKCKEH
CKE
tXP
tMPCWR ( = tRCD + 3nCK)
WL
CS
CA
Valid
Valid
Valid
Valid
Valid
*1
COMMAND
DES
DES
Any Command
Any Command
DES
DES
DES
DES
Valid
Valid
MPC
WR FIFO
Valid
CAS-2
DES
DON'T CARE
Note
DES
DES
TIME BREAK
Figure 125 - Power Down Exit to MPC [Write FIFO] Timing
Notes
1. Any commands except MPC WR FIFO and other exception commands defined other section in this document (i.e. MPC Read DQ Cal).
2. DES commands are shown for ease of illustration; other commands may be valid at these times.
Parameter
Symbol
Min/Max
Data Rate
Unit
Min
tRCD+3nCK
-
Note
MPC Write FIFO Timing
Additional time After tXP has expired until
MPC [Write FIFO] CMD may be issued
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2.30. DQS Interval Oscillator
As voltage and temperature change on the SDRAM die, the DQS clock tree delay will shift and may require re-training. The LPDDR4SDRAM includes an internal DQS clock-tree oscillator to measure the amount of delay over a given time interval (determined by the
controller), allowing the controller to compare the trained delay value to the delay value seen at a later time. The DQS Oscillator will
provide the controller with important information regarding the need to re-train, and the magnitude of potential error.
The DQS Interval Oscillator is started by issuing a MPC [Start DQS Osc] command with OP[6:0] set as described in the MPC Operation section, which will start an internal ring oscillator that counts the number of time a signal propagates through a copy of the DQS
clock tree.
The DQS Oscillator may be stopped by issuing a MPC [Stop DQS Osc] command with OP[6:0] set as described in the MPC Operation
section, or the controller may instruct the SDRAM to count for a specific number of clocks and then stop automatically (See MR23 for
more information). If MR23 is set to automatically stop the DQS Oscillator, then the MPC [Stop DQS Osc] command should not be
used (illegal). When the DQS Oscillator is stopped by either method, the result of the oscillator counter is automatically stored in
MR18 and MR19.
The controller may adjust the accuracy of the result by running the DQS Interval Oscillator for shorter (less accurate) or longer (more
accurate) duration. The accuracy of the result for a given temperature and voltage is determined by the following equation:
DQS Oscillator Granularity Error = 2 * (DQS delay) / run time
Where:
Run Time = total time between start and stop commands
DQS delay = the value of the DQS clock tree delay (tDQS2DQ min/max)
Additional matching error must be included, which is the difference between DQS training circuit and the actual DQS clock tree
across voltage and temperature. The matching error is vendor specific.
Therefore, the total accuracy of the DQS Oscillator counter is given by:
DQS Oscillator Accuracy = 1 - Granularity Error - Matching Error
For example: If the total time between start and stop commands is 100ns, and the maximum DQS clock tree delay is 800ps
(tDQS2DQ max), then the DQS Oscillator Granularity Error is:
DQS Oscillator Granularity Error = 2*(0.8ns) / 100ns = 1.6%
This equates to a granularity timing error or 12.8ps.
Assuming a circuit Matching Error of 5.5ps across voltage and temperature, then the accuracy is:
DQS Oscillator Accuracy = 1 - [(12.8+5.5) / 800] = 97.7%
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For example: running the DQS oscillator for a longer period improves the accuracy. If the total time between start and stop commands is 500ns, and the maximum DQS clock tree delay is 800ps (tDQS2DQ max), then the DQS Oscillator Granularity Error is:
DQS Oscillator Granularity Error = 2*(0.8ns) / 500ns = 0.32%
This equates to a granularity timing error or 2.56ps.
Assuming a circuit Matching Error of 5.5ps across voltage and temperature, then the accuracy is:
DQS Oscillator Accuracy = 1 - [(2.56+5.5) / 800] = 99.0%
The result of the DQS Interval Oscillator is defined as the number of DQS Clock Tree Delays that can be counted within the “run
time,” determined by the controller. The result is stored in MR18-OP[7:0] and MR19-OP[7:0]. MR18 contains the least significant bits
(LSB) of the result, and MR19 contains the most significant bits (MSB) of the result. MR18 and MR19 are overwritten by the SDRAM
when a MPC-1 [Stop DQS Osc] command is received. The SDRAM counter will count to its maximum value (=2^16) and stop. If the
maximum value is read from the mode registers, then the memory controller must assume that the counter overflowed the register
and discard the result. The longest “run time” for the oscillator that will not overflow the counter registers can be calculated as follows:
Longest Run Time Interval = 216 * tDQS2DQ(min) = 216 * 0.2ns = 13.1us
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2.30.1. Interval Oscillator matching error
The interval oscillator matching error is defined as the difference between the DQS training ckt(interval oscillator) and the actual DQS
clock tree across voltage and temperature.
Parameters:
- tDQS2DQ: Actual DQS clock tree delay
- tDQSOSC: Training ckt (interval oscillator) delay
- OSCOffset: Average delay difference over voltage and temp (shown in the Figure below)
- OSCMatch: DQS oscillator matching error
Offset 2
tDQS2DQ
tDQS osc
Time
(ps)
OSC offset = avg(offset1,offset2)
Offset 1(at end point) = tDQS2DQ(V,T) - tDQS osc (V,T)
Offset 2(at end point) = tDQS2DQ(V,T) - tDQS osc (V,T)
Offset 1
Temp(T)/Voltage(V)
Figure 126 - Interval oscillator offset (OSCoffset)
OSCMatch :
tDQSOSC :
OSCMatch = [tDQS2DQ(V,T) - tDQSOSC(V,T) - OSCoffset ]
tDQSOSC(V,T) = Runtime / 2 * Count
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Table 61 - DQS Oscillator Matching Error Specification
Parameter
Symbol
Min
Max
Units
Notes
DQS Oscillator Matching Error
OSCMatch
-20
20
ps
1,2,3,4,5,6,7
DQS Oscillator Offset
OSCoffset
-100
100
ps
2,4,7
Notes
1. The OSCMatch is the matching error per between the actual DQS and DQS interval oscillator over voltage and temp.
2. This parameter will be characterized or guaranteed by design.
3. The OSCMatch is defined as the following:
OSCMatch = [tDQS2DQ(V,T) - tDQSOSC(V,T) - OSCoffset ]
Where tDQS2DQ(V,T) and tDQSOSC(V,T) are determined over the same voltage and temp conditions.
4. The runtime of the oscillator must be at least 200ns for determining tDQSOSC(V,T)
tDQSOSC(V,T) = Runtime / 2 * Count
5.
6.
7.
8.
The input stimulus for tDQS2DQ will be consistent over voltage and temp conditions.
The OSCoffset is the average difference of the endpoints across voltage and temp.
These parameters are defined per channel.
tDQS2DQ(V,T) delay will be the average of DQS to DQ delay over the runtime period.
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2.30.2. DQS Interval Oscillator Readout Timing
OSC Stop to its counting value readout timing is shown in following Figures:
T0
T1
T2
Valid
Valid
T3
T4
T5
Ta0
Ta1
Ta2
Valid
Valid
Ta3
Ta4
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
Valid
Valid
Valid
Valid
Tb6
CK_c
CK_t
CKE
CS
CA
COMMAND
DES
MPC :Start
MR Write-2
DQS
Oscillator
DES
DES
DES
DES
MPC :Stop
DQS Oscillator
DES
DES
DES
MRR-1
MR18/MR19
DES
CAS-2
tOSCO
Figure 127 - In case of DQS Interval Oscillator is stopped by MPC Command
Notes
1. DQS interval timer run time setting : MR23 OP[7:0] = 00000000
2. DES commands are shown for ease of illustration; other commands may be valid at these times.
T0
T1
T2
Valid
Valid
T3
T4
T5
Ta0
Ta1
Ta2
Ta3
Ta4
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
Valid
Valid
Valid
Valid
Tb6
CK_c
CK_t
CKE
CS
CA
COMMAND
DES
MPC :Start
MR Write-2
DQS
Oscillator
DES
DES
DES
DES
DES
DES
DES
DES
DES
See Note 2
MRR-1
MR18/MR19
DES
CAS-2
tOSCO
Figure 128 - In case of DQS Interval Oscillator is stopped by DQS interval timer
Notes
1. DQS interval timer run time setting : MR23 OP[7:0] ≠ 00000000
2. Setting counts of MR23
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
Parameter
Symbol
Min/Max
Data Rate
Unit
Delay time from OSC stop to Mode Register Readout
tOSCO
Min
Max (40ns, 8nCK)
tCK
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2.31. Read Preamble Training
LPDDR4 READ Preamble Training is supported through the MPC function.
This mode can be used to train or read level the DQS receivers. Once READ Preamble Training is enabled by MR13[OP1] = 1, the
LPDDR4 DRAM will drive DQS_t LOW, DQS_c HIGH within tSDO and remain at these levels until an MPC DQ READ Training command
is issued.
During READ Preamble Training the DQS preamble provided during normal operation will not be driven by the DRAM. Once the MPC
DQ READ Training command is issued, the DRAM will drive DQS_t/DQD_c like a normal READ burst after RL. DRAM may or may not
drive DQ[15:0] in this mode.
While in READ Preamble Training Mode, only READ DQ Calibration commands may be issued.
•Issue an MPC [RD DQ Calibration] command followed immediately by a CAS-2 command.
• Each time an MPC [RD DQ Calibration] command followed by a CAS-2 is received by the LPDDR4 SDRAM,
a 16-bit data burst will, after the currently set RL, drive the eight bits programmed in MR32 followed by the eight
bits programmed in MR40 on all I/O pins.
• The data pattern will be inverted for I/O pins with a '1' programmed in the corresponding invert mask mode
register bit.
• Note that the pattern is driven on the DMI pins, but no data bus inversion function is enabled, even if Read DBI
is enabled in the DRAM mode register.
• This command can be issued every tCCD seamlessly.
• The operands received with the CAS-2 command must be driven LOW.
READ Preamble Training is exited within tSDO after setting MR13[OP1] = 0.
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T4
Ta0
Ta1
Ta6
Tb0
Tb1
Tc0
Tc1
Tc2
Tc3
Tc4
Td0
Td4
Te0
Te1
COMMAND MRW-1 MRW-1 MRW-2 MRW-2 DES
DES
MPC-1 MPC-1
DES RD Cal. RD Cal. CAS-2 CAS-2 DES
DES
DES
DES
DES
DES
DES
DES
DES MRW-1 MRW-1 MRW-2 MRW-2 DES
DES
DES
T0
T1
T2
T3
Ta2 Ta3
Ta4
Ta4
Td1
Td2 Td3
Td4
CK_c
CK_t
CS
tSDO
RL
tDQSCK
tSDO
Read Preamble Training Mode = Enable: MR13[OP1] = 1
Read Preamble Training Mode = Disable: MR13[OP1] = 0
DQS_c
DQS_t
tDQSQ
DQ
Dout Dout Dout Dout Dout Dout
n0 n1 n12 n13 n14 n15
DQ (High-Z or Driven )
DQ (High-Z or Driven )
Figure 129 - Read Preamble Training
Notes
1. Read DQ Calibration supports only BL16 operation
Parameter
Symbol
Min
Value
Units
Delay from MRW command to DQS Driven
tSDO
Min
Max(12nCK, 20ns)
-
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2.32. Multi-Purpose Command (MPC)
LPDDR4-SDRAMs use the MPC command to issue a NOP and to access various training modes. The MPC command is initiated with
CS, and CA[5:0] asserted to the proper state at the rising edge of CK, as defined by the Command Truth Table. The MPC command
has seven operands (OP[6:0]) that are decoded to execute specific commands in the SDRAM. OP[6] is a special bit that is decoded
on the first rising CK edge of the MPC command. When OP[6]=0 then the SDRAM executes a NOP (no operation) command, and
when OP[6]=1 then the SDRAM further decodes one of several training commands.
When OP[6]=1 and when the training command includes a Read or Write operation, the MPC command must be followed immediately by a CAS-2 command. For training commands that Read or Write the SDRAM, read latency (RL) and write latency (WL) are
counted from the second rising CK edge of the CAS-2 command with the same timing relationship as any normal Read or Write command. The operands of the CAS-2 command following a MPC Read/Write command must be driven LOW. The following MPC commands must be followed by a CAS-2 command:
- Write FIFO
- Read FIFO
- Read DQ Calibration
All other MPC commands do not require a CAS-2 command, including:
- NOP
- Start DQS Interval Oscillator
- Stop DQS Interval Oscillator
- Start ZQ Calibration
- Latch ZQ Calibration
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Table 62 - MPC Command Definition
SDR Command Pins (2)
Command
CKE
CK_t(n-1)
CK_t(n)
H
H
Multi Purpose
Command (MPC)
Function
Training Modes
Operand
OP[6:0]
SDR CA Pins (6)
CS
CA0
CA1
CA2
CA3
CA4
CA5
CK_t
edge
H
L
L
L
L
L
OP6
R1
L
OP0
OP1
OP2
OP3
OP4
OP5
R2
Data
0XXXXXXB: NOP
1000001B: RD FIFO
1000011B: RD DQ Calibration (MR32/MR40)
1000101B: RFU
1000111B: WR FIFO
1001001B: RFU
1001011B: Start DQS Osc
1001101B: Stop DQS Osc
1001111B: ZQCal Start
1010001B: ZQCal Latch
All Others: Reserved
Notes
1,2
Notes
1,2,3
Notes
1. See Command Truth Table for more information
2. MPC commands for Read or Write training operations must be immediately followed by CAS-2 command consecutively without any other
commands in between. MPC command must be issued first before issuing the CAS-2 command.
3. Write FIFO and Read FIFO commands will only operate as BL 16, ignoring the burst length selected by MR1 OP[1:0].
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CK_t
CK_c
tCCD
tWRWTR
CA
Write
Write
CAS-2
CAS-2
VALID
VALID
MPC
MPC
CAS-2
CAS-2
VALID
VALID
MPC
MPC
CAS-2
CAS-2
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
WL
CMD
Write-1
CAS-2
VALID
MPC
CAS-2
Write FIFO
VALID
MPC
CAS-2
Write FIFO
VALID
tDQSS
WL
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
tDQSS
DQS_t
DQS_c
tDQS2DQ
tWPRE
tDQS2DQ
DQ[15:0]
D0 D1 D2 D7 D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D15
DM[1:0]
Figure 130 - MPC [WR FIFO] Operationt :WPRE =2nCK, tWPST = 0.5nCK
Notes
1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. Write-1 to MPC is shown as an example of command-to-command timing for MPC. Timing from Write-1 to MPC [WR-FIFO] is tWRWTR.
3. Seamless MPC [WR-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC [WR-FIFO] uses the same command-to-data timing relationship (WL, tDQSS, tDQS2DQ) as a Write-1 command.
5. A maximum of 5 MPC [WR-FIFO] commands may be executed consecutively without corrupting FIFO data. The 6th MPC [WR-FIFO] command
will overwrite the FIFO data from the first command. If fewer than 5 MPC [WR-FIFO] commands are executed, then the remaining FIFO locations
will contain undefined data.
6. For the CAS-2 command following a MPC command, the CAS-2 operands must be driven “LOW.”
7. To avoid corrupting the FIFO contents, MPC [RD-FIFO] must immediately follow MPC [WR-FIFO]/CAS-2 without any other command disturbing
FIFO pointers in-between. FIFO pointers are disturbed by CKE Low, Write, Masked Write, Read, Read DQ Calibration and MRR.
See Write Training section for more information on FIFO pointer behavior.
CK_t
CK_c
tCCD
CA
CMD
VALID
VALID
MPC
Write FIFO
VALID
VALID
CAS-2
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
MPC
Read FIFO
VALID
CAS-2
VALID
VALID
VALID
VALID
VALID
MPC
Read FIFO
VALID
VALID
CAS-2
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
WL
tWTR
tDQSS
RL
tDQSCK
DQS_t
DQS_c
tWPRE
tDQS2DQ
tRPRE
tRPST
DQ[15:0]
D0 D13 D14 D15
D0 D1 D2 D15 D4 D13 D14 D15
DM[1:0]
Figure 131 - MPC [RD FIFO] Read Operation (Shown with tWPRE=2nCK, tWPST=0.5nCK, tRPRE=toggling, tRPST=1.5nCK)
Notes
1. MPC [WR FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. MPC [WR FIFO] to MPC [RD FIFO] is shown as an example of command-to-command timing for MPC.
3. Seamless MPC [RD-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC [RD-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK) as a Read-1 command.
5. Data may be continuously read from the FIFO without any data corruption. After 5 MPC [RD-FIFO] commands the FIFO pointer will wrap back
to the 1st FIFO and continue advancing. If fewer than 5 MPC [WR-FIFO] commands were executed, then the MPC [RD-FIFO] commands to those
FIFO locations will return undefined data. See the Write Training section for more information on the FIFO pointer behavior.
6. For the CAS-2 command immediately following a MPC command, the CAS-2 operands must be driven “LOW.”
7. DMI[1:0] signals will be driven if any of WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training section for more information
on DMI behavior.
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CK_t
CK_c
tRTRRD
CA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
RL
CMD
MPC
Read FIFO
CAS-2
VALID
VALID
Read
RL
CAS-2
VALID
VALID
VALID
tDQSCK
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
tDQSCK
DQS_t
DQS_c
tRPRE
tRPST
tRPRE
tRPST
DQ[15:0]
D0 D1 D2 D3 D4 D13 D14 D15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
DM[1:0]
Figure 132 - MPC [RD FIFO] Operation (Shown with tRPRE=toggling, tRPST=1.5nCK)
Notes
1. MPC [RD FIFO] can be executed with a single bank or multiple banks active, during Refresh, or during SREF with CKE HIGH.
2. MPC [RD-FIFO] to Read-1 Operation is shown as an example of command-to-command timing for MPC. Timing from MPC [RD-FIFO] command to
Read is tRTRRD.
3. Seamless MPC [RD-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC [RD-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK) as a Read-1 command.
5. Data may be continuously read from the FIFO without any data corruption. After 5 MPC [RD-FIFO] commands the FIFO pointer will wrap back
to the 1st FIFO and continue advancing. If fewer than 5 MPC [WR-FIFO] commands were executed, then the MPC [RD-FIFO] commands to those
FIFO locations will return undefined data. See the Write Training section for more information on the FIFO pointer behavior.
6. For the CAS-2 command immediately following a MPC command, the CAS-2 operands must be driven “LOW.”
7. DMI[1:0] signals will be driven if any of WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training section for more information
on DMI behavior.
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Table 63 - Timing Constraints for Training Commands
Previous
Command
WR/MWR
RD/MRR
MPC
[WR FIFO]
MPC
[RD FIFO]
MPC
[RD DQ Calibration]
Next Command
Minimum Delay
Unit
Notes
MPC [WR FIFO]
tWRWTR
nCK
1
MPC [RD FIFO]
Not Allowed
-
2
MPC [RD DQ Calibration]
WL+RU(tDQSS(max)/tCK)+BL/2+RU(tWTR/tCK)
nCK
MPC [WR FIFO]
tRTRRD
nCK
MPC [RD FIFO]
Not Allowed
MPC[RD DQ Calibration]
tRTRRD
4
2
nCK
3
WR/MWR
Not Allowed
MPC [WR FIFO]
tCCD
RD/MRR
Not Allowed
MPC [RD FIFO]
WL+RU(tDQSS(max)/tCK)+BL/2+RU(tWTR/tCK)
MPC [RD DQ Calibration]
Not Allowed
WR/MWR
tRTRRD
nCK
4
MPC [WR FIFO]
tRTW
nCK
4
RD/MRR
tRTRRD
nCK
3
2
nCK
2
nCK
2
MPC [RD FIFO]
tCCD
nCK
MPC [RD DQ Calibration]
tRTRRD
nCK
3
WR/MWR
tRTRRD
nCK
4
MPC [WR FIFO]
tRTRRD
nCK
4
nCK
RD/MRR
tRTRRD
MPC [RD FIFO]
Not Allowed
MPC [RD DQ Calibration]
tCCD
3
2
nCK
Notes
1. tWRWTR = WL + BL/2 + RU(tDQSS(max)/tCK) + max(RU(7.5ns/tCK), 8nCK)
2. No commands are allowed between MPC [WR FIFO] and MPC [RD FIFO] except MRW commands related to training parameters.
3. tRTRRD = RL + RU(tDQSCK(max)/tCK) + BL/2 + RD(tRPST) + max(RU(7.5ns/tCK),8nCK)
4. tRTW (DQ ODT Disabled case; MR11 OP[2:0]=000b)
= RL + RU(tDQSCK(max)/tCK) + BL/2 - WL + tWPRE + RD(tRPST)
tRTW (DQ ODT Enabled case; MR11 OP[2:0]≠000b)
= RL + RU(tDQSCK(max)/tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon,min/tCK) + 1
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2.33. Thermal offset
Because of their tight thermal coupling with the LPDDR4 device, hot spots on an SOC can induce thermal gradients across the LPDDR4 device. As these hot spots may not be located near the device thermal sensor, the devices’ temperature compensated selfrefresh circuit may not generate enough refresh cycles to guarantee memory retention. To address this shortcoming, the controller
can provide a thermal offset that the memory uses to adjust its TCSR circuit to ensure reliable operation.
This offset is provided through MR4(6:5) to either or to both the channels. This temperature offset may modify refresh behavior for
the channel to which the offset is provided. It will take a max of 200us to have the change reflected in MR4(2:0) for the channel to
which the offset is provided. If the induced thermal gradient from the device temperature sensor location to the hot spot location of
the controller is larger than 15 degrees C, then self-refresh mode will not reliably maintain memory contents.
To accurately determine the temperature gradient between the memory thermal sensor and the induced hot spot, the memory thermal sensor location must be provided to the LPDDR4 memory controller.
Support of thermal offset function is optional. Please refer to vendor data sheet to figure out if the function is supported or not.
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2.34. Temperature Sensor
LPDDR4 devices feature a temperature sensor whose status can be read from MR4. This sensor can be used to determine an appropriate refresh rate, determine whether AC timing de-rating is required in the elevated temperature range, and/or monitor the operating temperature. Either the temperature sensor or the device TOPER may be used to determine whether operating temperature
requirements are being met.
LPDDR4 devices shall monitor device temperature and update MR4 according to tTSI. Upon exiting self-refresh or power-down, the
device temperature status bits shall be no older than tTSI.
When using the temperature sensor, the actual device case temperature may be higher than the TOPER specification that applies for
the standard or elevated temperature ranges. For example, TCASE may be above 85oC when MR4[2:0] equals ‘b011. LPDDR4
devices shall allow for 2oC temperature margin between the point at which the device updates the MR4 value and the point at which
the controller re-configures the system accordingly. In the case of tight thermal coupling of the memory device to external hot spots,
the maximum device temperature might be higher than what is indicated by MR4.
To assure proper operation using the temperature sensor, applications should consider the following factors:
• TempGradient is the maximum temperature gradient experienced by the memory device at the temperature ofinterest over a
range of 2oC.
• ReadInterval is the time period between MR4 reads from the system.
• TempSensorInterval (tTSI) is maximum delay between internal updates of MR4.
• SysRespDelay is the maximum time between a read of MR4 and the response by the system.
In order to determine the required frequency of polling MR4, the system shall use the maximum TempGradient and the maximum
response time of the system using the following equation:
TempGradient x (ReadInterval + tTSI + SysRespDelay)
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