HG74ALVC16835C

18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS Features l Ideal for Use in PC100 Registered DIMM l 0.5µ m CMOS Technology l 2.3 ~ 3.6 VCC Operation l Balanced Output Drive(±24mA) l Package Options Include Plastic Thin Shrink Small-Outline Packages, Shrink Small-Outline Packages (TSSOP 56 Pins, SSOP 56 Pins, TVSOP56 Pins) HG74ALVC16835C Jan 1999 General Description The HG74ALVC16835C is an 18-bit universal bus driver designed for 2.3V to 3.6 V VCC Operation. The Output-Enable(OE) controls data flow from A to Y. The device operates in transparent mode when the latch-enable(LE) input is high. When LE is low, the A data is latched if the clock input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the Outputs are in the high impedance state. OE should be tied to VCC through a pull up resistor to ensure the high impedance state during power up or power down. The HG74ALVC16835C is characterized for operation from -40°C to 85°C. Pin Configuration (TOP VIEW) NC NC Y1 GND Y2 Y3 Vcc Y4 Y5 Y6 GND Y7 Y8 Y9 Y10 Y11 Y12 GND Y13 Y14 Y15 Vcc Y16 Y17 GND Y18 OE LE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND NC A1 GND A2 A3 Vcc A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 Vcc A16 A17 GND A18 CLK GND Function Table INPUTS OE H L L L L L LE X H H L L L CLK X X X ↑ ↑ L or H A X L H L H X OUTPUT Y Z L H L H YO= =Output level before the indicated steady-state input conditions were established, provided that CLK is high before LE goes low. NC- No ineternal connection 1 Copyright ©1999, Hyundai Electronics Industries Co., Ltd. ELECTRONICS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS HG74ALVC16835C Jan 1999 Logic Diagram (positive logic) 27 OE 30 CLK LE 28 A1 54 3 1D C1 CLK Y1 TO 17 Other Channels Absolute Maximum Ratings Over Operating Free-air Temperature Range= Symbols VCC VI VO IIK IOK IO ICC IGND Tstg Parameter Supply Voltage Range Input Voltage Range (see note 1) Output Voltage Range (see note 1 and 2) Input Clamp Current Output Clamp Current Continuous Output Current Continuous Current through each VCC Continuous Current through each GND Storage Temperature Range Value -0.5 V to 4.6 V -0.5V to VCC+ 0.5V -0.5V to VCC+ 0.5V ±50 mA ±50 mA ± 50 mA + 100 mA -100 mA -65°C to 150°C Conditions VI < 0 VO VCC VO =0 to VCC =Stresses beyond those listed under “ absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating condition” is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. Note 1) The input and output voltage ratings may be exceeded if the input and output clamp current are observed. Note 2) This value is limited to 4.6 V maximum. 2 Copyright ©1999, Hyundai Electronics Industries Co., Ltd. ELECTRONICS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS HG74ALVC16835C Jan 1999 Recommended Operating Conditions (see Note 3) Symbols VCC VIH VIL VI VO IOH Parameter Supply Voltage High -level input Voltage Low-level input Voltage Input Voltage Output Voltage High-level output current 0 0 Value MIN 2.3 1.7 2 MAX 3.6 Units V V V V V V V mA mA mA mA mA mA ns/V °C Conditions VCC =2.3V to 2.7V VCC =2.7V to 3.6V VCC =2.3V to 2.7V VCC =2.7V to 3.6V IOL ∆t/∆v TA Low-level output current Input transition rise or fall rate Operating free-air temperature 0 -40 0.7 0.8 VCC VCC -12 -12 -24 12 12 24 10 85 VCC =2.3V VCC =2.7V VCC =3V VCC =2.3V VCC =2.7V VCC =3V Note 3) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Electrical Characteristics Over Recommended Operating Free-air Temperature Range Parameter Test Conditions IOH = -100µA IOH = - 6mA VOH IOH = -12mA IOH = -24 mA IOL = 100µA IOL = 6mA IOL = 12mA VIH =1.7V VIH =1.7V VIH = 2V VIH = 2V VIL = 0.7V VIL = 0.7V VIL = 0.8V VIL = 0.8V Min VCC− 0.2 2 1.7 2.2 2.4 2 0.2 0.4 0.7 0.4 0.55 ±5 ±10 40 750 3.5 5 VO= VCC or GND 7 ρF ρF Value Typ= Max Units VCC 2.3V to 3.6V 2.3V 2.3V 2.7V 3V 3V 2.3V to 3.6V 2.3V 2.3V 2.7V 3V 3.6V 3.6V 3.6V 3V to 3.6V 3.3V 3.3V V VOL V IL IOZ ICC ∆ICC Control Inputs CI Co Data Inputs Outputs IOL =24mA VI= VCC or GND VO = VCC or GND VI = VCC or GND IO = 0 One input at VCC - 0.6V, Other inputs at VCC or GND VI = VCC or GND µA = All typical Values are at VCC =3.3V, TA = 25°C. 3 Copyright ©1999, Hyundai Electronics Industries Co., Ltd. ELECTRONICS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS HG74ALVC16835C Jan 1999 Timing Requirements Over Recommended Operating Free-air Temperature Range(see figure1~10 ) Symbol fclock tW tsu Parameter Clock frequency Pulse Duration Setup time Condition Vcc=2.5V±0.2V Min Max 150 LE high CLK high or low Data before CLK↑ Data before LE↓ CLK high CLK low Data after CLK↑ CLK high Data after LE↓ or low 3.3 3.3 0.9 1.9 1.3 1.0 1.4 3.3 3.3 0.9 1.6 1.1 1.0 1.7 Vcc=2.7V Min Max 150 3.3 3.3 0.7 1.5 1 1.1 1.4 Vcc=3.3V±0.3V Min Max 150 MHz ns ns ns ns ns ns ns Unit th Hold time Switching Characteristics Over Recommended Operating Free-air Temperature Range Parameter fmax tpd ten Idis A LE CLK OE OE Input (From) Output VCC =2.5V± 0.2V VCC =2.7V VCC =3.3V±0.3V (to) Y Y Y Min 150 1 1.3 1.4 1.4 1 Max 4.2 5 5.5 5.5 4.5 Min 150 Max 4.2 4.9 5.2 5.6 4.3 Min 150 1 1.3 1.4 1.1 1.3 Max 3.6 4.2 4.5 4.6 3.9 Unit MHz ns ns ns ns ns Switching Characteristics From 0° C to 65° C, CL=50ρ F Parameter tpd Input (From) CLK Output (To) Y VCC=3.3V± 0.15V Min 1.7 Max 4.5 Unit ns Parameter Measurement (VCC=2.5V±0.2V) 2 x Vcc From Output Under Test 500 Ω S1 Open GND C L = 30pF ( see Note) Test tpd tPLZ / tPZL tPHZ /tPZH S1 Open 2 x VCC GND 500 Ω Figure 1. Load Circuit Note) CL includes probe and jig capacitance 4 Copyright ©1999, Hyundai Electronics Industries Co., Ltd. ELECTRONICS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS Voltage Waveforms HG74ALVC16835C Jan 1999 Timing Input tsu Data VCC /2 Input VCC VCC /2 0V th VCC VCC /2 0V Input VCC /2 tw VCC /2 0V VCC Figure 2. Set up and Hold Times Figure 3. Pulse Duration VCC Input VCC /2 VCC /2 0V tPHL tPLH VOH Output VCC/2 VCC /2 VOL Figure 4. Propagation Delay times Output Control (Low-level enabling) VCC /2 VCC /2 VCC 0V Output Waveform 1 S1 at 2 x VCC (See Note 1 ) tPZL VCC /2 tPLZ VCC VOL + 0.15V VOL tPZH Output Waveform 2 S1 at GND (See Note 1 ) VCC /2 tPHZ VOH VOH - 0.15V 0V Figure 5. Enable and Disable Times Note 1 )Waveform1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control Note 2) All input pulses are supplied by generators having the following characteristics: PRR ⊆ 10Mhz, Zo = 50Ω , tr ⊆ 2ns, tf ⊆ 2ns. Note 3) The output are measured one at a time with one transition per measurement. Note 4) tPLZ and tPHZ are the same as tdis. Note 5) tPZL and tPZH are the same as ten . Note 6) tPLH and tPHL are the same as tpd. 5 Copyright ©1999, Hyundai Electronics Industries Co., Ltd. ELECTRONICS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS Parameter Measurement (Vcc=2.7V and 3.3V±0.3V) HG74ALVC16835C Jan 1999 From Output Under Test 500 S1 6V Open GND Test tpd tPLZ / tPZL tPHZ /tPZH S1 Open 6V GND CL = 50pF (see note) 500 Figure 6. Load Circuit Note) CL includes probe and jig capacitance Voltage Waveforms Timing Input tsu Data 1.5V Input 2.7V 1.5V 0V th Input 2.7V 1.5V 0V 1.5V 1.5V 0V tw 2.7V Figure 7. Set up and Hold Times Figure 8. Pulse Duration 2.7V Input tPLH 1.5V 1.5V 0V tPHL VOH Output 1.5V 1.5V VOL Figure 9. Propagation Delay times 6 Copyright ©1999, Hyundai Electronics Industries Co., Ltd. ELECTRONICS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS HG74ALVC16835C Jan 1999 Output Control (Low-level enabling) 1.5V 2.7V 1.5V 0V tPLZ 3V 1.5V VCC + 0.3V VOL tPHZ VOH 1.5V VOH - 0.3V 0V Output Waveform 1 S1 at 6V (See Note1) tPZL tPZH Output Waveform 2 S1 at GND (See Note1) Figure 10. Enable and Disable Times Note 1 ) Waveform1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control Note 2) All input pulses are supplied by generators having the following characteristics : PRR ⊆ 10MHz, Zo = 50Ω, tr ⊆ 2.5ns, tf ⊆ 2.5ns. Note 3) The output are measured one at a time with one transition per measurement. Note 4) tPLZ and tPHZ are the same as tdis. Note 5) tPZL and tPZH are the same as ten . Note 6) tPLH and tPHL are the same as tpd. 7 Copyright ©1999, Hyundai Electronics Industries Co., Ltd. ELECTRONICS