HMP351S6AFR8C-Y5

200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 2Gb version A This Hynix unbuffered Small Outline Dual In-Line Memory Module (DIMM) series consists of 2Gb version A DDR2 SDRAMs in Fine Ball Grid Array (FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 2Gb version A based Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC standard Double Data Rate 2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply • All inputs and outputs are compatible with SSTL_1.8 interface • • • Posted CAS Programmable CAS Latency 3,4,5, and 6 OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) • Fully differential clock operations (CK & CK) • • • • • • • Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60 ball(x4/8) 67.60 x 30.00 mm form factor RoHS compliant & Halogen-free * This product is in compliance with the directive pertaining of RoHS. ORDERING INFORMATION Part Name HMP351S6AFR8C-Y5/S5/S6 Density 4GB Organization 512Mx64 # of DRAMs 16 # of ranks 2 Materials Halogen free This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Dec. 2009 1 1200pin Unbuffered DDR2 SDRAM SO-DIMMs SPEED GRADE & KEY PARAMETERS Y5 (DDR2-667) Speed@CL3 Speed@CL4 Speed@CL5 Speed@CL6 CL-tRCD-tRP 400 533 667 5-5-5 S6 (DDR2-800) 533 667 800 6-6-6 S5 (DDR2-800) 400 533 800 5-5-5 Unit Mbps Mbps Mbps Mbps tCK ADDRESS TABLE Density Organization Ranks 4GB 512M x 64 2 SDRAMs 512Mb x 4 # of DRAMs 16 # of row/bank/column Address 14(A0~A13)/3(BA0~BA2)/10(A0~A9) Refresh Method 8K / 64ms Rev. 1.0 / Dec. 2009 2 1200pin Unbuffered DDR2 SDRAM SO-DIMMs PIN DESCRIPTION Symbol Type Polarity Cross Point Pin Description The system clock inputs. All address an commands lines are sampled on the cross point CK[1:0], CK[1:0] Input of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. CKE[1:0] Input Active High Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR2 SDRAM command decoder when low and disables the S[1:0] Input Active Low Active Low command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1 RAS, CAS, WE BA[2:0] ODT[1:0] Input Input Input Active High When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS and WE define the operation to be executed by the SDRAM. Selects which DDR2 SDRAM internal bank of four or eight is activated. Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2 SDRAM mode register. During a Bank Activate command cycle, difines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to A[9:0], A10/AP, A[15:11] Input invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. DQ[63:0] DM[7:0] In/Out Input Active High Data Input/Output pins. The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. The data strobe, associated with one data byte, sourced whit data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. DQS[7:0], DQS[7:0] In/Out Cross point In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed approriately. VDD, VDDSPD,VSS SDA SCL SA[1:0] TEST Supply In/Out Input Input In/Out Power supplies for core, I/O, Serial Presense Detect, and ground for the module. This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister must be connected to VDD to act as a pull up. This signals is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to VDD to act as a pull up. Address pins used to select the Serial Presence Detect base address. The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules (SODIMMs). Rev. 1.0 / Dec. 2009 3 1200pin Unbuffered DDR2 SDRAM SO-DIMMs PIN ASSIGNMENT Pin NO. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Front Side VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2 Pin NO. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Back Side VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0 VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC Pin NO. 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 Front Side DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 Pin NO. 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 Back Side DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3 DQS3 VSS DQ30 DQ31 VSS VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 Pin NO. 101 103 105 107 109 111 113 115 117 121 123 125 127 131 133 135 137 139 141 143 145 147 149 Front Side A1 VDD A10/AP BA0 WE VDD CAS NC/S1 VDD VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS Pin NO. 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 Back Side A0 VDD BA1 RAS S0 VDD ODT0 A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5 DQS5 VSS Pin NO. 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 Front Side DQ42 DQ43 VSS DQ48 DQ49 VSS VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD Pin NO. 152 154 156 158 160 162 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 Back Side DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7 DQS7 VSS DQ62 DQ63 VSS SA0 SA1 NC,TEST 164 119 NC/ODT1 NC/CKE1 129 Pin Location Pin #40 Pin #2 Pin #42 Pin #200 Front Side Pin #1 Pin #39 Pin #41 Pin #99 Back Side Rev. 1.0 / Dec. 2009 4 1200pin Unbuffered DDR2 SDRAM SO-DIMMs FUNCTIONAL BLOCK DIAGRAM 4GB(512Mbx64): HMP351S6AFR8C 3Ω +/-5% CKE1 ODT1 /S1 CKE0 ODT0 /S0 DQS0 /DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 /CS0 ODT0 CKE0 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS1 ODT1 CKE1 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS4 /DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 /CS0 ODT0 CKE0 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS1 ODT1 CKE1 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D0 D8 D1 D9 DQS1 /DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /CS0 ODT0 CKE0 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 /CS1 ODT1 CKE1 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS5 /DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D10 /CS0 ODT0 CKE0 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 /CS1 ODT1 CKE1 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D11 DQS2 /DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 /CS0 ODT0 CKE0 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D4 /CS1 ODT1 CKE1 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS6 /DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D12 /CS0 ODT0 CKE0 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D5 /CS1 ODT1 CKE1 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D13 DQS3 /DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 /CS0 ODT0 CKE0 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 /CS1 ODT1 CKE1 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS7 /DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D14 /CS0 ODT0 CKE0 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D7 /CS1 ODT1 CKE1 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D15 10Ω +/-5% BA0-BA2 A0-AN /RAS /CAS /WE SDRAMS D0-15 SDRAMS D0-15 SDRAMS D0-15 SDRAMS D0-15 SDRAMS D0-15 SCL SA0 SA1 SCL A0 A1 A2 Serial PD WP SDA SDA VDDSPD VREF Serial PD SDRAMS D0-D15 SDRAMS D0-D15, VDD and VDDQ SDRAMS D0-D15, SPD CK0 /CK0 5.6pF 8 loads VDD VSS CK1 5.6pF /CK1 8 loads Note: 1.Resistor values are 22 ohm +/-5% unless other wide stated. Rev. 1.0 / Dec. 2009 5 1200pin Unbuffered DDR2 SDRAM SO-DIMMs ABSOLUTE MAXIMUM RATINGS Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on VDDL pin relative to Vss Voltage on any pin relative to Vss Symbol VDD VDDQ VDDL VIN, VOUT Value - 1.0 V ~ 2.3 V - 0.5 V ~ 2.3 V -0.5V ~ 2.3 V - 0.5 V ~ 2.3 V Unit V V V V Note 1 1 1 1 Operating Conditions and Environmental Parameters Parameter DIMM Operating temperature (ambient) Storage Temperature Storage Humidity (without condensation) DIMM Barometric Pressure (operating & storage) DRAM Component Case Temperature Range Notes: 1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating con ditions for extended periods may affect reliability. 2. Up to 9850 ft. 3. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2. Symbol TOPR TSTG HSTG PBAR TCASE Rating 0 ~ +65 -50 ~ +100 5 to 95 105 to 69 0 ~+95 Units oC oC Notes 1 1 2 3 % K Pascal oC DC OPERATING CONDITIONS Symbol VDD VDDL VDDQ VREF VTT VDDSPD Parameter Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage EEPROM Supply Voltage (SSTL_1.8) Rating Min. 1.7 1.7 1.7 0.49*VDDQ VREF-0.04 1.8 Typ. 1.8 1.8 1.8 0.50*VDDQ VREF Max. 1.9 1.9 1.9 0.51*VDDQ VREF+0.04 3.3 Units V V V mV V V Notes 1 1,2 1,2 3,4 5 Note: 1. Min. Typ. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option. 2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD. 3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc). 5. VTT of transmitting device must track VREF of receiving device. Rev. 1.0 / Dec. 2009 6 1200pin Unbuffered DDR2 SDRAM SO-DIMMs INPUT DC LOGIC LEVEL Parameter dc Input logic HIGH dc Input logic LOW Symbol VIH(DC) VIL(DC) Min VREF + 0.125 -0.30 Max VDDQ + 0.3 VREF - 0.125 Unit V V Note INPUT AC LOGIC LEVEL Parameter AC Input logic HIGH AC Input logic LOW Symbol Min DDR2 667/800 Max Unit VREF - 0.200 V V VIH(AC) VIL(AC) VREF + 0.200 - AC INPUT TEST CONDITIONS Symbol VREF VSWING(MAX) SLEW Notes: 1. 2. 3. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure. AC timings are referenced with input waveforms switching from VIL (ac) to VIH (ac) on the positive transitions and VIH (ac) to VIL (ac) on the negative transitions. Condition Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate Value 0.5 * VDDQ 1.0 1.0 Units V V V/ns Notes 1 1 2, 3 VSWING(MAX) VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS delta TF Falling Slew = VREF - VIL(ac) max delta TF delta TR Rising Slew = VIH(ac)min - VREF delta TR < Figure: AC Input Test Signal Waveform> Rev. 1.0 / Dec. 2009 7 1200pin Unbuffered DDR2 SDRAM SO-DIMMs Differential Input AC logic Level Symbol VID (ac) VIX (ac) Parameter ac differential input voltage ac differential cross point voltage Min. 0.5 0.5 * VDDQ - 0.175 Max. VDDQ + 0.6 0.5 * VDDQ + 0.175 Units V V Note 1 2 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - VIL(DC). VTR VID VCP VSSQ < Differential signal levels > Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross. Crossing point VIX or VOX DIFFERENTIAL AC OUTPUT PARAMETERS Symbol VOX (ac) Parameter ac differential cross point voltage Min. 0.5 * VDDQ - 0.125 Max. 0.5 * VDDQ + 0.125 Units V Note 1 Notes: 1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross. Rev. 1.0 / Dec. 2009 8 1200pin Unbuffered DDR2 SDRAM SO-DIMMs OUTPUT BUFFER LEVELS OUTPUT AC TEST CONDITIONS Symbol VOTR Notes: 1. The VDDQ of the device under test is referenced. Parameter Output Timing Measurement Reference Level SSTL_18 0.5 * VDDQ Units V Notes 1 OUTPUT DC CURRENT DRIVE Symbol IOH(dc) IOL(dc) Parameter Output Minimum Source DC Current Output Minimum Sink DC Current SSTl_18 - 13.4 13.4 Units mA mA Notes 1, 3, 4 2, 3, 4 Notes: 1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define a convenient driver current for measurement. Rev. 1.0 / Dec. 2009 9 1200pin Unbuffered DDR2 SDRAM SO-DIMMs PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25°…) 4GB: HMP351S6AFR8C Pin CK, CK CKE, ODT,CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Notes: 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only. Symbol CCK CI1 CI2 CIO Min 17 24 31 7 Max 29 38 56 12 Unit pF pF pF pF Rev. 1.0 / Dec. 2009 10 1200pin Unbuffered DDR2 SDRAM SO-DIMMs IDD SPECIFICATIONS (TCASE: 0 to 95oC) 4GB, 512M x 64 SO-DIMM: HMP351S6AFR8C Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4W IDD4R IDD5B IDD6 IDD6(L) IDD7 Y5 (DDR2 667@CL5) 1120 1200 192 720 800 560 288 1120 2000 1880 2160 240 128 2640 S5/S6 (DDR2 800@CL5&6) 1200 1280 192 800 880 560 288 1280 2360 2200 2280 240 128 2880 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1 1 Note Rev. 1.0 / Dec. 2009 11 1200pin Unbuffered DDR2 SDRAM SO-DIMMs IDD Measurement Conditions Symbol IDD0 Conditions Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin (IDD);CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin (IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Fast PDN Exit MRS(12) = 0 Other control and address bus inputs are STABLE; Data bus inputs are FLOATSlow PDN Exit MRS(12) = 1 ING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax (IDD), tRP =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax (IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax (IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85 ℃ max. Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions Units mA IDD1 mA mA mA mA mA mA mA IDD2P IDD2Q IDD2N IDD3P IDD3N IDD4W mA IDD4R mA IDD5B mA IDD6 mA IDD7 mA Notes: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as Vin £ VILAC (max) HIGH is defined as Vin Š VIHAC (min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. Rev. 1.0 / Dec. 2009 12 1200pin Unbuffered DDR2 SDRAM SO-DIMMs Electrical Characteristics & AC Timings Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin Speed Bin (CL-tRCD-tRP) Parameter CAS Latency tRCD tRP tRAS tRC DDR2-800 (S5) 5-5-5 min 5 12.5 12.5 45 57.5 DDR2-800 (S6) 6-6-6 min 6 15 15 45 60 DDR2-667 (Y5) 5-5-5 min 5 15 15 45 60 tCK ns ns ns ns Unit Rev. 1.0 / Dec. 2009 13 1200pin Unbuffered DDR2 SDRAM SO-DIMMs AC Timing Parameters by Speed Grade DDR2-667 min tAC tDQSCK tCH tCL tHP tCK tDS tDH tIPW tDIPW tHZ tLZ(DQS) tLZ(DQ) tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPRE tWPST tIS tIH tRPRE tRPST tRAS tRRD tRRD tFAW tFAW -450 -400 0.45 0.45 min(tCL, tCH) 3000 100 175 0.6 0.35 tAC min 2*tAC min tHP - tQHS -0.25 0.35 0.35 0.2 0.2 2 0.35 0.4 200 275 0.9 0.4 45 7.5 10 37.5 50 max +450 +400 0.55 0.55 8000 tAC max tAC max tAC max 240 340 +0.25 0.6 1.1 0.6 70000 tAC min 2*tAC min tHP - tQHS -0.25 0.35 0.35 0.2 0.2 2 0.35 0.4 175 250 0.9 0.4 45 7.5 10 35 45 DDR2-800 min -400 -350 0.48 0.48 min(tCL, tCH) 2500 50 125 0.6 0.35 max +400 +350 0.52 0.52 8000 tAC max tAC max tAC max 240 300 +0.25 0.6 1.1 0.6 70000 ps ps tCK tCK ps ps ps ps tCK tCK ps ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK tCK ps ps tCK tCK ns ns ns ns ns 1 1 Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input setup time (differential strobe) Symbol Unit Note DQ and DM input hold time (differential strobe) Control & Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK/CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS First DQS latching transition to associated clock edge DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write preamble Write postamble Address and control input setup time Address and control input hold time Read preamble Read postamble Activate to precharge command Row Active to Row Active Delay for 1KB page size Row Active to Row Active Delay for 2KB page size Four Active Window for 1KB page size products Four Active Window for 2KB page size products Rev. 1.0 / Dec. 2009 14 1200pin Unbuffered DDR2 SDRAM SO-DIMMs - continued Parameter CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any nonread command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on (Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW Average periodic Refresh Interval Symbol tCCD tWR tDAL tWTR tRTP tXSNR tXSRD tXP tXARD tXARDS tCKE tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD tOIT tDelay tREFI tREFI DDR2-667 min 2 15 WR+tRP 7.5 7.5 tRFC + 10 200 2 2 7 - AL 3 2 tAC (min) tAC(min)+2 2.5 tAC (min) tAC(min)+2 3 8 0 tIS + tCK + tIH 12 7.8 3.9 2 tAC(max)+0.7 2tCK+ tAC(max)+1 2.5 tAC (max)+ 0.6 2.5tCK+ tAC(max)+1 max 2 15 DDR2-800 min max 2 tAC(max)+0.7 2tCK+ tAC(max)+1 2.5 tAC (max)+ 0.6 2.5tCK+ tAC(max)+1 12 7.8 3.9 Unit Note tCK ns tCK ns ns ns tCK tCK tCK tCK tCK tCK ns ns tCK ns ns tCK tCK ns ns us us 2 3 WR+tRP 7.5 7.5 tRFC + 10 200 2 2 8 - AL 3 2 tAC (min) tAC(min)+2 2.5 tAC (min) tAC(min)+2 3 8 0 tIS + tCK + tIH - Notes: 1. For details and notes, please refer to the relevant Hynix component datasheet(HY5PS1G8(16)31CFP). 2. 0°C ≤ TCASE ≤ 85°C 3. 85°C ＜ TCASE ≤ 95°C Rev. 1.0 / Dec. 2009 15 1200pin Unbuffered DDR2 SDRAM SO-DIMMs PACKAGE OUTLINE 512Mx64 - HMP351S6AFR8C Front 67.60 2.00 Min 4.00 ± 0.10 30.00 PIN 1 2.15 11.40 6.00 1.80 ± 0.10 4.20 11.40 1.50 ± 0.10 PIN 2 PIN 40 PIN42 PIN 200 Detail B 47.40 PIN 39 Detail B PIN 41 Detail A PIN 199 20.00 Back 47.40 SIDE 3.8MAX 2.45 1.00 ± 0.10 Detail of Contacts A 0.45 ± 0.03 Detail of Contacts B (Front) Detail of Contacts B (Back) 4.20 2.70 ± 0.10 0.20 ± 0.15 1.50 4.0 ± 0.10 0.60 2.55 1.0 ± 0.05 4.20 2.40 ± 0.10 1.80 Note: 1. All dimensions are in millimeters. 2. All outline dimensions and tolerances follow the JEDEC standard. 3. ± 0.13 tolerance on all dimensions unless otherwise stated. Rev. 1.0 / Dec. 2009 16 1200pin Unbuffered DDR2 SDRAM SO-DIMMs REVISION HISTORY Revision 0.1 0.2 0.3 Initial data sheet released Added pin capacitance Updated AC Timing Parameters by Speed Grade History Date Jan. 2009 Jul. 2009 Dec. 2009 Rev. 1.0 / Dec. 2009 17