HMP512F7FFP8C-S5

240pin Fully Buffered DDR2 SDRAM DIMMs based on 512 Mb F-ver. This Hynix’s Fully Buffered DIMM is a high-bandwidth & large capacity channel solution that has a narrow host interface. Hynix’s FB-DIMM features novel architecture including the Advanced Memory Buffer that isolates the DDR2 SDRAMs from the channel. This single component located in the front side center of each DIMM, acts as a repeater and buffer for all signals and commands which are exchanged between the host controller and the DDR2 SDRAMs including data in and output. The AMB communicates with the host controller and adjacent DIMMs on a system board using an industry standard Differential Point to Point Link Interface at 1.5V power. The AMB also allows buffering of memory traffic to support large memory capacities. All memory control for the DDR2 SDRAM devices resides in the host, including memory request initiation, timing, refresh, scrubbing, sparing, configuration access and power management. The AMB interface is responsible for handling channel and memory requests to and from the local FBDIMM and for forwarding request to other FBDIMMs on the memory channel. FEATURES • • • • • • • • • • • • • • • • • 240 pin Fully Buffered ECC dual In-Line DDR2 SDRAM Module JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface Built with 512Mb DDR2 SDRAMs in 60ball FBGA Host interface and AMB component industry standard compliant MBIST & IBIST test functions 4 Bank architecture OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination) Fully differential clock operations (CK & CK) Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM 133.35 x 30.35 mm form factor RoHS compliant Full Module Heat Spreader This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 / Feb. 2009 1 1240pin Fully Buffered DDR2 SDRAM DIMMs ORDERING INFORMATION # of # of DRAMs ranks AMB Vendor Version Intel IDT Intel IDT Intel IDT D1 C1 D1 C1 D1 C1 Full Module 30.35mm H. S type Part Name HMP564F7FFP8C-C4/Y5N3 HMP564F7FFP8C-C4/Y5/S5/S6D3 HMP512F7FFP8C-C4/Y5N3 HMP512F7FFP8C-C4/Y5/S5/S6D3 HMP525F7FFP4C-C4/Y5N3 HMP525F7FFP4C-C4/Y5D3 Density Org. Height 512MB 64Mx72 9 1 1GB 128Mx72 18 2 2GB 256Mx72 36 2 Note: *: The 16th and 17th digits stand for AMB vendor and revision. SPEED GRADE & KEY PARAMETERS Speed Grade DDR2 DRAM Speed Grade FB-DIMM Speed Grade FB-DIMM Peak Channel Throughput FB-DIMM Link Transfer Rate C4 DDR2 533 4-4-4 PC2 4200 6.4 3.2 Y5 DDR2 667 5-5-5 PC2 5300 8.0 4.0 S5/6 DDR2 800 5-5-5 / 6-6-6 PC2 6400 9.6 4.8 GByte/S GT/s Unit ADDRESS TABLE Density 512MB 1GB 2GB Org. 64M x 72 128M x 72 256M x 72 Ranks 1 2 2 SDRAMs 64Mbx8 64Mbx8 128Mbx4 # of DRAMs 9 18 36 # of row/bank/column Address 14(A0~A13)/2(BA0~BA1)/10(A0~A9) 14(A0~A13)/2(BA0~BA1)/10(A0~A9) 14(A0~A13)/2(BA0~BA1) 11(A0~A9,A11) Refresh Method 8K / 64ms 8K / 64ms 8K / 64ms Rev 1.2 / Feb. 2009 2 1240pin Fully Buffered DDR2 SDRAM DIMMs Input/Output Functional Description Pin Name SCK SCK PN[13:0] PN[13:0] PS[9:0] PS[9:0] SN[13:0] SN[13:0] SS[9:0] SS[9:0] SCL SDA SA[2:0] VID[1:0] RESET RFU VCC VDD VTT VDDSPD VSS type Input Input Output Output Input Input Output Output Input Input Input Input / Output Input Input Input Supply Supply Supply Supply Supply Polarity Positive Negative Positive Negative Positive Negative Positive Negative Positive Negative Active Low +1.5V +1.8V +0.9V +3.3V System clock input System clock input Primary Northbound Data Primary Northbound Data Primary Southbound Data Primary Southbound Data Secondary Northbound Data Secondary Northbound Data Secondary Southbound Data Secondary Southbound Data Serial Presence Detect (SPD) Clock Input SPD Data Input / Output SPD Address inputs, also used to select the DIMM number in the AMB Voltage ID: These pins must be unconnected for DDR2-based Fully buffered DIMMs AMB reset signal Reserved for Future Use AMB Core Power and AMB channel Interface Power(1.5volt) DRAM Power and AMB DRAM I/O Power DRAM Address/Command/Clock Termination Power(VDD/2) SPD Power Ground The DNU/M_Test pin provides an external connection on R/Cs A-D for testing the margin of Vref which is produced by a voltage divider on the module. It is not intended to be used in normal system operation and must not be connected(DNU) in a system. This test pin may have other features on future card designs and if it does, will be included in this specification at that time. Total Function Description Count 1 1 14 14 10 10 14 14 10 10 1 1 3 2 1 16 8 24 4 1 80 1 DNU/ M_Test - / Analog - / 0.9V 240 Rev 1.2 / Feb. 2009 3 1240pin Fully Buffered DDR2 SDRAM DIMMs PIN ASSIGNMENT Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name VDD VDD VDD VSS VDD VDD VDD VSS VCC VCC VSS VTT VCC VSS VTT VID1 RESET VSS RFU** RFU** VSS PN0 PN0 VSS PN1 PN1 VSS PN2 PN2 VSS PN3 PN3 VSS PN4 PN4 VSS PN5 PN5 VSS PN13 69 70 71 72 73 74 75 76 77 78 79 80 Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Key VSS PS0 PS0 VSS PS1 PS1 VSS PS2 PS2 VSS PS3 PS3 Name PN13 VSS VSS RFU* RFU* VSS VSS PN12 PN12 VSS PN6 PN6 VSS PN7 PN7 VSS PN8 PN8 VSS PN9 PN9 VSS PN10 PN10 VSS PN11 PN11 VSS Pin 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Name VSS PS4 PS4 VSS VSS RFU* RFU* VSS VSS PS9 PS9 VSS PS5 PS5 VSS PS6 PS6 VSS PS7 PS7 VSS PS8 PS8 VSS RFU** RFU** VSS VDD VDD VSS VDD VDD VDD VSS VDD VDD VTT SA2 SDA SCL Pin 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Name VDD VDD VDD VSS VDD VDD VDD VSS VCC VCC VSS VCC VCC VSS VTT VID0 DNU/M_Test VSS RFU** RFU** VSS SN0 SN0 VSS SN1 SN1 VSS SN2 SN2 VSS SN3 SN3 VSS SN4 SN4 VSS SN5 SN5 VSS SN13 189 190 191 192 193 194 195 196 197 198 199 200 NC= No Connect, RFU= Reserved for Future Use. Pin 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 Key VSS SS0 SS0 VSS SS1 SS1 VSS SS2 SS2 VSS SS3 SS3 Name SN13 VSS VSS RFU* RFU* VSS VSS SN12 SN12 VSS SN6 SN6 VSS SN7 SN7 VSS SN8 SN8 VSS SN9 SN9 VSS SN10 SN10 VSS SN11 SN11 VSS Pin 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Name VSS SS4 SS4 VSS VSS RFU* RFU* VSS VSS SS9 SS9 VSS SS5 SS5 VSS SS6 SS6 VSS SS7 SS7 VSS SS8 SS8 VSS RFU* RFU* VSS SCK SCK VSS VDD VDD VDD VSS VDD VDD VTT VDDSPD SA0 SA1 Note: *: These pin positions are reserved for forwarded clocks to be used in future module implementations **: These pin positions are reserved for future architecture flexibility 1) The following signals are CRC bits and thus appear out of the normal sequence: PN12/ PN12, SN12 / SN12, PN13 / PN13, SN13 / SN13,PS9 / PS9, SS9 / SS9 Rev 1.2 / Feb. 2009 4 1240pin Fully Buffered DDR2 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 512MB(64Mbx72) ECC FB-DIMM /S0 DQS0 /DQS0 DQS9 DM NU /CS RDQS /RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 DQS /DQS DQS4 /DQS4 DQS13 DM NU /CS RDQS /RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 DQS /DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 /DQS1 DQS10 D0 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 /DQS5 DQS14 D4 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 /DQS2 DQS11 DM NU /CS RDQS /RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 DQS /DQS D1 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 /DQS6 DQS15 DM NU /CS RDQS /RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 DQS /DQS D5 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 /DQS3 DQS12 DM NU /CS RDQS /RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 DQS /DQS D2 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 /DQS7 DQS16 DM NU /CS RDQS /RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 DQS /DQS D6 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM NU /CS RDQS /RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 DQS /DQS D3 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 V TT DQS8 /DQS8 DQS17 DM NU /CS RDQS /RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 DQS /DQS D7 All address/command/control/clock CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM NU /CS RDQS /RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 DQS /DQS D8 Serial PD SCL SCL WP A0 U0 A1 SDA A2 SA2 SDA VTT VCC VDD SPD VDD VREF VSS Terminators AMB Serial PD,AMB DO-D8, AMB DO-D8 DO-D8,SPD, AMB PN0-PN13 /PN0-/PN13 PS0-PS9 /PS0-/PS9 DQ0-DQ63 CB0-CB7 DQS0-DQS17 /DQS0-/DQS8 SCL SDA SA0-SA2 /RESET SCK/ /SCK A M B SN0-SN13 /SN0-/SN13 SS0-SS9 /SS0-/SS9 /S0-/CS(all SDRAMs) CKE0 -> CKE ODT -> ODT BA0-BA2 A0-A15 /RAS /CAS /WE CK/ /CK SA0 SA1 Notes : 1. DQ-to-I/O wiring may be changed within a byte. 2. There are two physical copies of each address/command/control/clock. Rev 1.2 / Feb. 2009 5 1240pin Fully Buffered DDR2 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 1GB(128Mbx72) ECC FB-DIMM /S 1 /S 0 DQS /D Q S DQS9 DM N U /C S R D Q S /R D Q S I/O 0 I/O 1 I/O 2 I/O I/ O I/O I/O I/O 3 4 5 6 7 DQS5 /D Q S 5 D Q S14 D Q S /D Q S DM N U /C S R D Q S /R D Q S I/ O 0 I/ O 1 I/ O 2 I/ O I/O I/ O I/ O I/ O 3 4 5 6 7 D Q S /D Q S DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 /D Q S 1 D Q S 10 D0 D9 D Q 40 D Q 41 D Q 42 D Q 43 D Q 44 D Q 45 D Q 46 DQ 47 DQ S6 /D Q S 6 DQ S15 DM N U /C S R D Q S /R D Q S I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 D Q S /D Q S D5 DM N U /C S R D Q S /R D Q S I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 D Q S /D Q S D 14 DQ8 DQ 9 D Q 10 D Q 11 D Q 12 D Q 13 D Q 14 DQ 15 DQS2 /D Q S 2 DQ S11 DM N U /C S R D Q S /R D Q S I/O 0 I/O 1 I/O 2 I/O I/ O I/O I/O I/O 3 4 5 6 7 D Q S /D Q S D1 DM N U /C S R D Q S /R D Q S I/ O 0 I/ O 1 I/ O 2 I/ O I/O I/ O I/ O I/ O 3 4 5 6 7 D Q S /D Q S D1 0 z DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 D Q 55 DQS7 /D Q S 7 DQ S16 DM N U /C S R D Q S /R D Q S I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 D Q S /D Q S D6 DM N U /C S R D Q S /R D Q S I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 D Q S /D Q S D 15 D Q16 D Q17 D Q18 D Q19 D Q20 D Q21 D Q22 D Q 23 DQS3 /D Q S 3 D Q S12 DM N U /C S R D Q S /R D Q S I/ O 0 I/ O 1 I/ O 2 I/ O I/O I/ O I/ O I/ O 3 4 5 6 7 D Q S /D Q S D2 DM N U /C S R D Q S /R D Q S I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 D Q S /D Q S D1 1 D Q 56 D Q 57 D Q 58 D Q 59 D Q 60 D Q 61 D Q 62 D Q 63 DQS8 /D Q S 8 D Q S17 DM N U /C S R D Q S /R D Q S I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 D Q S /D Q S D7 DM N U /C S R D Q S /R D Q S I/ O 0 I/ O 1 I/ O 2 I/ O I/O I/ O I/ O I/ O 3 4 5 6 7 D Q S /D Q S D 16 D Q24 D Q25 D Q26 D Q27 D Q28 D Q29 D Q30 D Q 31 DQS4 /D Q S 4 D Q S 13 DM N U /C S R D Q S /R D Q S I/ O 0 I/ O 1 I/ O 2 I/ O I/O I/ O I/ O I/ O 3 4 5 6 7 D Q S /D Q S D3 DM N U /C S R D Q S /R D Q S I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 D Q S /D Q S D1 2 C B0 C B1 C B2 C B3 C B4 C B5 C B6 C B7 DM N U /C S R D Q S /R D Q S I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 D Q S /D Q S D8 DM N U /C S R D Q S /R D Q S I/ O 0 I/ O 1 I/ O 2 I/ O I/O I/ O I/ O I/ O 3 4 5 6 7 D Q S /D Q S D 17 D Q32 D Q33 D Q34 D Q35 D Q36 D Q37 D Q38 DQ 39 DM N U /C S R D Q S /R D Q S I/O 0 I/O 1 I/O 2 I/O I/ O I/O I/O I/O 3 4 5 6 7 D Q S /D Q S D4 DM N U /C S R D Q S /R D Q S I/ O 0 I/ O 1 I/ O 2 I/ O I/O I/ O I/ O I/ O 3 4 5 6 7 D Q S /D Q S D 13 A ll a d d re s s/ c o m m a n d /c o n tro l/c lo c k V TT P N 0 -P N 1 3 /P N 0 -/P N 1 3 P S 0 -P S 9 /P S 0 -/P S 9 T e rm in a to rs AMB S e ria l P D ,A M B D O -D 1 7 , A M B D O -D 1 7 D O -D 1 7 ,S P D , A M B D Q 0 -D Q 6 3 C B 0 -C B 7 D Q S 0 -D Q S 1 7 /D Q S 0 -/D Q S 8 SCL SDA S A 0 -S A 2 /R ES ET S C K , /S C K VTT S e ria l P D SCL SCL WP A0 SA0 U0 A1 SA1 SDA A2 SA2 SDA VCC VDD SPD VDD VREF VSS A M B S N 0 -S N 1 3 /S N 0 -/S N 1 3 S S 0 -S S 9 /S S 0 -/S S 9 /S 0 -/ C S (D 0 -D 8 ) C K E 0 -> C K E (D 0 -D 8 ) /S 1 -/ C S (D 9 -D 1 7 ) C K E 1 -> C K E (D 9 -D 1 7 ) O D T -> O D T (a ll S D R A M s ) B A 0 -B A 2 (a ll S D R A M s ) A 0 -A 1 5 (a ll S D R A M s ) /R A S (a ll S D R A M s ) /C A S (a ll S D R A M s ) /W E (a ll S D R A M s ) C K , /C K (a ll S D R A M s ) Notes : 1. DQ-to-I/O wiring may be changed within a byte. 2. There are two physical copies of each address/command/control/clock. Rev 1.2 / Feb. 2009 6 1240pin Fully Buffered DDR2 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 2GB(256Mbx72) ECC FB-DIMM VSS /S1 /S0 /DQS0 DQS0 DQ0 DQ1 DQ2 DQ3 /DQS1 DQS1 DQ 8 DQ 9 DQ 10 DQ 11 /DQS2 DQS2 DQ 16 DQ 17 DQ 18 DQ 19 /DQS3 DQS3 DQ 24 DQ 25 DQ 26 DQ27 /DQS4 DQS4 DQ 32 DQ 33 DQ 34 DQ 35 /DQS5 DQS5 DQ 40 DQ 41 DQ 42 DQ43 /DQS6 DQS6 DQ 48 DQ 49 DQ 50 DQ51 /DQS7 DQS7 DQ 56 DQ 57 DQ 58 DQ59 /DQS8 DQS8 CB0 CB1 CB2 CB3 DQS /DQS /CS I/O 0 I/O 1 D0 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D1 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D2 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D3 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D4 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D5 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D6 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D7 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D8 I/O 2 I/O 3 /DQS9 DQS9 DM DQS /DQS /CS I/O 0 I/O 1 I/O 2 D18 I/O 3 DQS /DQS /CS I/O 0 I/O 1 I/O 2 D19 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D20 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D21 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D22 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D23 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 I/O 2 D24 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D25 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 I/O 2 D26 I/O 3 DM DQ4 DQ5 DQ6 DQ7 /DQS10 DQS10 DQ20 DQ21 DQ22 DQ23 /DQS11 DQS11 DQ36 DQ37 DQ38 DQ39 /DQS12 DQS12 DQ44 DQ45 DQ46 DQ47 /DQS13 DQS13 DQ52 DQ53 DQ54 DQ55 /DQS14 DQS14 DQ60 DQ61 DQ62 DQ63 /DQS15 DQS15 DQ64 DQ65 DQ66 DQ67 /DQS16 DQS16 DQ60 DQ61 DQ62 DQ63 /DQS17 DQS17 CB4 CB5 CB6 CB7 DQS /DQS /CS I/O 0 I/O 1 D9 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D10 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D11 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D12 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D13 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D14 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D15 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D16 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D17 I/O 2 I/O 3 DM DQS /DQS /CS I/O 0 I/O 1 D27 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D28 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D29 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D30 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D31 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D32 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D33 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D34 I/O 2 I/O 3 DQS /DQS /CS I/O 0 I/O 1 D35 I/O 2 I/O 3 DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM All address/command/control/clock Serial PD SCL SCL WP U0 A0 A1 SDA A2 SDA VTT VCC VDD SPD VDD VREF VSS V TT Terminators AMB PN0-PN13 /PN0-/PN13 PS0-PS9 /PS0-/PS9 SA0 SA1 SA2 DQ0-DQ63 Serial PD,AMB CB0-CB7 DQS0-DQS17 DO-D35, AMB /DQS0-/DQS17 DO-D35 DO-D35,SPD, AMB SCL SDA SA0-SA2 /RESET SCK, /SCK A M B SN0-SN13 /SN0-/SN13 SS0-SS9 /SS0-/SS9 /S0-/CS (all SDRAMs) CKE0 -> CKE (all SDRAMs) ODT -> ODT (all SDRAMs) BA0-BA2 (all SDRAMs) A0-A15 (all SDRAMs) /RAS (all SDRAMs) /CAS (all SDRAMs) /W E (all SDRAMs) CK, /CK (all SDRAMs) Notes : 1. DQ-to-I/O wiring may be changed within a byte. 2. There are two physical copies of each address/command/control/clock. Rev 1.2 / Feb. 2009 7 1240pin Fully Buffered DDR2 SDRAM DIMMs Architecture Advanced Memory Buffer Pin Description Pin Name Pin Description FB-DIMM Channel Signals SCK SCK PN[13:0] PN[13:0] PS[9:0] PS[9:0] SN[13:0] SN[13:0] SS[9:0] SS[9:0] FBDRES System Clock Input, positive line System Clock Input, negative line Primary Northbound Data, positive lines Primary Northbound Data, negative lines Primary Southbound Data, positive lines Primary Southbound Data, negative lines Secondary Northbound Data, positive lines Secondary Northbound Data, negative lines Secondary Southbound Data, positive lines Secondary Southbound Data, negative lines To an external precision calibration resistor connected to Vcc DDR2 Interface Signals DQS[8:0] DQS[8:0] DQS[17:9]/DM[8:0] DQS[17:9] DQ[63:0] CB[7:0] A[15:0]A,A[15:0]B BA[2:0]A,BA[2:0]B RASA,RASB CASA,CASB WEA,WEB ODTA,ODTB CKE[1:0]A,CKE[1:0]B CS[1:0]A,CS[1:0]B CLK[3:0] CLK[3:0] DDRC_C14 DDRC_B18 DDRC_C18 DDRC_B12 DDRC_C12 Data Strobes, positive lines Data Strobes, negative lines Data Strobes(x4 DRAM only), positive lines. These signals are driven low to x8 DRAM on writes. Data Strobes(x4 DRAM only), negative lines Data Checkbits Addresses. A10 is part of the pre-charge command Bank Addresses Part of command, with CAS, WE and CS[1:0] Part of command, with RAS, WE and CS[1:0] Part of command, with RAS, WE and CS[1:0] On-die Termination Enable Clock Enable(one per rank) Chip Select(One per rank) CLK[1:0] used on 9 and 18 device DIMMs, CLK[3:0] used on 36 device DIMMs. CLK[3:2] should be output disabled when not in use. Negative lines for CLK[3:0] DDR Compensation: Common return pin for DDRC_B18 and DDRC_C18 DDR Compensation: Resistor connected to common return pin DDRC_C14 DDR Compensation: Resistor connected to common return pin DDRC_C14 DDR Compensation: Resistor connected to VSS DDR Compensation: Resistor connected to VDD Count 99 1 1 14 14 10 10 14 14 10 10 1 175 9 9 9 9 64 8 32 6 2 2 2 2 4 4 4 4 1 1 1 1 1 Rev 1.2 / Feb. 2009 8 1240pin Fully Buffered DDR2 SDRAM DIMMs Advanced Memory Buffer Pin Description Pin Name Pin Description SPD Bus Interface Signals SCL SDA SA{2:0] Serial Presence Detect (SPD) Clock Input SPD Data Input / Output SPD Address Inputs, also used to select the DIMM number in the AMB Miscellaneous Signals PLLTSTO VCCAPLL VSSAPLL TEST_pin# TESTLO_pin# BFUNC RESET NC RFU PLL Clock Observability Output Analog VCC for the PLL. Tied with low pass filter to VCC. Analog VSS for the PLL. Tied to Leave floating on the DIMM Tie to ground on the DIMM2 Tie to ground to set functionality as “buffer on DIMM.” AMB reset signal No connect. Many NC are connected to VDD on the DIMM, to lower the impedance of the VDD power islands. Reserved for Future Use Power/Ground Signals VCC VCCFBD VDD VDDSPD VSS AMB Core Power(1.5 Volt) AMB Channel I/O Power(1.5 Volt) AMB DRAM I/O Power (1.8 Volt) SPD Power (3.3 Volt) Ground Total Count 5 1 1 3 163 1 1 1 6 5 1 1 129 18 213 24 8 24 1 156 655 Note: 1. System Clock Signals SCK and SCK switch at one half the DRAM CK/ CK frequency. 2. TESTLO_AB20 and TESTLO_AC20 should be configured for debug purposes on protype DIMMs: each pin should have a zero ohm resistor pull-down to ground, and an unpopulated resistor pull-up to VCC. These resistors can be replaced on production DIMMs with a direct connection to ground. Rev 1.2 / Feb. 2009 9 1240pin Fully Buffered DDR2 SDRAM DIMMs Pin Assignments for the Advanced Memory Buffer(AMB) (Top View) 655-Ball LFBGA 0.8 mm x 0.8 mm pitch Left Side 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC 1 2 VSS DQ19 DQ21 VSS VDD DQS2 DQS2 VSS DQ20 2 3 VSS DQS3 DQ18 VSS DQ17 DQ23 NC NC NC NC NC NC NC NC NC NC NC VSS VSS VSS PN4 RESET VSS 3 4 DQ26 DQS3 VSS DQ16 DQ29 VSS NC NC NC NC NC NC NC NC NC NC NC SN0 SN1 SN2 VSS PN5 PN5 4 5 DQ12 VSS DQ4 DQ24 VSS DQ31 NC NC NC NC NC NC NC NC NC NC NC SN0 SN1 SN0 VSS PN13 PN13 5 6 VDD 7 8 9 VDD DQ11 DQ9 VSS DQ5 10 DQS1 DQS1 VSS DQ3 DQ1 VSS NC NC NC NC NC NC NC NC NC NC NC RFUa SN12 SN12 VSS PN8 PN8 10 11 DQ10 VSS DQ8 DQS0 VSS DQS0 NC NC NC NC NC NC NC NC NC NC NC RFUa SN6 SN6 VSS PN9 PN9 11 12 VDD DDRC DDRC VSS DQ0 DQ2 BFUNC VSS VDD VSS VCC VSS VCC VSS VCC VSS RFU VCCFBD SN7 SN7 VSS 13 TEST TESTLO VSS DQS8 CB1 VDD RFU VDD VSS VCC VSS VCC VSS VCC VSS VCC VCCFBD VSS SN8 SN8 VSS 14 VDD VDD 15 VDD VSS DQS10 DQ13 VSS DQ15 DQ7 VSS DQ14 DQS10 DQS9 VSS DQ25 DQ27 VSS DQ28 BA1A VSS A0A CASA VSS A2A A11A VSS A15A VCCFBD SN3 SN3 VSS RFUa RFU 6 a VSS DQS9 DQ6 VSS DDRC DQS17 DQS8 VSS CB0 RFU VSS VDD VSS VCC VSS VCC VSS VCC VSS VSS VSS SN9 SN9 VSS VDD CB2 CB3 RFU VDD VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS SN10 SN10 VSS PN11 PN11 15 TESTLO TEST NC NC NC NC NC NC NC NC NC NC NC VSS SN13 SN13 VSS PN7 PN7 9 DQS11 DQS11 DQ22 VSS CLK2 CLK0 ODT0A CS1A A6A VSS A4A PN0 PN1 PN2 PN3 VSS VSS CLK2 CLK0 VSS RFU CS0A VSS A8A A13A PN0 PN1 PN2 PN3 PN4 VSS DQS12 DQS12 DQ30 VSS WEA CKE0A VSS BA0A A1A VSS A9A A14A VSS SN4 SN4 VSS PN12 PN12 7 VSS CKE1A RASA VSS BA2A A10A A3A A5A A7A A12A VCCFBD SN5 SN6 VSS PN6 PN6 8 VSSAPLL VCCAPLL PN10 FBDRES PLLTSTO PN10 12 13 14 NC= No Connect, RFU= Reserved for Future Use. Note: a. These pin positions are reserved for forwarded clocks to be used in future AMB implementations Rev 1.2 / Feb. 2009 10 1240pin Fully Buffered DDR2 SDRAM DIMMs Right Side 16 A B C D E F G H J K L M N P R T U V W Y AA AB AC VDD VDD DQS17 CB6 VSS CB4 TESTLO VSS VDD VSS VCC VSS VCC VSS VCC VSS VSS VCCFBD VSS VSS VSS VSS RFU 16 17 TEST TEST VSS CB7 CB5 VDD RFU VDD VSS VCC VSS VCC VSS VCC VSS VCC VCCFBD VSS SS0 SS0 VSS SN11 SN11 17 18 VDD DDRC DDRC VSS DQS16 DQ62 RFU VSS VDD VSS VCC VSS VCC VSS VCC VSS RFU VCCFBD SS1 SS1 VSS VSS VSS 18 19 DQ52 VSS DQ54 DQS16 VSS DQ60 NC NC NC NC NC NC NC NC NC NC NC VSS SS2 SS2 VSS SCK SCK 19 20 DQS15 DQS15 VSS DQ63 DQ61 VSS NC NC NC NC NC NC NC NC NC NC NC VCCFBD SS3 SS3 VSS TESTLO TESTLO 20 21 VDD DQ53 DQ55 VSS DQ57 TEST NC NC NC NC NC NC NC NC NC NC NC RFU a 22 DQ49 VSS DQ51 DQ59 VSS TEST DQS4 VSS RASB ODT0B VSS CS0B A0B VSS A6B A11B A8B RFUa SS9 SS9 VSS PS1 PS1 22 23 DQS6 DQS6 VSS DQS7 DQ58 VSS DQS4 DQ34 VSS CS1B CASB VSS A2B A4B VSS A9B A15B VSS SS5 SS5 VSS PS2 PS2 23 24 VDD DQ50 DQS7 VSS DQ39 DQ37 VSS DQ32 RFU VSS WEB BA1B VSS A1B A10B VSS A14B A13B SS6 SS6 VSS PS3 PS3 24 25 DQ48 VSS DQ56 DQ36 VSS DQ35 NC NC NC NC NC NC NC NC NC NC SA0 A12B SS7 SS7 VSS PS4 PS4 25 26 DQ38 DQS13 VSS DQ44 DQ33 VSS NC NC NC NC NC NC NC NC NC NC SCL SA2 SS8 SS8 VSS RFUa RFU 26 a 27 VDD DQS13 DQ46 VSS DQ45 DQS5 NC NC NC NC NC NC NC NC NC NC SDA SA1 VSS VSS PS9 VDDSPD VSS 27 28 29 VSS DQS14 VDD DQS14 DQ47 VSS DQ43 DQS5 VSS CLK3 CLK1 VSS CKE0B BA0B VSS A3B A7B PS8 PS7 PS6 PS5 PS9 VSS DQ41 VSS DQ40 DQ42 VSS CLK3 CLK1 VSS BA2B CKE1B VSS A5B PS8 PS7 PS6 PS5 VSS SS4 SS4 VSS PS0 PS0 21 28 29 NC= No Connect, RFU= Reserved for Future Use. Note: a. These pin positions are reserved for forwarded clocks to be used in future AMB implementations Rev 1.2 / Feb. 2009 11 1240pin Fully Buffered DDR2 SDRAM DIMMs Advanced Memory Buffer(AMB) DRAM Interface Specifications Please refer to the AMB Specification for all technical requirements The following specifications for the AMB constitute the subset which is critical for proper operation of the DDR2 SDRAM interface. Note: This list is not complete, more information will follow in later revisions of this specification. Critical AMB Specifications Symbol tSU tH tDVBamb tDVAamb tCVBamb tCVAamb tDQSCKamb CIN Parameter DQ to DQS, DQS setup time (read) DQ to DQS, DQS hold time (read) AMB Data Valid Before DQS AMB Data Valid After DQS C/A/CNTL Valid Before Clock C/A/CNTL Valid After Clock DQS/DQS-to-CK/CK output skew Input Capacitance(DQ/DQS/DQS) Type Input Input Output Output Output Output Output 470 470 1030 890 -240 2.0 240 2.5 VDDQ =1.8V +/-0.1V Min Max 245 245 Units Notes ps ps ps ps ps ps ps pF 1 1 1 1 1 1 1 1 Note 1: The timing numbers are for example only. Design should be based on the latest component specifications Rev 1.2 / Feb. 2009 12 1240pin Fully Buffered DDR2 SDRAM DIMMs Basic Functionality 1. Advanced Memory Buffer Overview The Advanced Memory Buffer reference design complies with the JEDEC FB-DIMM Architecture and Protocol Specification. 2. Advanced Memory Buffer Functionality 2.1 Advanced Memory Buffer • • • • • • • • • • Supports channel initialization procedures as defined in the initialization chapter of the FB-DIMM Architecture and Protocol Specification to align the clocks and the frame boundaries verify channel connectivity and identify AMB DIMM position. Supports the forwarding of southbound and northbound frames, servicing requests directed to DIMM, as defined in the protocol chapter, and merging the return data into the northbound frames. If the AMB resides on the last DIMM in the channel, the AMB initializes northbound frames. Detects errors on the channel and reports them to the host memory controller. Acts as DRAM memory buffer for all read, write and configuration accesses addressed to the DIMM. Provides a read buffer FIFO and a write buffer FIFO. Supports an SMBus protocol interface for access to the AMB configuration registers. Provides logic to support MEMBIST and IBIST Design for Test functions. Provides a register interface for the thermal sensor and status indicator. Functions as a repeater to extend the maximum length of FBD Links. 2.2 Transparent Mode for DRAM Test Support In this mode, the Advanced Memory Buffer will provide lower speed tester access to DRAM pins through the FB-DIMM I/O pins. This allows the tester to send and arbitrary test pattern to the DRAMs. Transparent mode only supports a maximum DRAM frequency equivalent to DDR2 400. Transparent mode functionality: • • • Reconfigure FB-DIMM inputs from differential high speed link receivers to two single ended lower speed receivers(~200 Mhz) These inputs directly control DDR2 Command/Address and input data that is replicated to all DRAMs Used low speed direct drive FB-DIMM outputs to bypass high speed Parallel/Serial circuitry and provide test results back to tester 2.3 DDR2 SDRAM • • • Supports DDR2 at speeds of 533,667 and 800 MT/s Supports 512Mb devices in x4 and x8 configurations 72 bit DDR2 SDRAM memory array Rev 1.2 / Feb. 2009 13 1240pin Fully Buffered DDR2 SDRAM DIMMs 3. Advanced Memory Buffer Block Diagram 10x2 South bound Data in 10x2 South bound Data out Re-Time Data Merge PLL 1x2 Ref Clock Demux I0*12 Reset# Re-synch PISO I0*12 MUX Link init SM & Control & CSRs Reset Control Init patterns IBIST - RX IBIST - RX Command Decoder & CRC Check Failover 4 4 DRAMclock DRAMclock# DRAM Cmd MUX LAI Logic DDR State Controller & CSRs Cmd Out Thermal Sensor 36 Deep Write Data FIFO 29 DRAM Address /CommandCopy1 DRAM Address /CommandCopy2 29 Data Out Core Control & CSRs DDR IO’s 72+18X2 MUX External MEMBIST DDR Calibration & DDR IOBIST/DFX Data CRC Gen & Read FIFO DRAM Address Data/Strobe Data In LAI Controller Sync & Idle Pattern Generator IBIST - TX IBISt - RX NB LAI Buffer MUX SMbus SMbus Controller Failover 14*6*2 PISO Re-synch Re-Time Link init SM & Control & CSRs 14*12 Demux Data Merge Northbound DataOut 14x2 14x2 Northbound DataIn Advanced Memory Buffer Block Diagram Rev 1.2 / Feb. 2009 14 1240pin Fully Buffered DDR2 SDRAM DIMMs 4. Interfaces Below Figure illustrates the AMB and all of its interfaces.They consists of two FB-DIMM links, one DDR2 channel and an SMBus interface. Each FB-DIMM link connects the AMB to a host memory controller or an adjacent FB-DIMM. The DDR2 channel supports direct connection to the DDR2 SDRAMs on a Fully Buffered DIMM. M e m o ry In te rfa ce DDR2 Channel Primary or Host Direction SB FBD In L in k SB FBD O u t L in k AMB NB FBD O u t L in k NB FBD In L in k SMBus A d v a n c e d M e m o ry B u ffe r In te rfa c e s 4.1 FBD High-Speed Differential Point-to-Point Link (at 1.5V) Interfaces The Advanced Memory Buffer supports one FBD channel consisting of two bidirectional link interfaces using high speed differential point-to-point electrical signaling. The southbound input link is 10 lanes wid and carries commands and write data from the host memory controller or the adjacent DIMM in the host direction. The southbound output link forwards this same data to the next FBD. The northbound input link is 13 to 14 lanes wide and carries read return data or status information from the next FB-DIMM in the chain back towards the host. The northbound output link forwards this information back towards the host and multiplexes in any read return data or status information that is generated internally. 4.2 DDR2 Channel The DDR2 channel on the Advanced Memory Buffer supports direct connection to DDR2 SDRAMs. The DDR2 channel supports two ranks of eight banks with 16 row/column request, 64 data signals, and eight check-bit signals. There are two copies of address and command signals to support DIMM routing and electrical requirements. Four transfer bursts are driven on the data and check-bit lines at 800 MHz. Propagation delays between read data/check-bit strobe lanes on a given channel can differ. Each strobe can be calibrated by hardware state machines using write/read trial and error. Hardware aligns the read data and check-bits to a single core clock. The Advanced Memory Buffer provides four copies of the command clock phase references(CLK[3:0]) and write data/check-bit strobes(DQSs) for each DRAM nibble. Rev 1.2 / Feb. 2009 15 Secondary or to optional next FBD 1240pin Fully Buffered DDR2 SDRAM DIMMs 4.3 SMBus Slave Interface The Advanced Memory Buffer supports an SMBus interface to allow system access to configuration registers independent of the FB-DIMM link. The Advanced Memory Buffer will never be a master on the SMBus, only a slave. Serial SMBus data transfer is supported at 100 kHz. SMBus access to the Advanced Memory Buffer may be a requirement to boot and to set link strength, frequency and other parameters needed to insure robust configurations. It is also required for diagnostic support when the link is down. The SMBus address straps located on the DIMM connector are used by the unique ID. 4.4 FBD Channel Latency FB-DIMM channel latency is measured from the time a read request is driven on the FB-DIMM channel pins to the time when the first 16 bytes (2nd chunk) of read completion data is sampled by the memory controller. When not using the Variable Read Latency capability, the latency for a specific DIMM on a channel is always equal to the latency for any other DIMM on that channel. However, the latency for each DIMM in a specific configuration with some number of DIMMs installed. As more DIMMs are added to the channel, additional latency is required to read from each DIMM on the channel. Because the channel is based on the point to point interconnection of buffer components between DIMMs, memory requests are required to travel through N-1 buffers before reaching the Nth buffer. The result is that a 4 DIMM channel configuration will have greater idle read latency compared to a 1DIMM channel configuration.The Variable Read Latency capability can be used to reduce latency for DIMMs closer to the host. The idle latencies listed in this section are representative of what might be achieved in typical AMB designs. Actual implementations with latencies less than the values listed will have higher application performance and vice versa. 4.5 Peak Theoretical Throughput An FB-DIMM channel transfers read completion data on the FBD Northbound data connection. 144 bits of data are transferred for every FBD Northbound data frame. This matches the 18-byte data transfer of an ECC DDR DRAM in a single DRAM command clock. A DRAM burst of 8 from a single channel or a DRAM burst of four from two lock stepped channels provides a total of 72 bytes of data(64 bytes plus 8 bytes ECC) The FBD frame rate matches the DRAM command clock because of the fixed 6:1 ratio of the FBD channel clock to the DRAM command clock. Therefore, the Northbound data connection will exhibit the same peak theoretical throughput as a single DRAM channel. For example, when using DDR2 533 DRAMs, the peak theoretical throughput as a single DRAM channel.For example, when using DDR2 533 DRAMs, the peak theoretical bandwidth of the Northbound data connection is 4.276 GB/sec. Write data is transferred on the FBD Southbound command and data connection, via Command+Wdata frames. 72 bits of data are transferred for every FBD Command+Wdata frame. Two Command+Wdata frames match the 18-byte data transfer of and ECC DDR DRAM in a single DRAM command clock. A DRAM burst of 8 transfers from a single channel, or a burst of 4 from two lock-step channels provides a total of 72 bytes of data(64 bytes plus & bytes ECC) When the FBD frame rate matches the DRAM command clock, the Southbound command and data connection will exhibit one half the peak theoretical throughput of a single DRAM channel. For example, when using DDR2 533 DRAMs, the peak theoretical bandwidth of the Southbound command and data connection is 2.133 GB/sec. The total peak theoretical throughput for a single FBD channel is defined as the sum of the peak theoretical throughput of the Northbound data connection and the Southbound command and data connection. When the FBD frame rate matches the DRAM command clock, this is equal to 1.5 times the peak theoretical throughput of a single DRAM channel. For example, when using DDR2 533 DRAMs, the peak theoretical throughput of a DDR2 533 channel would be 4.267 GB/sec, while the peak theoretical throughput of and FBD -/+533 channel would be 6.4 GB/sec. Rev 1.2 / Feb. 2009 16 1240pin Fully Buffered DDR2 SDRAM DIMMs 5 Hot-add The FB-DIMM channel does not provide a mechanism to automatically detect and report the addition of a new DIMM south of the currently active last DIMM. It is assumed the system will be notified through some means of the addition of one or more new DIMMs so that specific commands can be sent to the host controller to initialize the newly added DIMM(s) and perform a Hot-add Reset to bring them into the channel timing domain. It should be noted that the power to the DIMM socket must be removed before a “hot-add” DIMM is inserted or removed. Applying or removing the power to a DIMM socket is a system platform function. 6 Hot-remove In order to accomplish removal of DIMMs the host must perform a Fast Reset sequence targeted at the last DIMM that will be retained on the channel. The Fast Reset re-establish the appropriate last DIMM so that the Southbound Tx outputs of the last DIMM and the Southbound and Northbound outputs of the DIMMs beyond the last active DIMM are disabled. Once the appropriate outputs are disabled the system can coordinate the procedure to remove power in preparation for physical removal of the DIMM if needed. It should be noted that the power to the DIMM socket must be removed before a “hot-add” DIMM is inserted or removed. Applying or removing the power to a DIMM socket is a system platform function. 7 Hot-replace Hot replace of DIMM is accomplished through combing th Hot-Remove and Hot-Add process. Rev 1.2 / Feb. 2009 17 1240pin Fully Buffered DDR2 SDRAM DIMMs Electrical Characteristics ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pins relative to Vss Voltage on VCC relative to Vss Voltage on VDD relative to Vss Voltage on VTT relative to Vss Storage Temperature range Symbol VIN, VOUT VCC VDD VTT TSTG Value - 0.3 V ~ 1.75 V - 0.3 V ~ 1.75 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V - 55 oC ~ 100 oC Unit V V V V o Note 1 1 1 1 1 C Note: 1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING TEMPERATURE RANGE Parameter AMB Component Case temperature Range DRAM Component Case Temperature Range Symbol TCASE TCASE Rating 0 ~ + 110 0 ~ + 95 Units oC oC Notes 1,2 Note: 1. Within the DRAM component Case Temperature range all DRAM specification will be supported. 2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced from 7.8us of tREFI to 3.9us. Supply Voltage Levels and DC Operating Conditions. Parameter AMB Supply Voltage DRAM Supply Voltage Termination Voltage EEPROM Supply Voltage DC Input Logic High(SPD) DC Input Logic Low(SPD) DC Input Logic High(RESET) DC Input Logic Low(RESET) Leakage Current (RESET) Leakage Current (Link) Symbol VCC VDD VTT VDDSPD VIH(DC) VIL(DC) VIH(DC) VIL(DC) IL IL Min 1.455 1.7 0.48 x VDD 3.0 2.1 1.0 -90 -5 Nom 1.5 1.8 0.50 x VDD 3.3 Max 1.575 1.9 0.52 x VDD 3.6 VDDSPD 0.8 +0.5 +90 +5 Unit V V V V V V V V uA uA 1 1 2 2 2 3 Note Note: 1. Applies for SMB and SPD bus Signals. 2. Applies for AMB CMOS Signal RESET. 3. for all other AMB related DC parameters, please refer to the High Speed Differential Link Interface Specifications Rev 1.2 / Feb. 2009 18 1240pin Fully Buffered DDR2 SDRAM DIMMs Timing Parameters Parameter EI Assertion Pass-Thru Timing EI Deassertion Pass-Thru Timing EI Assertion Duration Bit Lock Interval Frame Lock Interval Symbol tEI Propagad tEID tEI tBitLock tFrameLock 100 119 154 Min Typ Max 4 bit lock Unit clks clks clks frames frames Note 1 1 1 Note: 1. Defined in FB-DIMM Architecture and Protocol Spec. Environmental Parameters Symbol TOPR HOPR TSTG HSTG PBAR PBAR Note: 1. The designer must meet the case temperature specifications for individual module components. 2. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods Parameter Operating temperature Operating humidity(relative) Storage temperature Storage humidity(without condensation) Barometric pressure(operating) Barometric pressure (storage) Rating See Note 10 to 90 -50 to +100 5 to 95 3050 15240 % oC Units Notes 1 2 2 2 2 2 % m m Rev 1.2 / Feb. 2009 19 1240pin Fully Buffered DDR2 SDRAM DIMMs IDD Specification and Conditions IDD Measurement Conditions Symbol Idle_0 Conditions Idle Current, single or last DIMML0 state, idle (0 BW)Primary channel enabled, Secondary Channel Disabled CKE high. Command and address lines stable. DRAM clock active. Idle Current, first DIMML0 state, idle (0 BW)Primary and Secondary channels enabled CKE high. Command and address lines stable. DRAM clock active. Idle Current, DRAM power downL0 state, idle (0 BW)Primary and Secondary channels enabledCKE low. Command and address lines floated. DRAM clock active, ODT and CKE driven low. Active PowerL0 state. 50% DRAM BW, 67% read, 33% write. Primary and Secondary channels enabled. DRAM clock active, CKE high. Active Power, data pass throughL0 state. 50% DRAM BW to downstream DIMM, 67% read, 33% write. Primary and Secondary channels enabled CKE high. Command and address lines stable. DRAM clock active. Channel Standby Average power over 42 frames where the channel enters and exits L0sDRAMs Idle (0 BW). CKE low. Command and address lines floated. Dram clocks active, ODE and CKE driven low. Training Primary and Secondary channels enabled.100% toggle on all channels lanes.DRAMs idle (0 BW).CKE high. Command and address lines stable.DRAM clock active. Idle_1 Idle_2 Active_1 Active_2 L0s Training (for AMB spec, not in SPD) Rev 1.2 / Feb. 2009 20 1240pin Fully Buffered DDR2 SDRAM DIMMs IDD Power Supply Currents Specifications. SAC Timing Parameters by Speed Grade 512MB(HMP564F7FFP8C) 1GB(HMP512F7FFP8C) Intel Y5 2400 630 4.734 3100 630 5.784 3600 1800 8.640 3300 1800 8.190 4000 1800 9.240 2400 630 4.734 3100 630 5.784 3600 1800 8.640 3300 1800 8.190 4000 1800 9.240 IDT IDT S5 3000 630 5.634 3875 630 6.947 4500 2070 10.476 4125 2070 9.914 5000 2070 11.226 2400 1260 5.868 3100 1260 6.918 3600 3600 11.880 3300 3600 11.430 4000 3600 11.480 2GB(HMP525F7FFP4C) Intel Y5 2400 1260 5.868 3100 1260 6.918 3600 3600 11.880 3300 3600 11.430 4000 3600 11.480 mA mA W mA mA W mA mA W mA mA W mA mA W IDT Unit Note1) Power Supply Icc_Idle_0 @1.5V Idd_Idle_0 @1.8V Idle_0 Total Power Icc_Idle_1 @1.5V Idd_Idle_1 @1.8V Idle_1 Total Power Icc_Active_1 @1.5V Idd_Active_1 @1.8V Active_1 Total Power Icc_Active_2 @1.5V Idd_Active_2 @1.8V Active_2 Total Power Icc_Training @1.5V Idd_Training @1.8V Training Total Power Intel Y5 2400 315 4.167 3100 315 5.217 3600 900 7.020 3300 900 6.570 4000 900 7.620 IDT 2400 315 4.167 3100 315 5.217 3600 900 7.020 3300 900 6.570 4000 900 7.620 IDT S5 3000 315 5.067 3875 315 6.380 4500 1035 8.613 4125 1035 8.051 5000 1035 9.363 Note: 1) Assure that Primary channel Drive strength at 100% with De-emphasis at -6.5dB Secondary channel drive strength at 60% with De-emphasis at -3dB when enabled. Address and Data fields are pseudo-random, which provides a 50% toggle rate on DRAM data lines and link lanes when data is being transferred. Assuming 1 activate command and 1 read/write command per BL=4 transferBL=4.10 lanes southbound and 14 lanes northbound are enabled and active (12 lanes NB if non-ECC DIMM). SPD specific assumption:Number of devices on the specific DIMM assumed.Termination of command, address, and control is actual value used on the DIMM. ECC or non-ECC as per the specific DIMM. SPD specifies Delta TAMB power spec specific assumptions: Dual rank x8 ECC DIMM assumed (18 DRAM devices present on DIMM) Modeled with 27 ohm termination for command, address, and clocks, and 47 ohm termination for control. ECC DIMM assumed (72 bit data, 14 lanes northbound). AMB specification specifies current for each rail. Rev 1.2 / Feb. 2009 21 1240pin Fully Buffered DDR2 SDRAM DIMMs Termination Current Internal signals are terminated on the DIMM through resistors to an external power supply VTT = VDD / 2. Modeled with 30 Ohm termination for clocks, 39 ohm for command / address and 47 ohm for control. The VTT power supply must be able to source and sink these currents: VTT Currents table Description Idle Current, DRAM Power Down (Conditions TBD) Active Power, 50% DRAM BW (conditions TBD) Symbol Typ Max 700 700 Unit mA mA ITT1 ITT2 Rev 1.2 / Feb. 2009 22 1240pin Fully Buffered DDR2 SDRAM DIMMs PACKAGE OUTLINE 64Mx72, 512MB Module (1 rank of x8 based DDR2 SDRAMs) HMP564F7FFP8C FRONT VIEW 133.35 ±0.15 4.0 ±0.1 30.35 AMB 67.00 5.00 51.00 BACK VIEW Chekbit FRONT VIEW WITH HEAT SPREADER Side 8.20 max 5.20 max BACK VIEW WITH HEAT SPREADER 3.0 max 1.27±0.10 Note 1: All dimensions are typical millimeter scale unless otherwise stated. Rev 1.2 / Feb. 2009 23 1240pin Fully Buffered DDR2 SDRAM DIMMs PACKAGE OUTLINE 128Mx72, 1GB Module (2 ranks of x8 based DDR2 SDRAMs) HMP512F7FFP8C FRONT VIEW 133.35 ±0.15 4.0 ±0.1 AMB 67.00 51.00 5.00 BACK VIEW Chekbit Chekbit FRONT VIEW WITH HEAT SPREADER 30.35 Side 8.20 max 5.20 max BACK VIEW WITH HEAT SPREADER 3.0 max 1.27±0.10 Note 1: All dimensions are typical millimeter scale unless otherwise stated. Rev 1.2 / Feb. 2009 24 1240pin Fully Buffered DDR2 SDRAM DIMMs PACKAGE OUTLINE 256Mx72, 2GB Module (2 ranks of x4 based DDR2 SDRAMs) HMP525F7FFP4C FRONT VIEW 133.35 ±0.15 4.0 ±0.1 67.00 51.00 5.00 BACK VIEW FRONT VIEW WITH HEAT SPREADER 30.35 Side 8.20 max 5.20 max BACK VIEW WITH HEAT SPREADER 3.0 max 1.27±0.10 Note 1: All dimensions are typical millimeter scale unless otherwise stated. Rev 1.2 / Feb. 2009 25 1240pin Fully Buffered DDR2 SDRAM DIMMs REVISION HISTORY Revision 1.0 1.1 1.2 First Version Release Orddering Info. table revised IDD Power spec added History Date July. 2008 Sep. 2008 Feb. 2009 Remark Rev 1.2 / Feb. 2009 26