HMT112S6AFP6C-S5

204pin DDR3 SDRAM SODIMMs DDR3 SDRAM Unbuffered SODIMMs Based on 1Gb A version HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C ** Contents are subject to change without prior notice. Rev. 0.2 / Dec. 2008 1 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Revision History Revision No. 0.01 0.02 0.03 0.1 0.2 History Initial draft Added IDD, corrected typos Halogen-free added Initial Specification Release Added outline: DIMMs with thermal sensor. Corrected typo on package ball feature. Draft Date Sep. 2007 Mar. 2008 May. 2008 May 2008 Dec. 2008 Remark preliminary preliminary preliminary Rev. 0.2 / Dec. 2008 2 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table of Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Speed Grade & Key Parameters 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 512MB, 64Mx64 Module(1Rank of x16) 3.2 1GB, 128Mx64 Module(2Rank of x16) 3.3 2GB, 256Mx64 Module(2Rank of x8) 4. Absolute Maximum Ratings 4.1 Absolute Maximum DC Ratings 4.2 Operating Temperature Range 5. AC & DC Operating Conditions 5.1 Recommended DC Operating Conditions 5.2 DC & AC Logic Input Levels 5.2.1 For Single-ended Signals 5.2.2 For Differential Signals 5.2.3 Differential Input Cross Point 5.3 Slew Rate Definition 5.3.1 For Ended Input Signals 5.3.2 For Differential Input Signals 5.4 DC & AC Output Buffer Levels 5.4.1 Single Ended DC & AC Output Levels 5.4.2 Differential DC & AC Output Levels 5.4.3 Single Ended Output Slew Rate 5.4.4 Differential Ended Output Slew Rate 5.5 Overshoot/Undershoot Specification 5.5.1 Address and Control Overshoot and Undershoot Specifications 5.5.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications 5.6 Input/Output Capacitance & AC Parametrics 5.7 IDD Specifications & Measurement Conditions 6. Electrical Characteristics and AC Timing 6.1 Refresh Parameters by Device Density 6.2 DDR3 Standard speed bins and AC para 7. DIMM Outline Diagram 7.1 512MB, 64Mx64 Module(1Rank of x16) 7.2 1GB, 128Mx64 Module(2Rank of x16) 7.3 2GB, 256Mx64 Module(2Rank of x8) Rev. 0.2 / Dec. 2008 3 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 1. Description This Hynix unbuffered Small Outline Dual In-Line Memory Module (SODIMM) series consists of 1Gb A version. DDR3 SDRAMs in Fine Ball Grid Array (FBGA) packages on a 204 pin glass-epoxy substrate. This DDR3 Unbuffered SODIMM series based on 1Gb A version provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is suitable for easy interchange and addition. 1.1 Device Features & Ordering Information 1.1.1 Features • VDD=VDDQ=1.5V • VDDSPD=3.0V to 3.6V • Fully differential clock inputs (CK, /CK) operation • Differential Data Strobe (DQS, /DQS) • On chip DLL align DQ, DQS and /DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11) supported • Programmable additive latency 0, CL-1 and CL-2 supported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8 banks • 8K refresh cycles /64ms • DDR3 SDRAM Package: JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16) • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • TDQS (Termination Data Strobe) supported (x8 only) • Write Levelization supported • Auto Self Refresh supported • 8 bit pre-fetch Rev. 0.2 / Dec. 2008 4 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 1.1.2 Ordering Information # of DRAMs 4 4 8 8 16 16 # of ranks 1 1 2 2 2 2 Part Name HMT164S6AFP6C-S6/S5/G8/G7/H9/H8 HMT164S6AFR6C-S6/S5/G8/G7/H9/H8 HMT112S6AFP6C-S6/S5/G8/G7/H9/H8 HMT112S6AFR6C-S6/S5/G8/G7/H9/H8 HMT125S6AFP8C-S6/S5/G8/G7/H9/H8 HMT125S6AFR8C-S6/S5/G8/G7/H9/H8 Density 512MB 512MB 1GB 1GB 2GB 2GB Organization 64Mx64 64Mx64 128Mx64 128Mx64 256Mx64 256Mx64 Materials Lead free Halogen free Lead free Halogen free Lead free Halogen free Two types, with integrated thermal sensor and with no thermal sensor, exist in each configuration. Rev. 0.2 / Dec. 2008 5 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 1.2 Speed Grade & Key Parameters MT/S Grade tCK (min) CAS Latency tRCD (min) tRP (min) tRAS (min) tRC (min) CL-tRCD-tRP 6 15 15 37.5 52.5 6-6-6 DDR3-800 -S6 2.5 5 12.5 12.5 37.5 50 5-5-5 8 15 15 37.5 52.5 8-8-8 -S5 DDR3-1066 -G8 1.875 7 13.125 13.125 37.5 50.625 7-7-7 9 13.5 13.5 36 49.5 9-9-9 -G7 DDR3-1333 Unit -H9 1.5 8 12 12 36 48 8-8-8 -H8 ns tCK ns ns ns ns tCK 1.3 Address Table 512MB Organization Refresh Method Row Address Column Address Bank Address Page Size # of Rank # of Device 64M x 64 8K/64ms A0-A12 A0-A9 BA0-BA2 2KB 1 4 1GB 128M x 64 8K/64ms A0-A12 A0-A9 BA0-BA2 2KB 2 8 2GB 256M x 64 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 2 16 Rev. 0.2 / Dec. 2008 6 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 2. Pin Architecture 2.1 Pin Definition Pin Name CK[1:0] CK[1:0] CKE[1:0] RAS CAS WE S[1:0] A[9:0], A11, A[15:13] A10/AP A12/BC BA[2:0] ODT[1:0] SCL SDA SA[1:0] Description Clock Inputs, positive line Clock Inputs, negative line Clock Enables Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Autoprecharge Address Input/Burst Stop SDRAM Bank Address On-die termination control 2 2 2 1 1 1 2 14 1 1 3 2 Pin Name DQ[63:0] DM[7:0] DQS[7:0] DQS[7:0] RESET TEST EVENT VDD VSS VREFDQ VREFCA VDDSPD Vtt NC Description Data Input/Output Data Masks Data strobes Data strobes complement Reset pin 64 8 8 8 1 Logic Analyzer specific test pin (No 1 connect on SODIMM) Temperature event pin Core and I/O power Ground Input/Output Reference SPD and Temp sensor power Termination voltage Reserved for future use Total 1 18 52 2 1 2 2 204 Serial Presence Detect (SPD) Clock 1 input SPD Data Input/Output SPD address 1 2 Rev. 0.2 / Dec. 2008 7 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 2.2 Input/Output Functional Description Symbol CK0/CK0 CK1/CK1 Type Polarity Function The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when Input Cross point CKE[1:0] Input Active High low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR3 SDRAM command decoder when low and disables the S[1:0] Input Active Low command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. RAS, CAS, WE BA[2:0] ODT[1:0] Input Input Input Active Low Active High When sampled at the cross point of the rising edge of CK and falling edge of CK, signals CAS, RAS, and WE define the operation to be executed by the SDRAM. Selects which DDR3 SDRAM internal bank of eight is activated. Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode register. During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write A[9:0], A10/AP, A11, A12/BC, A[15:13] Input - cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-thefly) will be performed (HIGH, no burst chop; LOW, burst chopped) DQ[63:0] DM[7:0] In/Out Input Active High Data Input/Output pins. The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. The data strobes, associated with one data byte, sourced with data transfers. In DQS[7:0], DQS[7:0] Write mode, the data strobe is sourced by the controller and is centered in the data In/Out Cross Point window. In Read mode, the data strobe is sourced by the DDR3 SDRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. Rev. 0.2 / Dec. 2008 8 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Symbol VDD,VDDSPD, VSS, VREFDQ, VREFCA SDA SCL SA[1:0] TEST Type Supply Supply Polarity Function Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module. Reference voltage for SSTL15 inputs. This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and In/Out Input Input In/Out Wire OR Out In Temp sensor. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up. This signal is used to clock data into and out of the SPD EEPROM and Temp sensor. Address pins used to select the Serial Presence Detect and Temp sensor base address. The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules (SO-DIMMs). The EVENT pin is reserved for use to flag critical module temperature. A resistor EVENT RESET Active Low Active Low may be connected from EVENT bus line to VDDSPD on the system planar to act as a pullup. This signal resets the DDR3 SDRAM Rev. 0.2 / Dec. 2008 9 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 2.3 Pin Assignment Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 Front Side VREFDQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 Back Side VSS DQ4 DQ5 VSS DQS0 DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 Pin # 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 Front Side DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD Pin # 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 Back Side VSS DQ28 DQ29 VSS DQS3 DQS3 VSS DQ30 DQ31 VSS CKE1 VDD A152 A142 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1 Pin # 105 Front Side VDD Pin # 106 Back Side VDD BA1 RAS VDD S0 ODT0 VDD ODT1 NC VDD Pin # 157 159 161 163 165 167 169 171 173 175 Front Side DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 Pin # 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 Back Side DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7 DQS7 VSS DQ62 DQ63 VSS EVENT SDA SCL VTT 107 A10/AP 108 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 BA0 VDD WE CAS VDD A132 S1 VDD TEST VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS 110 112 114 116 118 120 122 124 126 VREFCA 177 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5 DQS5 VSS 179 181 183 185 187 189 191 193 195 197 83 A12/BC 85 87 89 91 93 95 97 99 101 103 A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0 199 VDDSPD 200 201 203 SA1 VTT 202 204 NC = No Connect; RFU = Reserved Future Use 1. TEST (pin 125) is reserved for bus analysis probes and is NC on normal memory modules. 2. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor. Rev. 0.2 / Dec. 2008 10 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 3. Functional Block Diagram 3.1 512MB, 64Mx64 Module(1Rank of x16) A[O:N]/BA[O:N] SCL SA0 SA1 A[O:N]/BA[O:N] DQS0 DQS0 DM0 DQ [0:7] DQS1 DQS1 DM1 DQ [8:15] LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] ZQ 240ohm +/-1% SCL A0 Temp Sensor (with SPD) A1 A2 EVENT EVENT SCL A0 A1 A2 S0 RAS ODT0 CK0 CKE0 CAS CK0 WE SDA The SPD may be integrated with the Temp Sensor or may be a separate component D0 ODT CK CKE SCL SA0 SA1 (SPD) WP SDA RAS CAS WE CS CK A[O:N]/BA[O:N] DQS2 DQS2 DM2 DQ [16:23] DQS3 DQS3 DM3 DQ [24:31] LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] ZQ 240ohm +/-1% Vtt VDDSPD VREFCA VREFDQ Vtt SPD/TS D0–D3 D0–D3 D0–D3 D0–D3, SPD, Temp sensor D0–D3 D0–D3 Terminated at near card edge NC NC Temp Sensor D0-D3 D1 ODT VDD VSS CK0 CK0 CK1 CK1 ODT1 S1 EVENT RESET RAS CAS CS CS ODT RAS CAS CKE CK A[O:N]/BA[O:N] DQS4 DQS4 DM4 DQ [32:39] DQS5 DQS5 DM5 DQ [40:47] LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] D2 WE CK CK CKE ZQ WE CK 240ohm +/-1% D0 D1 D2 D3 A[O:N]/BA[O:N] DQS6 DQS6 DM6 DQ [48:55] DQS7 DQS7 DM7 DQ [56:63] LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] ZQ 240ohm +/-1% D3 ODT RAS CAS CS CKE WE CK CK NOTES 1. DQ wiring may differ from that shown however, DQ, DM, DQS, and DQS relationships are maintained as shown Rank 0 Address and Control Lines Vtt Vtt VDD Rev. 0.2 / Dec. 2008 Vtt 11 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 3.2 1GB, 128Mx64 Module(2Rank of x16) ODT0 A[O:N]/BA[O:N] ODT1 CK0 CKE0 CK1 CKE1 SCL SA0 SA1 A[O:N]/BA[O:N] A[O:N]/BA[O:N] DQS0 DQS0 DM0 DQ [0:7] DQS1 DQS1 DM1 DQ [8:15] LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] ZQ 240ohm +/-1% D0 ODT CK CKE LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] ZQ 240ohm +/-1% SCL A0 Temp Sensor (with SPD) A1 A2 EVENT EVENT SCL A0 A1 A2 CK0 RAS CAS S0 CK1 WE S1 SDA The SPD may be integrated with the Temp Sensor or may be a separate component D4 ODT CK CKE SCL SA0 SA1 (SPD) WP SDA CAS RAS RAS CAS WE CK WE CS CS CK Vtt DQS2 DQS2 DM2 DQ [16:23] DQS3 DQS3 DM3 DQ [24:31] LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] 240ohm +/-1% LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] 240ohm +/-1% VDDSPD VREFCA VREFDQ VDD A[O:N]/BA[O:N] Vtt SPD/TS D0–D7 D0–D7 D0–D7 D0–D7, SPD, Temp sensor D0–D3 D0–D7 D0–D3 D0–D7 Temp Sensor D0-D7 ZQ ZQ A[O:N]/BA[O:N] D1 ODT D5 ODT CK CKE VSS CK0 CK1 CK0 CK1 EVENT RESET RAS CAS CK CKE RAS CAS WE WE CK CS A[O:N]/BA[O:N] ODT RAS CAS CKE CK CS A[O:N]/BA[O:N] A[O:N]/BA[O:N] DQS6 DQS6 DM6 DQ [48:55] DQS7 DQS7 DM7 DQ [56:63] LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] ZQ ZQ D0 D1 D2 D3 D3 ODT D7 ODT CK CKE NOTES 1. DQ wiring may differ from that shown however, DQ, DM, DQS, and DQS relationships are maintained as shown Rank 0 Rank 1 Address and Control Lines RAS CAS CKE RAS CAS WE CK WE CK Vtt Vtt VDD VDD Vtt Rev. 0.2 / Dec. 2008 CS CS CK Vtt 240ohm +/-1% CS LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] 240ohm +/-1% ODT RAS CAS CK CK CKE WE A[O:N]/BA[O:N] DQS4 DQS4 DM4 DQ [32:39] DQS5 DQS5 DM5 DQ [40:47] LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] ZQ 240ohm +/-1% CS CK D2 LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] ZQ 240ohm +/-1% D6 D4 D5 D6 D7 WE CK V1 V2 V3 V4 Vtt V1 V2 V3 V4 12 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C A[O:N]/BA[O:N] 3.3 2GB, 256Mx64 Module(2Rank of x8) Cterm ODT0 CK0 CKE0 CKE1 ODT1 VDD Vtt Cterm VDD Vtt Vtt CK1 RAS CAS CK1 S1 DQS3 DQS3 DM3 DQ[24:31] DQS DQS DM DQ [0:7] ZQ 240ohm +/-1% S0 CK0 WE D11 A[O:N]/BA[O:N] LDQS LDQS LDM DQ [0:7] ZQ 240ohm +/-1% D3 A[O:N]/BA[O:N] DQS DQS DM DQ [0:7] ZQ 240ohm +/-1% D4 A[O:N]/BA[O:N] DQS DQS DM DQ [0:7] ZQ 240ohm +/-1% D12 A[O:N]/BA[O:N] DQS4 DQS4 DM4 DQ[32:39] ODT ODT ODT CS CS CS DQS1 DQS1 DM1 DQ[8:15] DQS DQS DM DQ [0:7] ZQ 240ohm +/-1% D1 A[O:N]/BA[O:N] LDQS LDQS LDM DQ [0:7] ZQ 240ohm +/-1% D9 A[O:N]/BA[O:N] DQS DQS DM DQ [0:7] ZQ 240ohm +/-1% CS D14 A[O:N]/BA[O:N] DQS DQS DM DQ [0:7] ZQ 240ohm +/-1% ODT CAS CAS CAS RAS RAS RAS RAS CK CKE CK CKE CK CKE CAS CK CKE WE WE WE CK CK CK WE CK D6 A[O:N]/BA[O:N] DQS6 DQS6 DM6 DQ[48:55] ODT ODT ODT CS CS DQS0 DQS0 DM0 DQ[0:7] DQS DQS DM DQ [0:7] ZQ 240ohm +/-1% CS D0 A[O:N]/BA[O:N] LDQS LDQS LDM DQ [0:7] ZQ 240ohm +/-1% D8 A[O:N]/BA[O:N] DQS DQS DM DQ [0:7] ZQ 240ohm +/-1% CS D15 A[O:N]/BA[O:N] DQS DQS DM DQ [0:7] ZQ 240ohm +/-1% ODT CAS RAS RAS CK CKE CAS RAS RAS CK CKE CK CKE CK CKE CAS CAS WE WE WE CK WE CK CK CK D7 A[O:N]/BA[O:N] DQS7 DQS7 DM7 DQ[56:43] ODT ODT CAS CAS ODT CS DQS2 DQS2 DM2 DQ[6:23] DQS DQS DM DQ [0:7] ZQ 240ohm +/-1% D2 A[O:N]/BA[O:N] LDQS LDQS LDM DQ [0:7] ZQ 240ohm +/-1% D10 A[O:N]/BA[O:N] DQS DQS DM DQ [0:7] ZQ 240ohm +/-1% CS D13 A[O:N]/BA[O:N] DQS DQS DM DQ [0:7] ZQ 240ohm +/-1% DQS5 DQS5 DM5 DQ[40:47] D5 A[O:N]/BA[O:N] ODT ODT ODT RAS RAS CK CKE CK CKE CS CS The SPD may be integrated with the Temp Sensor or may be a separate component SCL SA0 SA1 SCL A0 A1 A2 D9 CS CS Vtt ODT CAS RAS RAS CK CKE CAS CAS CAS CK CKE WE WE WE CK WE CK CK CK ODT RAS RAS CK CKE CK CKE CAS RAS RAS CK CKE CAS CK CKE WE WE WE CK WE CK CK CK CS CS Vtt SPD/TS D0–D15 D0–D15 D0–D15 D0–D15, SPD, Temp sensor D0–D7 D8–D15 D0–D7 D8–D15 D0-D7 D8-D15 D0–D7 D8–D15 D0–D7 D8–D15 Temp Sensor D0-D15 V2 D3 V1 V9 D12 V8 VDDSPD D6 (SPD) WP VREFCA VREFDQ VDD VSS CK0 CK1 CK0 CK1 SDA V3 D8 V7 V4 V5 D10 D5 V6 D7 SCL SA0 SA1 SCL A0 Temp Sensor (with SPD) A1 A2 EVENT EVENT SDA D0 V4 V3 D2 V5 D13 V6 V7 CKE0 D15 CKE1 S0 S1 ODT0 ODT1 EVENT RESET V1 V2 D11 NOTES 1. DQ wiring may differ from that shown however, DQ, DM, DQS, and DQS relationships are maintained as shown Vtt V1 V9 V8 D4 Rank 0 Rank 1 D1 D14 Rev. 0.2 / Dec. 2008 13 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 4. ABSOLUTE MAXIMUM RATINGS 4.1 Absolute Maximum DC Ratings Symbol VDD VDDQ VIN, VOUT TSTG Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on any pin relative to Vss Storage Temperature Rating - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V -55 to +100 ℃ Units V V V ℃ Notes 1,3 1,3 1 1, 2 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. 4.2 DRAM Component Operating Temperature Range Symbol TOPER Parameter Normal Temperature Range Extended Temperature Range Rating 0 to 85 85 to 95 Units ℃ ℃ Notes ,2 1,3 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85°… and 95°… case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. (This double refresh requirement may not apply for some devices.) It is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to supplier data sheet and/ or the DIMM SPD for option avail ability. b) If Self-Refresh operation is required in the Extended Temperature Range, than it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0band MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Rev. 0.2 / Dec. 2008 14 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 5. AC & DC Operating Conditions 5.1 Recommended DC Operating Conditions Rating Min. 1.425 1.425 Typ. 1.500 1.500 Max. 1.575 1.575 Symbol VDD VDDQ Parameter Supply Voltage Supply Voltage for Output Units V V Notes 1,2 1,2 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD bad VDDQ tied together. 5.2 DC & AC Logic Input Levels 5.2.1 DC & AC Logic Input Levels for Single-Ended Signals DDR3-800, DDR3-1066, DDR3-1333 Symbol VIH(DC) VIL(DC) VIH(AC) VIL(AC) VRefDQ (DC) VRefCA (DC) VTT Parameter Min DC input logic high DC input logic low AC input logic high AC input logic low Reference Voltage for DQ, DM inputs Reference Voltage for ADD, CMD inputs Termination voltage for DQ, DQS outputs 0.49 * VDD 0.49 * VDD VDDQ/2 - TBD Vref + 0.175 Vref + 0.100 Max Vref - 0.100 Vref - 0.175 0.51 * VDD 0.51 * VDD VDDQ/2 + TBD V V V V V V V 1, 2 1, 2 1, 2 1, 2 3, 4 3, 4 Unit Notes 1. For DQ and DM, Vref = VrefDQ. For input only pins except RESET#, Vref = VrefCA. 2. The “t.b.d.” entries might change based on overshoot and undershoot specification. 3. The ac peak noise on VRef may not allow VRef to deviate from VRef (DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). For reference: approx. VDD/2 +/- 15 mV. The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure 6.2.1. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise).VRef(DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in Table 1. Furthermore VRef (t) may temporarily deviate from VRef (DC) by no more than +/- 1% VDD. Rev. 0.2 / Dec. 2008 15 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C voltage VDD VRef ac-noise VRef(DC) VRef(t) VRef(DC)max VDD/2 VRef(DC)min VSS time < Figure 6.2.1: Illustration of Vref (DC) tolerance and Vref AC-noise limits > The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VRef. "VRef" shall be understood as VRef (DC), as defined in Figure 6.2.1 This clarifies, that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VRef (DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings. 5.2.2 DC & AC Logic Input Levels for Differential Signals DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600 Min + 0.200 Max - 0.200 Symbol VIHdiff VILdiff Note1: Parameter Differential input logic high Differential input logic low Unit V V Notes 1 1 Refer to “Overshoot and Undershoot Specification section 6.5 on 26 page Rev. 0.2 / Dec. 2008 16 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 5.2.3 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the requirements in Table 6.2.3 The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the midlevel between of VDD and VSS. VDD CK#, DQS# VIX VDD/2 VIX VIX CK, DQS VSS < Figure 5.2.3 Vix Definition > DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600 Symbol Parameter Min VIX Differential Input Cross Point Voltage relative to VDD/2 - 150 Max + 150 mV Unit Notes < Table 5.2.3: Cross point voltage for differential input signals (CK, DQS) > Rev. 0.2 / Dec. 2008 17 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 5.3 Slew Rate Definitions 5.3.1 For Single Ended Input Signals - Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS) Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VRef and the first crossing of VIH (AC) min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VRef and the first crossing of VIL (AC) max. - Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH) Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (DC) max and the first crossing of VRef. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH (DC) min and the first crossing of VRef. Measured Min Vref Vref VIL (DC) max VIH (DC) min Max VIH (AC) min VIL (AC) max Vref Vref Description Input slew rate for rising edge Input slew rate for falling edge Input slew rate for rising edge Input slew rate for falling edge Defined by VIH (AC) min-Vref Delta TRS Vref-VIL (AC) max Delta TFS Vref-VIL (DC) max Delta TFH VIH (DC) min-Vref Delta TRH Applicable for Setup (tIS, tDS) Hold (tIH, tDH) < Table 5.3.1: Single-Ended Input Slew Rate Definition > Part A: Set up Delta TRS Single Ended input Voltage(DQ,ADD, CMD) vIH(AC)min vIH(DC)min vRefDQ or vRefCA vIL(DC)max vIL(AC)max Delta TFS Rev. 0.2 / Dec. 2008 18 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C P a rt B : H o ld D e lta T R H Single Ended input Voltage(DQ,ADD, CMD) v IH (A C )m in v IH (D C )m in v R e fD Q o r v R e fC A v IL (D C )m a x v IL (A C )m a x D e lta T F H < Figure 5.3.1: Input Nominal Slew Rate Definition for Single-Ended Signals > 5.3.2 Differential Input Signals Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown in below Table and Figure . Measured Min VILdiffmax VIHdiffmin Max VIHdiffmin VILdiffmax Description Differential input slew rate for rising edge (CK-CK and DQS-DQS) Differential input slew rate for falling edge (CK-CK and DQS-DQS) Note: Defined by VIHdiffmin-VILdiffmax DeltaTRdiff VIHdiffmin-VILdiffmax DeltaTFdiff The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds. Rev. 0.2 / Dec. 2008 19 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Differential Input Voltage (i.e. DQS-DQS; CK-CK) D e lta T R d iff vIH d iffm in 0 vILd iffm a x D e lta T F d iff < Figure 5.3.2: Differential Input Slew Rate Definition for DQS,DQS# and CK,CK# > 5.4 DC & AC Output Buffer Levels 5.4.1 Single Ended DC & AC Output Levels Below table shows the output levels used for measurements of single ended signals. Symbol VOH(DC) VOM(DC) VOL(DC) VOH(AC) VOL(AC) Parameter DC output high measurement level (for IV curve linearity) DC output mid measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) AC output high measurement level (for output SR) AC output low measurement level DDR3-800, 1066, 1333 0.8 x VDDQ 0.5 x VDDQ 0.2 x VDDQ VTT + 0.1 x VDDQ Unit V V V V 1 Notes VTT - 0.1 x VDDQ V 1 (for output SR) 1. The swing of ± 0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ / 2. Rev. 0.2 / Dec. 2008 20 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 5.4.2 Differential DC & AC Output Levels Below table shows the output levels used for measurements of differential signals. Symbol VOHdiff (AC) VOLdiff (AC) Parameter AC differential output high measurement level (for output SR) DDR3-800, 1066, 1333 + 0.2 x VDDQ Unit V Notes 1 AC differential output low - 0.2 x VDDQ V 1 measurement level (for output SR) 1. The swing of °æ 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with a driver impedance of 40ߟ and an effective test load of 25ߟ to VTT = VDDQ/2 at each of the differential output 5.4.3 Single Ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in below Table and Figure 6.4.3. Measured From VOL(AC) VOH(AC) To VOH(AC) VOL(AC) Description Single ended output slew rate for rising edge Single ended output slew rate for falling edge Note: Defined by VOH(AC)-VOL(AC) DeltaTRse VOH(AC)-VOL(AC) DeltaTFse Output slew rate is verified by design and characterisation, and may not be subject to production test. D e lt a T R s e Single Ended Output Voltage(l.e.DQ) vO H (A C ) V∏ vO L(A C ) D e lt a T F s e < Figure 5.4.3: Single Ended Output Slew Rate Definition > Rev. 0.2 / Dec. 2008 21 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Parameter Single-ended Output Slew Rate Symbol SRQse DDR3-800 Min 2.5 Max 5 DDR3-1066 Min 2.5 Max 5 DDR3-1333 Min 2.5 Max 5 Units V/ns *** Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) For Ron = RZQ/7 setting < Table 5.4.3: Output Slew Rate (single-ended) > 5.4.4 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in below Table and Figure 5.4.4 Measured From VOLdiff (AC) VOHdiff (AC) To VOHdiff (AC) VOLdiff (AC) Description Differential output slew rate for rising edge Differential output slew rate for falling edge Defined by VOHdiff (AC)-VOLdiff (AC) DeltaTRdiff VOHdiff (AC)-VOLdiff (AC) DeltaTFdiff Note: Output slew rate is verified by design and characterization, and may not be subject to production test.. Differential Output Voltage(i.e. DQS-DQS) D e lta T R d iff v O H d iff(A C ) O v O L d iff(A C ) D e lta T F d iff < Figure 5.4.4: Differential Output Slew Rate Definition > Rev. 0.2 / Dec. 2008 22 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C DDR3-800 Parameter Differential Output Slew Rate Symbol Min SRQdiff 5 DDR3-1066 Min 5 DDR3-1333 Min 5 Max 10 Max 10 Max 10 Units V/ns ***Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) diff: Differential Signals For Ron = RZQ/7 setting < Table 5.4.4: Differential Output Slew Rate > 5.5 Overshoot and Undershoot Specifications 5.5.1 Address and Control Overshoot and Undershoot Specifications Description Maximum peak amplitude allowed for overshoot area (see Figure) Maximum peak amplitude allowed for undershoot area (see Figure) Maximum overshoot area above VDD (See Figure) Maximum undershoot area below VSS (See Figure) Specification DDR3-800 0.4V 0.4V 0.67 V-ns 0.67 V-ns DDR3-1066 0.4V 0.4V 0.5 V-ns 0.5 V-ns DDR3-1333 0.4V 0.4V 0.4 V-ns 0.4 V-ns < Table 5.5.1: AC Overshoot/Undershoot Specification for Address and Control Pins > < Figure 5.5.1: Address and Control Overshoot and Undershoot Definition > Maximum Amplitude Overshoot Area Volts (V) VDD VSS Undershoot Area Maximum Amplitude Time (ns) Rev. 0.2 / Dec. 2008 23 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 5.5.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications Specification DDR3-800 0.4V 0.4V 0.25 V-ns 0.25 V-ns DDR3-1066 0.4V 0.4V 0.19 V-ns 0.19 V-ns DDR3-1333 0.4V 0.4V 0.15 V-ns 0.15 V-ns Description Maximum peak amplitude allowed for overshoot area (see Figure) Maximum peak amplitude allowed for undershoot area (see Figure) Maximum overshoot area above VDDQ (See Figure) Maximum undershoot area below VSSQ (See Figure) < Table 5.5.2: AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask > M a x im u m A m p litu d e O v e rsh o o t A re a V o lts (V ) VDDQ VSSQ U n d e rsh o o t A re a M a x im u m A m p litu d e T im e (n s) C lo c k , D a ta S tro b e a n d M a sk O v e rsh o o t a n d U n d e rsh o o t D e fin itio n < Figure 5.5.2: Clock, Data, Strobe and Mask Overshoot and Undershoot Definition > Rev. 0.2 / Dec. 2008 24 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 5.6 Pin Capacitance Parameter Input/output capacitance (DQ, DM, DQS, DQS#, TDQS, TDQS#) Input capacitance, CK and CK# Input capacitance delta CK and CK# Input capacitance (All other input-only pins) Input capacitance delta, DQS and DQS# Input capacitance delta (All CTRL input-only pins) Input capacitance delta (All ADD/CMD input-only pins) Input/output capacitance delta (DQ, DM, DQS, DQS#) Notes: 1. TDQS/TDQS# are not necessarily input function but since TDQS is sharing DM pin and the parasitic characterization of TDQS/TDQS# should be close as much as possible, Cio & Cdio requirement is applied (recommend deleting note or changing to “Although the DM, TDQS and TDQS# pins have different functions, the loading matches DQ and DQS.”) 2. This parameter is not subject to production test. It is verified by design and characterization. Input capacitance is measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE, RESET# and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK#. 5. The minimum CCK will be equal to the minimum CI. 6. Input only pins include: ODT, CS, CKE, A0-A15, BA0-BA2, RAS#, CAS#, WE#. 7. CTRL pins defined as ODT, CS and CKE. 8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK#)) 9. ADD pins defined as A0-A15, BA0-BA2 and CMD pins are defined as RAS#, CAS# and WE#. 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK#)) 11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS#)) 12. Absolute value of CIO(DQS) - CIO(DQS#) Symbol DDR3-800 Min TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD TBD TBD DDR3-1066 Min TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD TBD TBD DDR3-1333 Min TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD TBD TBD Units Notes CIO CCK CDCK CI CDDQS CDI_CTRL CDI_ADD_C MD pF pF pF pF pF pF pF pF 1,2,3 2,3,5 2,3,4 2,3,6 2,3,12 2,3,7,8 2,3,9,1 0 2,3,11 CDIO Rev. 0.2 / Dec. 2008 25 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 5.7 IDD Specifications (TCASE: 0 to 95oC) 512MB, 64M x 64 SO-DIMM: HMT164S6AFP6C Symbol IDD0 IDD1 IDD2P(F) IDD2P(S) IDD2Q IDD2N IDD3P IDD3N IDD4W IDD4R IDD5B IDD6(D) IDD6(S) IDD7 DDR3 800 360 480 100 40 180 200 140 220 700 700 740 40 24 1300 DDR3 1066 420 540 120 40 240 240 180 280 880 860 780 40 24 1420 DDR3 1333 480 620 140 40 280 300 200 340 1060 1020 840 40 24 1720 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1 1 note 1GB, 128M x 64 SO-DIMM: HMT112S6AFP6C Symbol IDD0 IDD1 IDD2P(F) IDD2P(S) IDD2Q IDD2N IDD3P IDD3N IDD4W IDD4R IDD5B IDD6(D) IDD6(S) IDD7 DDR3 800 560 680 200 80 360 400 280 440 900 900 940 80 48 1500 DDR3 1066 660 780 240 80 480 480 360 560 1120 1100 1020 80 48 1660 DDR3 1333 780 960 280 80 560 600 400 680 1360 1320 1140 80 48 2020 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1 1 note Rev. 0.2 / Dec. 2008 26 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 2GB, 256M x 64 SO-DIMM: HMT125S6AFP8C Symbol IDD0 IDD1 IDD2P(F) IDD2P(S) IDD2Q IDD2N IDD3P IDD3N IDD4W IDD4R IDD5B IDD6(D) IDD6(S) IDD7 DDR3 800 1040 1160 400 160 720 800 560 880 1520 1440 1880 160 96 2200 DDR3 1066 1240 1360 480 160 960 960 720 1120 1920 1800 2040 160 96 2480 DDR3 1333 1440 1560 560 160 1120 1200 800 1360 2160 2280 2320 160 96 3040 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1 1 note Rev. 0.2 / Dec. 2008 27 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 5.7 IDD Measurement Conditions Within the tables provided further down, an overview about the IDD measurement conditions is provided as follows: Table 1 — Overview of Tables providing IDD Measurement Conditions and DRAM Behavior Measurement Conditions IDD0 and IDD1 IDD2N, IDD2Q, IDD2P(0), IDD2P(1) IDD3N and IDD3P IDD4R, IDD4W, IDD7 IDD7 for different Speed Grades and different tRRD, tFAW conditions IDD5B IDD6, IDD6ET Table number Table 5 on page 33 Table 6 on page 36 Table 7 on page 38 Table 8 on page 39 Table 9 on page 42 Table 10 on page 43 Table 11 on page 44 Within the tables about IDD measurement conditions, the following definitions are used: - LOW is defined as VIN = VIHAC (min.). - STABLE is defined as inputs are stable at a HIGH or LOW level. - FLOATING is defined as inputs are VREF = VDDQ / 2. - SWITCHING is defined as described in the following 2 tables. Table 2 — Definition of SWITCHING for Address and Command Input Signals SWITCHING for Address (row, column) and Command Signals (CS, RAS, CAS, WE) is defined as: If not otherwise mentioned the inputs are stable at HIGH or LOW during 4 clocks and change Address (row, column): then to the opposite value (e.g. Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax ..... please see each IDDx definition for details Bank address: If not otherwise mentioned the bank addresses should be switched like the row/column addresses - please see each IDDx definition for details Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW} Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH,HIGH,HIGH} Define Command Background Pattern = D D D D D D D D D D D D... If other commands are necessary (e.g. ACT for IDD0 or Read for IDD4R), the Background Pattern Command is substituted by the respective CS, RAS, CAS, WE levels of the necessary command. See each IDDx definition for details and figures 1,2,3 as examples. Command (CS, RAS, CAS, WE): Rev. 0.2 / Dec. 2008 28 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 3 — Definition of SWITCHING for Data (DQ) SWITCHING for Data (DQ) is defined as Data DQ is changing between HIGH and LOW every other data transfer (once per clock) for DQ signals, which means that data DQ is stable during one clock; see each IDDx definition for exceptions from this rule and for further details. See figures 1,2,3 as examples. NO Switching; DM must be driven LOW all the time Data (DQ) Data Masking (DM) Timing parameters are listed in the following table: Table 4 — Parameter Bin For IDD testing the following parameters are utilized. DDR3-800 5-5-5 2.5 5 12.5 50 37.5 12.5 x4/x8 x16 x4/x8 x16 40 50 10 10 90 110 160 tbd 6 15 52.5 37.5 15 40 50 10 10 90 110 160 tbd 6 11.25 48.75 37.5 11.25 37.5 50 7.5 10 90 110 160 tbd 6-6-6 6-6-6 DDR3-1066 7-7-7 1.875 7 13.13 50.63 37.5 13.13 37.5 50 7.5 10 90 110 160 tbd 8 15 52.50 37.5 15 37.5 50 7.5 10 90 110 160 tbd 7 10.5 46.5 36 10.5 30 45 6.0 7.5 90 110 160 tbd 8-8-8 7-7-7 DDR3-1333 8-8-8 1.5 8 12 48 36 12 30 45 6.0 7.5 90 110 160 tbd 9 13.5 49.5 36 13.5 30 45 6.0 7.5 90 110 160 tbd 9-9-9 Unit ns clk ns ns ns ns ns ns ns ns ns ns ns ns tCKmin(IDD) CL(IDD) tRCDmin(IDD) tRCmin(IDD) tRASmin(IDD) tRPmin(IDD) tFAW(IDD) tRRD(IDD) tRFC(IDD) 512Mb Gb Gb Gb tRFC(IDD) - 1 tRFC(IDD) - 2 tRFC(IDD) - 4 The following conditions apply: - IDD specifications are tested after the device is properly initialized. - Input slew rate is specified by AC Parametric test conditions. - IDD parameters are specified with ODT and output buffer disabled (MR1 Bit A12). Rev. 0.2 / Dec. 2008 29 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 5 — IDD Measurement Conditions for IDD0 and IDD1 IDD0 Operating Current 0 Current IDD1 Operating Current 1 -> One Bank Activate -> Read -> Precharge Figure 1 Name -> One Bank Activate -> Precharge Measurement Condition Timing Diagram Example CKE External Clock HIGH on HIGH on tCK tRC tRAS tRCD tRRD CL AL CS Command Inputs (CS,RAS, CAS, WE) tCKmin(IDD) tRCmin(IDD) tRASmin(IDD) n.a. n.a. n.a. n.a. HIGH between. Activate and Precharge Commands SWITCHING as described in Table 2 only exceptions are Activate and Precharge commands; example of IDD0 pattern: A0DDDDDDDDDDDDDD P0 (DDR3-800: tRAS = 37.5ns between (A)ctivate and (P)recharge to bank 0; Definition of D and D: see Table 2 tCKmin(IDD) tRCmin(IDD) tRASmin(IDD) tRCDmin(IDD) n.a. CL(IDD) 0 HIGH between Activate, Read and Precharge SWITCHING as described in Table 2; only exceptions are Activate, Read and Precharge commands; example of IDD1 pattern: A0DDDDR0DDDDDDDDD P0 (DDR3-800 -555: tRCD = 12.5ns between (A)ctivate and (R)ead to bank 0; Definition of D and D: see Table 2) Rev. 0.2 / Dec. 2008 30 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 5 — IDD Measurement Conditions for IDD0 and IDD1 IDD0 Operating Current 0 Name -> One Bank Activate -> Precharge Row, Column Addresses Current IDD1 Operating Current 1 -> One Bank Activate -> Read -> Precharge in Table 2; Address Input A10 must be LOW all the time! bank address is fixed (bank 0) Read Data: output data switches every clock, which means that Read data is stable during one clock cycle. To achieve Iout = 0mA, the output buffer should be switched off by MR1 Bit A12 set to “1”. When there is no read data burst from DRAM, the DQ I/O should be FLOATING. Row addresses SWITCHING as described Row addresses SWITCHING as described in Table 2; Address Input A10 must be LOW all the time! Bank Addresses Data I/O bank address is fixed (bank 0) SWITCHING as described in Table 3 Output Buffer DQ,DQS / MR1 bit A12 ODT / MR1 bits [A6, A2] Burst length Active banks Idle banks Mode Register Bit 12 off / 1 disabled / [0,0] n.a. one ACT-PRE loop all other off / 1 disabled / [0,0] 8 fixed / MR0 Bits [A1, A0] = {0,0} one ACT-RD-PRE loop all other n.a. Precharge Power Down Mode / n.a. Rev. 0.2 / Dec. 2008 31 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C T0 CK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T12 T14 T16 T18 BA[2:0] 000 000 3FF 000 3FF 000 3F ADDR_a[9:0] ADDR_b[10] ADDR_c[12:11] 00 11 00 11 00 CS RAS CAS WE CMD ACT D D# D# D RD D# D# D D D# D# D D D# PRE D D D# DQ DM 00110011 IDD1 Measurment Loop < Figure 1. IDD1 Example > (DDR3-800-555, 512Mb x8): Data DQ is shown but the output buffer should be switched off (per MR1 Bit A12 =”1”) to achieve Iout = 0mA. Address inputs are split into 3 parts. Rev. 0.2 / Dec. 2008 32 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 6 — IDD Measurement Conditions for IDD2N, IDD2P(1), IDD2P(0) and IDD2Q Current Name IDD2N IDD2P(1) a IDD2P(0) Precharge Power Down Current Slow Exit MRS A12 Bit = 0 IDD2Q Precharge Quiet Standby Current Precharge Power Precharge Standby Down Current Current Fast Exit MRS A12 Bit = 1 Measurement Condition Timing Diagram Example CKE External Clock Figure 2 HIGH on LOW on LOW on HIGH on tCK tRC tRAS tRCD tRRD CL AL CS Bank Address, Row Addr. and Command Inputs Data inputs Output Buffer DQ,DQS / MR1 bit A12 ODT / MR1 bits [A6, A2] Burst length Active banks Idle banks Precharge Power Down Mode / Mode Register Bit a tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. HIGH SWITCHING as described in Table 2 SWITCHING off / 1 disabled / [0,0] n.a. none all n.a. tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. STABLE STABLE FLOATING off / 1 disabled / [0,0] n.a. none all Fast Exit / 1 (any valid command after tXPb) tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. STABLE STABLE FLOATING off / 1 disabled / [0,0] n.a. none all tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. HIGH STABLE FLOATING off / 1 disabled / [0,0] n.a. none all Slow Exit / 0 Slow exit (RD and n.a. ODT commands must satisfy tXPDLL-AL) a. In DDR3, the MRS Bit 12 defines DLL on/off behaviour ONLY for precharge power down. There are 2 different a. b. Precharge Power Down states possible: one with DLL on (fast exit, bit 12 = 1) and one with DLL off (slow exit, bit 12 = 0). b. Because it is an exit after precharge power down, the valid commands are: Activate, Refresh, Mode-Register Set, Enter - Self Refresh Rev. 0.2 / Dec. 2008 33 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C T0 CK T1 T2 T3 T4 T5 T6 T7 T8 T9 BA[2:0] 0 7 0 ADDR[12:0] 0 7 0 CS RAS CAS WE CMD D# D# D D D# D# D D D# D# DQ[7:0] FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF DM (DDR3-800-555, 512Mb x8) Rev. 0.2 / Dec. 2008 34 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 7 — IDD Measurement Conditions for IDD3N and IDD3P(fast exit) IDD3N Active Standby Current Measurement Condition Current Name IDD3P Active Power-Down Currenta Always Fast Exit Timing Diagram Example CKE External Clock Figure 2 HIGH on LOW on tCK tRC tRAS tRCD tRRD CL AL CS Addr. and cmd Inputs Data inputs Output Buffer DQ,DQS / MR1 bit A12 ODT / MR1 bits [A6, A2] Burst length Active banks Idle banks Precharge Power Down Mode / Mode Register Bit a tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. HIGH SWITCHING as described in Table 2 SWITCHING as described in Table 3 off / 1 disabled / [0,0] n.a. all none n.a. tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. STABLE STABLE FLOATING off / 1 disabled / [0,0] n.a. all none n.a. (Active Power Down Mode is always “Fast Exit” with DLL on a. DDR3 will offer only ONE active power down mode with DLL on (-> fast exit). MRS bit 12 will not be used for active power down. Instead bit 12 will be used to switch between two different precharge power down modes. Rev. 0.2 / Dec. 2008 35 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 8 — IDD Measurement Conditions for IDD4R, IDD4W and IDD7 Current Name IDD4R Operating Current Burst Read IDD4W Operating Current Burst Write IDD7 All Bank Interleave Read Current Measurement Condition Timing Diagram Example CKE External Clock Figure 3 HIGH on HIGH on HIGH on tCK tRC tRAS tRCD tRRD CL AL CS Command Inputs (CS, RAS, CAS, WE) tCKmin(IDD) n.a. n.a. n.a. n.a. CL(IDD) 0 HIGH btw. valid cmds SWITCHING as described in Table 2; exceptions are Read commands => IDD4R Pattern: tCKmin(IDD) n.a. n.a. n.a. n.a. CL(IDD) 0 HIGH btw. valid cmds SWITCHING as described in Table 2; exceptions are Write commands => IDD4W Pattern: tCKmin(IDD) tRCmin(IDD) tRASmin(IDD) tRCDmin(IDD) tRRDmin(IDD) CL(IDD) tRCDmin - 1 tCK HIGH btw. valid cmds For patterns see Table 9 R0DDDR1DDDR2DDDR3.DD W0DDDW1DDDW2DDDW3 DDD W4... D R4..... Rx = Read from bank x; Wx = Write to bank x; Definition of D and D: see Definition of D and D: see Table 2 Table 2 Rev. 0.2 / Dec. 2008 36 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 8 — IDD Measurement Conditions for IDD4R, IDD4W and IDD7 Current Name IDD4R Operating Current Burst Read column addresses IDD4W Operating Current Burst Write column addresses SWITCHING as described in Table 2; Address Input A10 must be LOW all the time! IDD7 All Bank Interleave Read Current Row, Column Addresses SWITCHING as described in Table 2; Address Input A10 must be LOW all the time! STABLE during DESELECTs Bank Addresses bank address cycling (0 -> 1 - bank address cycling (0 -> 1 > 2 -> 3...) Seamless Read Data Burst (BL8): output data switches every clock, which means that Read data is stable during one clock cycle. To achieve Iout = 0mA the output buffer should be switched off by MR1 Bit A12 set to “1”. > 2 -> 3...) bank address cycling (0 -> 1 > 2 -> 3...), see pattern in Table 9 Read Data (BL8): output data switches every clock, which means that Read data is stable during one clock cycle. To achieve Iout = 0mA the Seamless Write Data Burst (BL8): input data switches every clock, which means that Write data is stable during one clock cycle. DM is low all the time. DQ I/O output buffer should be switched off by MR1 Bit A12 set to “1”. Output Buffer DQ,DQS / MR1 bit A12 ODT / MR1 bits [A6, A2] Burst length Active banks Idle banks Precharge Power Down Mode / Mode Register Bit n.a. n.a. n.a. disabled / [0,0] 8 fixed / MR0 Bits [A1, A0] = {0,0} all none disabled / [0,0] 8 fixed / MR0 Bits [A1, A0] = {0,0} all none disabled / [0,0] 8 fixed / MR0 Bits [A1, A0] = {0,0} all, rotational none off / 1 off / 1 off / 1 Rev. 0.2 / Dec. 2008 37 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C T0 CK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 BA[2:0] 000 001 010 011 ADDR[12:0] 000 3FF 000 3FF ADDR_b[10] ADDR_c[12:11] 00 11 00 11 CS RAS CAS WE CMD[2:0] RD D D# D# RD D D# D# RD D D# D# RD DQ[7:0] 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF DM -> Start of Measurement Loop < Figure 3. IDD4R Example > (DDR3-800-555, 512Mb x8): data DQ is shown but the output buffer should be switched off (per MR1 Bit A12=”1”) to achieve Iout = 0mA. Address inputs are split into 3 parts. Rev. 0.2 / Dec. 2008 38 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 9 — Speed Mb/s all 800 all IDD7 Pattern for different Speed Grades and different tRRD, tFAW conditions Bin Org. tFAW [ns] x4/x8 x16 40 50 tFAW [CLK] 16 20 tRRD [ns] 10 10 tRRD IDD7 Patterna A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D DDDD A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D DDDD A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D A4 RA4 D D D D A5 RA5 D D D D A6 RA6 D D D D A7 RA7 D D D D D D D A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D DDDD A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D D D D D D D D A4 RA4 D D D A5 RA5 D D D A6 RA6 D D D A7 RA7 D D D D D D D D D D D D D A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D D A4 RA4 D D D A5 RA5 D D D A6 RA6 D D D A7 RA7 D D D D D D D A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D D D A4 RA4 D D D D A5 RA5 D D D D A6 RA6 D D D D A7 RA7 D D D D D D D D D DDD [CLK] (Note this entire sequence is repeated.) 4 4 all 1066 all x4/x8 37.5 20 7.5 4 x16 50 27 10 6 all 1333 all x4/x8 30 20 6 4 x16 45 30 7.5 5 all 1600 all x4/x8 30 24 6 5 x16 40 32 7.5 6 a. A0 = Activation of Bank 0; RA0 = Read with Auto-Precharge of Bank 0; D = Deselect Rev. 0.2 / Dec. 2008 39 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 10 — IDD Measurement Conditions for IDD5B Current IDD5B Burst Refresh Current Name Measurement Condition CKE External Clock HIGH on tCK tRC tRAS tRCD tRRD tRFC CL AL CS Addr. and cmd Inputs Data inputs Output Buffer DQ,DQS / MR1 bit A12 ODT / MR1 bits [A6, A2] Burst length Active banks Idle banks Precharge Power Down Mode / Mode Register Bit tCKmin(IDD) n.a. n.a. n.a. n.a. tRFCmin(IDD) n.a. n.a. HIGH btw. valid cmds SWITCHING SWITCHING off / 1 disabled / [0,0] n.a. Refresh command every tRFC = tRFCmin none n.a. Rev. 0.2 / Dec. 2008 40 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 11 — IDD Measurement Conditions for IDD6 and IDD6ET Current Name IDD6 Self-Refresh Current Normal Temperature Range TCASE = 0.. 85 °C Measurement Condition IDD6ET Self-Refresh Current Extended Temperature Range a TCASE = 0 .. 95 °C Temperature Auto Self Refresh (ASR) / MR2 Bit A6 Self Refresh Temperature Range (SRT) / MR2 Bit A7 CKE External Clock TCASE = 85 °C Disabled / “0” TCASE = 95 °C Disabled / “0” Normal / “0” LOW OFF; CK and CK at LOW n.a. n.a. n.a. n.a. n.a. n.a. n.a. FLOATING FLOATING FLOATING FLOATING FLOATING off / 1 disabled / [0,0] n.a. all during self-refresh actions all btw. Self-Refresh actions n.a. Extended / “1” LOW OFF; CK and CK at LOW n.a. n.a. n.a. n.a. n.a. n.a. n.a. FLOATING FLOATING FLOATING FLOATING FLOATING off / 1 disabled / [0,0] n.a. all during self-refresh actions all btw. Self-Refresh actions n.a. tCK tRC tRAS tRCD tRRD CL AL CS Command Inputs (RAS, CAS, WE) Row, Column Addresses Bank Addresses Data I/O Output Buffer DQ,DQS / MR1 bit A12 ODT / MR1 bits [A6, A2] Burst length Active banks Idle banks Precharge Power Down Mode / MR0 bit A12 a. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material. Rev. 0.2 / Dec. 2008 41 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 6. Electrical Characteristics and AC Timing 6.1 Refresh Parameters by Device Density Parameter REF command to ACT or REF command time Average periodic refresh interval tREFI Symbol tRFC 512Mb 1Gb 2Gb 4Gb 8Gb Units 90 110 160 300 350 ns 0 ×C < TCASE < 85 ×C 85 ×C < TCASE < 95 ×C 7.8 3.9 7.8 3.9 7.8 3.9 7.8 3.9 7.8 3.9 ms ms 6.2 DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin DDR3 800 Speed Bin CL - nRCD - nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CL = 6 CWL = 5 CWL = 5 Symbol min 12.5 12.5 12.5 50 37.5 2.5 2.5 5, 6 5 DDR3-800D 5-5-5 max 20 — — — 9 * tREFI 3.3 3.3 min 15 15 15 52.5 37.5 DDR3-800E 6-6-6 max 20 — — — 9 * tREFI ns ns ns ns ns ns ns 1)2)3)4) 1)2)3) Unit Notes tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) Reserved 2.5 6 5 3.3 Supported CL Settings Supported CWL Settings nCK nCK Rev. 0.2 / Dec. 2008 42 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C DDR3 1066 Speed Bin CL - nRCD - nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 6 CWL = 5 CL = 6 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 Symbol DDR3-1066E 6-6-6 min 11.25 11.25 11.25 48.75 37.5 2.5 max 20 — — — 9 * tREFI 3.3 DDR3-1066F 7-7-7 min 13.125 13.125 13.125 50.625 37.5 max 20 — — — 9 * tREFI DDR3-1066G 8-8-8 min 15 15 15 52.5 37.5 max 20 — — — 9 * tREFI ns ns ns ns ns ns ns ns ns ns ns ns ns 1)2)3)4)6) 4) 1)2)3)6) 1)2)3)4) 4) 1)2)3)4) 4) 1)2)3) Unit Note tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) Reserved Reserved 2.5 3.3 Reserved Reserved 2.5 3.3 Reserved 2.5 1.875 3.3 < 2.5 Reserved Reserved 1.875 < 2.5 Reserved Reserved Reserved Reserved 1.875 < 2.5 6, 8 5, 6 CL = 7 Reserved 1.875 < 2.5 CL = 8 Reserved 1.875 < 2.5 Reserved 1.875 < 2.5 Supported CL Settings Supported CWL Settings 5, 6, 7, 8 5, 6 6, 7, 8 5, 6 nCK nCK Rev. 0.2 / Dec. 2008 43 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C DDR3 1333 Speed Bin CL - nRCD - nRP Parameter Internal read command to first ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 5 CL = 6 CWL = 6 CWL = 7 CWL = 5 CL = 7 CWL = 6 CWL = 5 CWL = 6 CWL = 7 CL = 9 Symbol DDR3-1333F DDR3-1333J DDR3-1333G DDR3-1333H (optional) (optional) Unit 7-7-7 min 10.5 10.5 10.5 46.5 36 2.5 2.5 1.875 max 20 — — — 9* tREFI 3.3 3.3 < 2.5 8-8-8 min 12 12 12 48 36 2.5 2.5 max 20 — — — 9* tREFI 3.3 3.3 9-9-9 min 13.5 13.5 13.5 49.5 36 max 20 — — — 9* tREFI 10-10-10 min 15 15 15 51 36 max 20 — — — 9* tREFI ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1,2,3,4,7 4 1,2,3,7 1,2,3,4,7 4 4 1,2,3,4,7 4 1,2,3,7 1,2,3,4 4 1,2,3,4 4 1,2,3 5 Note tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) Reserved Reserved 2.5 3.3 Reserved Reserved Reserved 1.875 < 2.5 Reserved Reserved 2.5 3.3 Reserved Reserved Reserved Reserved Reserved 1.875 < 2.5 CWL = 6, 7 tCK(AVG) Reserved Reserved Reserved Reserved Reserved 1.875 < 2.5 Reserved Reserved 1.875 < 2.5 (Optional) Note 9.10 Reserved 1.875 < 2.5 CL = 8 tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) Reserved 1.875 1.5 < 2.5