HMT125R7BFR4C-G7

240pin DDR3 SDRAM Registered DIMM DDR3 SDRAM Registered DIMM Based on 1Gb B-die HMT112R7BFR8C HMT125R7BFR8C HMT125R7BFR4C HMT151R7BFR8C HMT151R7BFR4C *Hynix Semiconductor reserves the right to change products or specifications without notice Rev. 1.0 / Dec. 2009 1 Revision History Revision No. 0.01 0.02 0.03 0.1 0.2 0.3 1.0 History Initial Release Reflected the actual measurement, nonphysical change (max thichness) Added IDD Specification Updated IDD Specification and removed 8GB(4Rx4) RDIMM line-up Added FDHS usage option Added Environment Parameter JEDEC Update Draft Date Jan. 2009 Feb. 2009 Fev. 2009 Apr. 2009 May. 2009 Jul. 2009 Dec. 2009 Remark Preliminary Preliminary Preliminary Rev. 1.0 / Dec. 2009 2 Description Hynix Registered DDR3 SDRAM DIMMs (Registered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use Hynix DDR3 SDRAM devices. These Registered SDRAM DIMMs are intended for use as main memory when installed in systems such as servers and workstations. Features • • • • • • • • • • • • • Power Supply: VDD=1.5V (1.425V to 1.575V) VDDQ = 1.5V (1.425V to 1.575V) Backward Compatible with 1.5V DDR3 Memory Module VDDSPD=3.0V to 3.6V Functionality and operations comply with the DDR3L SDRAM datasheet 8 internal banks Data transfer rates: PC3L-10600, PC3L-8500 Bi-Directional Differential Data Strobe 8 bit pre-fetch Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop) Supports ECC error correction and detection On-Die Termination (ODT) Temperature sensor with integrated SPD * This product is in compliance with the RoHS directive. Ordering Information Part Number HMT112R7BFR8C-G7/H9 HMT125R7BFR8C-G7/H9 HMT125R7BFR4C-G7/H9 HMT151R7BFR4C-G7/H9 HMT151R7BFR8C-G7 Density 1GB 2GB 2GB 4GB 4GB Organization 128Mx72 256Mx72 256Mx72 512Mx72 512Mx72 Component Composition 128Mx8(H5TQ1G83BFR)*9 128Mx8(H5TQ1G83BFR)*18 256Mx4(H5TQ1G43BFR)*18 256Mx4(H5TQ1G43BFR)*36 128Mx8(H5TQ1G83BFR)*36 # of ranks 1 2 2 2 4 FDHS X X X O O * In order to uninstall FDHS, please contact sales administrator Rev. 1.0 / Dec. 2009 3 Key Parameters MT/s DDR3-1066 DDR3-1333 Grade -G7 -H9 tCK (ns) 1.875 1.5 CAS Latency (tCK) 7 9 tRCD (ns) 13.125 13.5 tRP (ns) 13.125 13.5 tRAS (ns) 37.5 36 tRC (ns) 50.625 49.5 CL-tRCD-tRP 7-7-7 9-9-9 Speed Grade Frequency [MHz] Grade CL6 -G7 -H9 800 800 CL7 1066 1066 CL8 1066 1066 1333 1333 CL9 CL10 Remark Address Table 1GB(1Rx8) Refresh Method Row Address Column Address Bank Address Page Size 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 2GB(2Rx8) 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 2GB(1Rx4) 8K/64ms A0-A13 A0-A9, A11 BA0-BA2 1KB 4GB(2Rx4) 8K/64ms A0-A13 A0-A9,A11 BA0-BA2 1KB 4GB(4Rx8) 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB Rev. 1.0 / Dec. 2009 4 Pin Descriptions Pin Name CK0 CK0 CK1 CK1 CKE[1:0] RAS Description Clock Input, positive line Clock Input, negative line Clock Input, positive line Clock Input, negative line Clock Enables Row Address Strobe Num ber 1 1 1 1 2 1 Pin Name ODT[1:0] DQ[63:0] CB[7:0] DQS[8:0] DQS[8:0] DM[8:0]/ DQS[17:9], TDQS[17:9] DQS[17:9], TDQS[17:9] EVENT TEST RESET VDD VSS VREFDQ VREFCA VTT VDDSPD Description On Die Termination Inputs Data Input/Output Data check bits Input/Output Data strobes Data strobes, negative line Data Masks / Data strobes, Termination data strobes Data strobes, negative line, Termination data strobes Reserved for optional hardware temperature sensing Memory bus test tool (Not Connected and Not Usable on DIMMs) Register and SDRAM control pin Power Supply Ground Reference Voltage for DQ Reference Voltage for CA Termination Voltage SPD Power Num ber 2 64 8 9 9 9 CAS WE S[3:0] A[9:0],A11, A[15:13] A10/AP A12/BC BA[2:0] SCL SDA SA[2:0] Par_In Err_Out Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Autoprecharge Address Input/Burst chop SDRAM Bank Addresses Serial Presence Detect (SPD) Clock Input SPD Data Input/Output SPD Address Inputs Parity bit for the Address and Control bus Parity error found on the Address and Control bus 1 1 4 14 1 1 3 1 1 3 1 1 9 1 1 1 22 59 1 1 4 1 Rev. 1.0 / Dec. 2009 5 Input/Output Functional Descriptions Symbol CK0 CK0 CK1 CK1 Type IN IN IN IN Polarity Positive Line Negative Line Positive Line Negative Line Active High Function Positive line of the differential pair of system clock inputs that drives input to the onDIMM Clock Driver. Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver. Terminated but not used on RDIMMs. Terminated but not used on RDIMMs. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank) Enables the command decoders for the associated rank of SDRAM when low and disables decoders when high. When decoders are disabled, new commands are ignored and previous operations continue. Other combinations of these input signals perform unique functions, including disabling all outputs (except CKE and ODT) of the register(s) on the DIMM or accessing internal control words in the register device(s). For modules with two registers, S[3:2] operate similarly to S[1:0] for the second set of register outputs or register control words. On-Die Termination control signals When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. Reference voltage for DQ0-DQ63 and CB0-CB7. Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In, ODT0 and ODT1. Selects which SDRAM bank of eight is activated. BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines mode register is to be accessed during an MRS cycle. Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8 identification of “’BL on the fly’’ during CAS command. The address inputs also provide the op-code during Mode Register Set commands. Data and Check Bit Input/Output pins Masks write data when high, issued concurrently with input data. Power and ground for the DDR SDRAM input buffers and core logic. Termination Voltage for Address/Command/Control/Clock nets. CKE[1:0] IN S[3:0] IN Active Low ODT[1:0] RAS, CAS, WE VREFDQ VREFCA IN IN Supply Supply Active High Active Low BA[2:0] IN — A[15:13, 12/BC,11, 10/AP,[9:0] IN — DQ[63:0], CB[7:0] DM[8:0] VDD, VSS VTT I/O IN Supply Supply — Active High Rev. 1.0 / Dec. 2009 6 Symbol DQS[17:0] DQS[17:0] Type I/O I/O Polarity Positive Edge Negative Edge Function Positive line of the differential data strobe for input and output data. Negative line of the differential data strobe for input and output data. TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1,DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. X4/X16 DRAMs must disable the TDQS function via mode register A11=0 in MR1 TDQS[17:9] TDQS[17:9] OUT SA[2:0] IN — These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pullup. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDDSPD on the system planar to act as a pullup. SDA I/O — SCL IN OUT (open drain) Supply IN IN OUT (open drain) — EVENT This signal indicates that a thermal event has been detected in the thermal sensing device.The system should guarantee the electrical level requirement is met for the Active Low EVENT pin on TS/SPD part. No pull-up resister is provided on DIMM. Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation. The RESET pin is connected to the RESET pin on the register and to the RESET pin on the DRAM. Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even) Parity error detected on the Address and Control bus. A resistor may be connected from Err_Out bus line to VDD on the system planar to act as a pull up. Used by memory bus analysis tools (unused (NC) on memory DIMMs) VDDSPD RESET Par_In Err_Out TEST Rev. 1.0 / Dec. 2009 7 Pin Assignments Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Front Side (left 1–60) VREFDQ VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 Pin # 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 Back Side (right 121–180) VSS DQ4 DQ5 VSS DM0,DQS9, TDQS9 NC,DQS9, TDQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1,DQS10, TDQS10 NC,DQS10, TDQS10 VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2,DQS11, TDQS11 NC,DQS11, TDQS11 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS Pin # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Front Side (left 61–120) A2 VDD NC, CK1 NC, CK1 VDD VDD VREFCA Par_In, NC VDD A10 / AP BA0 VDD WE CAS VDD S1, NC ODT1, NC VDD S2, NC VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 Pin # 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 Back Side (right 181–240) A1 VDD VDD CK0 CK0 VDD EVENT, NC A0 VDD BA1 VDD RAS S0 VDD ODT0 A13 VDD S3, NC VSS DQ36 DQ37 VSS DM4,DQS13, TDQS13 NC,DQS13, TDQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS NC = No Connect; RFU = Reserved Future Use Rev. 1.0 / Dec. 2009 8 Pin # 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Front Side (left 1–60) VSS DQS3 DQS3 VSS DQ26 DQ27 VSS CB0, NC CB1, NC VSS DQS8 DQS8 VSS CB2, NC CB3, NC VSS VTT, NC KEY Pin # 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back Side (right 121–180) DM3,DQS12, TDQS12 NC,DQS12, TDQS12 VSS DQ30 DQ31 VSS CB4, NC CB5, NC VSS NC,DM8,DQS17, TDQS17 NC,DQS17, TDQS17 VSS CB6, NC CB7, NC VSS NC(TEST) RESET KEY Pin # 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Front Side (left 61–120) VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SA0 SCL SA2 VTT Pin # 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Back Side (right 181–240) DM5,DQS14, TDQS14 NC,DQS14, TDQS14 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6,DQS15, TDQS15 NC,DQS15, TDQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7,DQS16, TDQS16 NC,DQS16, TDQS16 VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT 49 50 51 52 53 54 55 56 57 58 59 60 VTT, NC CKE0 VDD BA2 Err_Out, NC VDD A11 A7 VDD A5 A4 VDD 169 170 171 172 173 174 175 176 177 178 179 180 CKE1, NC VDD A15 A14 VDD A12 / BC A9 VDD A8 A6 VDD A3 NC = No Connect; RFU = Reserved Future Use Rev. 1.0 / Dec. 2009 9 Registering Clock Driver Specifications Capacitance Values Symbol Parameter Input capacitance, Data inputs CI Input capacitance, CK, CK, FBIN, FBIN Input capacitance, CK, CK, FBIN, FBIN (DDR3-1600) CIR Input capacitance, RESET, MIRROR, QCSEN VI = VDD or GND; VDD = 1.5v Conditions Min 1.5 2 1.5 Typ Max 2.5 3 2.5 3 Unit pF pF pF pF Input & Output Timing Requirements DDR3-800 1066/1333 Min fclock fTEST tSU tH tPDM tDIS tEN Input clock frequency Input clock frequency Setup time Hold time Propagation delay, singlebit switching Output disable time (1/2Clock prelaunch) Output enable time (1/2Clock prelaunch) Application frequency Test frequency Input valid before CK/CK Input to remain valid after CK/CK CK/CK to output Yn/Yn to output float Output driving to Yn/Yn 300 70 100 175 0.65 0.5 tCK + tQSK1(min) 0.5 tCK tQSK1(max) Max 670 300 1.0 Mhz Mhz ps ps ns ps ps Symbol Parameter Conditions Unit Rev. 1.0 / Dec. 2009 10 On DIMM Thermal Sensor The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal sensor comply with JEDEC “TSE2002av, Serial Presence Detect with Temperature Sensor”. Connection of Thermal Sensor EVENT SCL SDA SA0 SA1 SA2 SA0 SPD with SA1 Integrated SA2 TS EVENT SCL SDA Temperature-to-Digital Conversion Performance Parameter Condition Active Range, 75°C < TA < 95°C Temperature Sensor Accuracy (Grade B) Monitor Range, 40°C < TA < 125°C -20°C < TA < 125°C Min Typ ± 0.5 ± 1.0 ± 2.0 Max ± 1.0 ± 2.0 ± 3.0 Unit °C °C °C °C Resolution 0.25 Rev. 1.0 / Dec. 2009 11 Functional Block Diagram A[N:O]A /BA[N:O]A A[N:O]B /BA[N:O]B ZQ 1GB, 128Mx72 Module(1Rank of x8) RODT0A RS0B RRASB RS0A RRASA RODT0B ODT ODT PCK0A RCKE0A PCK0B RCKE0B CK CKE CK CKE RCASA RCASB PCK0A PCK0B RWEA RWEB A[N:O]/BA[N:O] D8 ODT CK CKE WE CK D4 WE CK A[O:N]/BA[N:O] D3 ODT CK CKE WE CK D5 WE CK RAS CAS CS A[O:N]/BA[N:O] D2 ODT CK CKE WE CK D6 ODT CK CKE WE CK RAS CAS CS A[N:O]/BA[N:O] D1 ODT CK CKE WE CK D7 ODT CK CKE WE CK A[N:O]/BA[N:O] DQS1 DQS1 DM1/DQS10 DQS10 DQ[15:8] DQS DQS TDQS TDQS DQ [7:0] RAS CAS CS ZQ DQS7 DQS7 DM7/DQS16 DQS16 DQ[63:56] DQS DQS TDQS TDQS DQ [7:0] RAS CAS CS A[O:N]/BA[N:O] ZQ DQS2 DQS2 DM2/DQS11 DQS11 DQ[23:16] DQS DQS TDQS TDQS DQ [7:0] ZQ DQS6 DQS6 DM6/DQS15 DQS15 DQ[55:48] DQS DQS TDQS TDQS DQ [7:0] RAS CAS CS A[O:N]/BA[N:O] ZQ DQS3 DQS3 DM3/DQS12 DQS12 DQ[31:24] DQS DQS TDQS TDQS DQ [7:0] ZQ DQS5 DQS5 DM5/DQS14 DQS14 DQ[47:40] DQS DQS TDQS TDQS DQ [7:0] RAS CAS CS A[O:N]/BA[O:N] ZQ DQS8 DQS8 DM8/DQS17 DQS17 CB[7:0] DQS DQS TDQS TDQS DQ [7:0] RAS CAS CS ZQ DQS4 DQS4 DM4/DQS13 DQS13 DQ[39:32] DQS DQS TDQS TDQS DQ [7:0] RAS CAS CS VDDSPD VDD VTT VREFCA VREFDQ VSS SPD D0–D8 D0–D8 D0–D8 D0–D8 D0 ODT CK CKE WE CK A[N:O]/BA[N:O] DQS0 DQS0 DM0/DQS9 DQS9 DQ[7:0] DQS DQS TDQS TDQS DQ [7:0] RAS CAS CS ZQ Vtt Note: 1.DQ-to-I/O wiring may be changed within byte. 2.ZQ resistors are 240Ω ± 1%.For all other resistor values refer to the appropriate wiring diagram. Vtt S0 S1 BA[N:0] A[N:0] RAS CAS WE CKE0 ODT0 CK0 CK0 CK0 CK0 PAR_IN 120Ω ± 1% 120Ω ± 1% 1: 2 R E G I S T E R / P L L OERR RST RS0A → CS0: SDRAMs D[3:0], D8 RS0B → CS0: SDRAMs D[7:4] RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D8 RBA[N:0]A → BA[N:0]: SDRAMs D[7:4] RA[N:0]A → A[N:0]: SDRAMs D[3:0], D8 RA[N:0]A → A[N:0]: SDRAMs D[7:4] RRASA → RAS: SDRAMs D[3:0], D8 RRASA → RAS: SDRAMs D[7:4] RCASA → CAS: SDRAMs D[3:0], D8 RCASA → CAS: SDRAMs D[7:4] RWEA → WE: SDRAMs D[3:0], D8 RWEA → WE: SDRAMs D[7:4] RCKE0A → CKE0: SDRAMs D[3:0], D8 RCKE0B → CKE0: SDRAMs D[7:4] RODT0A → ODT0: SDRAMs D[3:0], D8 RODT0B → ODT0: SDRAMs D[7:4] PCK0A → CK: SDRAMs D[3:0], D8 PCK0B → CK: SDRAMs D[7:4] PCK0A → CK: SDRAMs D[3:0], D8 PCK0B → CK: SDRAMs D[7:4] Err_Out VDDSPD EVENT SCL SDA VDDSPD SA0 SA0 SA1 SA2 VSS EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative RST: SDRAMs D[8:0] S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 330Ω resistor to ground RESET Rev. 1.0 / Dec. 2009 12 2GB, 256Mx72 Module(2Rank of x8) - page1 A[N:O]A /BA[N:O]A RODT1A A[N:O]B /BA[N:O]B RODT0A RODT0B PCK0A RCKE0A PCK0B RCKE0B RODT1B A[O:N]/BA[N:O] ODT A[N:O]/BA[N:O] ODT A[N:O]/BA[N:O] ODT A[N:O]/BA[N:O] ODT PCK1A RCKE1A RS1A A[N:O]/BA[N:O] D8 ODT CAS CK CKE WE CK A[N:O]/BA[N:O] D17 ODT CAS CK CKE WE CK D4 ODT CAS CK CKE WE CK A[N:O]/BA[N:O] DQS8 DQS8 DM8/DQS17 DQS17 CB[7:0] DQS DQS TDQS TDQS DQ [7:0] RAS DQS DQS TDQS TDQS DQ [7:0] RAS DQS4 DQS4 DM4/DQS13 DQS13 DQ[39:32] DQS DQS TDQS TDQS DQ [7:0] RAS DQS DQS TDQS TDQS DQ [7:0] RAS CAS WE WE WE WE RS1B D13 CK CKE CK CKE CK CKE CK CKE CK CK CK CK ZQ CS ZQ CS ZQ CS ZQ CS A[N:O]/BA[N:O] D3 ODT CK CKE CAS WE CK A[N:O]/BA[N:O] D12 ODT CAS CK CKE WE CK D5 ODT CK CKE CAS WE CK A[N:O]/BA[N:O] DQS3 DQS3 DM3/DQS12 DQS12 DQ[31:24] DQS DQS TDQS TDQS DQ [7:0] RAS DQS DQS TDQS TDQS DQ [7:0] RAS DQS5 DQS5 DM5/DQS14 DQS14 DQ[47:40] DQS DQS TDQS TDQS DQ [7:0] RAS DQS DQS TDQS TDQS DQ [7:0] RAS CAS D14 ZQ CS ZQ CS ZQ CS ZQ CS A[N:O]/BA[N:O] D2 ODT CAS CK CKE WE CK A[N:O]/BA[N:O] D11 ODT CK CKE CAS WE CK D6 ODT CAS CK CKE WE CK A[N:O]/BA[N:O] DQS2 DQS2 DM2/DQS11 DQS11 DQ[23:16] DQS DQS TDQS TDQS DQ [7:0] RAS DQS DQS TDQS TDQS DQ [7:0] RAS DQS6 DQS6 DM6/DQS15 DQS15 DQ55:48] DQS DQS TDQS TDQS DQ [7:0] RAS DQS DQS TDQS TDQS DQ [7:0] RAS CAS D15 ZQ CS ZQ CS ZQ CS ZQ CS A[O:N]/BA[N:O] D1 ODT CAS CK CKE WE CK A[O:N]/BA[N:O] D10 ODT CAS CK CKE WE CK D7 ODT CAS CK CKE WE CK A[N:O]/BA[N:O] DQS1 DQS1 DM1/DQS10 DQS10 DQ[15:8] DQS DQS TDQS TDQS DQ [7:0] RAS DQS DQS TDQS TDQS DQ [7:0] RAS DQS7 DQS7 DM7/DQS16 DQS16 DQ[63:56] DQS DQS TDQS TDQS DQ [7:0] RAS DQS DQS TDQS TDQS DQ [7:0] RAS CAS D16 ZQ CS ZQ CS ZQ CS ZQ CS A[N:O]/BA[N:O] D0 ODT CAS CK CKE WE CK D9 ODT CK CKE CAS WE CK RAS RAS ZQ CS ZQ CS A[N:O]/BA[N:O] DQS0 DQS0 DM0/DQS9 DQS9 DQ[7:0] DQS DQS TDQS TDQS DQ [7:0] DQS DQS TDQS TDQS DQ [7:0] Vtt VDDSPD EVENT Vtt VDDSPD SA0 SCL SDA EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA Note: 1. DQ-to-I/O wiring may be changed within a byte. 2. Unless otherwise noted, resistor values are 15Ω ± 5%. 3. ZQ resistors are 240Ω ± 1%. For all other resistor values refer to the appropriate wiring diagram. 4. See the wiring diagrams for all resistors associated with the command, address and control bus. Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative VDDSPD VDD VTT VREFCA VREFDQ VSS Serial PD D0–D17 D0–D17 D0–D17 D0–D17 D0–D17 Rev. 1.0 / Dec. 2009 PCK1B RCKE1B RCASA RS0A RRASA RS0B RRASB RCASB PCK0A PCK1A PCK0B RWEA RWEB PCK1B SA0 SA1 SA2 VSS 13 2GB, 256Mx72 Module(2Rank of x8) - page2 S0 S1 S[3:2] NC BA[N:0] A[N:0] RAS CAS WE CKE0 CKE1 ODT0 ODT1 CK0 120Ω ± 5% CK0 CK1 CK1 PAR_IN RESET 1:2 R E G I S T E R / P L L RS0A → CS0: SDRAMs D[3:0], D8 RS0B → CS0: SDRAMs D[7:4] RS1A → CS1: SDRAMs D[12:9], D17 RS1B → CS1: SDRAMs D[16:13] RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D17 RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13] RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D17 RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13] RRASA → RAS: SDRAMs D[3:0], D[12:8], D17 RRASB → RAS: SDRAMs D[7:4], D[16:13] RCASA → CAS: SDRAMs D[3:0], D[12:8], D17 RCASB → CAS: SDRAMs D[7:4], D[16:13] RWEA → WE: SDRAMs D[3:0], D[12:8], D17 RWEB → WE: SDRAMs D[7:4], D[16:13] RCKE0A → CKE0: SDRAMs D[3:0], D8 RCKE0B → CKE0: SDRAMs D[7:4] RCKE1A → CKE1: SDRAMs D[12:9], D17 RCKE1B → CKE1: SDRAMs D[16:13] RODT0A → ODT0: SDRAMs D[3:0], D8 RODT0B → ODT0: SDRAMs D[7:4] RODT1A → ODT1: SDRAMs D[12:9], D17 RODT1A → ODT1: SDRAMs D[16:13] PCK0A → CK: SDRAMs D[3:0], D8 PCK0B → CK: SDRAMs D[7:4] PCK1A → CK: SDRAMs D[12:9], D17 PCK1B → CK: SDRAMs D[16:13] PCK0A → CK: SDRAMs D[3:0], D8 PCK0B → CK: SDRAMs D[7:4] PCK1A → CK: SDRAMs D[12:9], D17 PCK1B → CK: SDRAMs D[16:13] 120Ω ± 5% OERR Err_Out RST RST: SDRAMs D[17:0] * S[3:2], CK1 and CK1 are NC Rev. 1.0 / Dec. 2009 14 2GB, 256Mx72 Module(1Rank of x4) - page1 A[O:N]A /BA[O:N]A A[O:N]/BA[O:N] A[O:N]/BA[O:N] A[O:N]/BA[O:N] D8 ODT CAS CK CKE WE CK D17 ODT CK CKE WE CK D4 ODT CAS CK CKE WE CK D13 ODT ODT ODT ODT CAS CK CKE WE CK A[O:N]/BA[O:N] ZQ VSS VSS VSS RAS RAS RAS A[O:N]/BA[O:N] A[O:N]/BA[O:N] A[O:N]/BA[O:N] D3 ODT CAS CK CKE WE CK D12 ODT CAS CK CKE WE CK D5 ODT CK CKE WE CK D14 CK CKE WE CK A[O:N]/BA[O:N] ZQ VSS VSS VSS RAS RAS RAS RAS CAS A[O:N]/BA[O:N] A[O:N]/BA[O:N] A[O:N]/BA[O:N] D2 ODT CK CKE CAS WE CK D11 ODT CK CKE CAS WE CK D6 ODT CK CKE WE CK D15 CK CKE WE CK A[O:N]/BA[O:N] ZQ VSS VSS VSS RAS RAS RAS RAS CAS A[O:N]/BA[O:N] A[O:N]/BA[O:N] A[O:N]/BA[O:N] D1 ODT CAS CK CKE WE CK D10 ODT CAS CK CKE WE CK D7 ODT CK CKE WE CK D16 CK CKE WE CK A[O:N]/BA[O:N] VSS VSS VSS RAS RAS RAS RAS CAS A[O:N]/BA[O:N] D0 ODT CAS CK CKE WE CK D9 ODT CAS CK CKE WE CK A[O:N]/BA[O:N] VSS RAS Vtt VDDSPD EVENT SCL SDA VDDSPD RAS CS CS SA0 SA0 SA1 SA2 VSS VSS DQS0 DQS0 VSS DQ[3:0] DQS DQS DM DQ [3:0] ZQ DQS9 DQS9 VSS DQ[7:4] DQS DQS DM DQ [3:0] ZQ Vtt EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative VDDSPD VDD VTT VREFCA VREFDQ VSS SPD D0–D17 D0–D17 D0–D17 D0–D17 D0–D17 Note: 1. DQ-to-I/O wiring may be changed within a nibble. 2. Unless otherwise noted, resistor values are 15%.± 5 Ω 3. See the wiring diagrams for all resistors associated with the command, address and control bus. Ω ±1 4. ZQ resistors are 240%. For all other resistor values refer to the appropriate wiring diagram. Rev. 1.0 / Dec. 2009 CAS CS CS CS CS VSS DQS1 DQS1 VSS DQ[11;8] DQS DQS DM DQ [3:0] ZQ DQS10 DQS10 VSS DQ[15:12] DQS DQS DM DQ [3:0] ZQ DQS7 DQS7 VSS DQ[59:56] DQS DQS DM DQ [3:0] ZQ DQS16 DQS16 VSS DQ[63:60] DQS DQS DM DQ [3:0] CAS CS CS CS CS VSS DQS2 DQS2 VSS DQ[19:16] DQS DQS DM DQ [3:0] ZQ DQS11 DQS11 VSS DQ23:20] DQS DQS DM DQ [3:0] ZQ DQS6 DQS6 VSS DQ[51:48] DQS DQS DM DQ [3:0] ZQ DQS15 DQS15 VSS DQ[55;52] DQS DQS DM DQ [3:0] CAS CS CS CS CS VSS DQS3 DQS3 VSS DQ[27:24] DQS DQS DM DQ [3:0] ZQ DQS12 DQS12 VSS DQ[31:28] DQS DQS DM DQ [3:0] ZQ DQS5 DQS5 VSS DQ[43:40] DQS DQS DM DQ [3:0] ZQ DQS14 DQS14 VSS DQ[47:44] DQS DQS DM DQ [3:0] RAS CAS CS CS CS CS VSS DQS8 DQS8 VSS CB[3:0] DQS DQS DM DQ [3:0] ZQ DQS17 DQS17 VSS CB[7:4] DQS DQS DM DQ [3:0] ZQ DQS4 DQS4 VSS DQ[35:32] DQS DQS DM DQ [3:0] ZQ A[O:N]B /BA[O:N]B RODT0A RS0A RRASA RS0B RRASB RODT0B PCK0A RCKE0A PCK0B RCKE0B RCASA RCASB PCK0A PCK0B RWEA RWEB DQS13 DQS13 VSS DQ[39:36] DQS DQS DM DQ [3:0] ZQ 15 2GB, 256Mx72 Module(1Rank of x4) - page2 S0 S1 BA[N:0] A[N:0] RAS CAS WE CKE0 ODT0 CK0 RS0A → CS0: SDRAMs D[3:0], D[12:8], D17 RS0B → CS0: SDRAMs D[7:4], D[16:13] RS1A → CS1: SDRAMs D[12:9], D17 RS1B → CS1: SDRAMs D[16:13] RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D17 RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13] RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D17 RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13] RRASA → RAS: SDRAMs D[3:0], D[12:8], D17 RRASB → RAS: SDRAMs D[7:4], D[16:13] RCASA → CAS: SDRAMs D[3:0], D[12:8], D17 RCASB → CAS: SDRAMs D[7:4], D[16:13] RWEA → WE: SDRAMs D[3:0], D[12:8], D17 RWEB → WE: SDRAMs D[7:4], D[16:13] RCKE0A → CKE0: SDRAMs D[3:0], D[12:8], D17 RCKE0B → CKE0: SDRAMs D[7:4], D[16:13] RODT0A → ODT0: SDRAMs D[3:0], D[12:8]. D17 RODT0B → ODT0: SDRAMs D[7:4], D[16:13] PCK0A → CK: SDRAMs D[3:0], D8 PCK0B → CK: SDRAMs D[7:4] PCK0A → CK: SDRAMs D[3:0], D8 PCK0B → CK: SDRAMs D[7:4] OERR Err_Out RESET RST RST: SDRAMs D[17:0] 1:2 R E G I S T E R / P L L CK0 PAR_IN * S[3:2], CKE1, ODT1, CK1 and CK1 are NC (Unused register inputs ODT1 and CKE1 have a 330Ω resistor to ground.) Rev. 1.0 / Dec. 2009 16 DQS10 DQS10 VSS DQ[15:12] DQS11 DQS11 VSS DQ[23:20] DQS12 DQS12 VSS DQ[31:28] DQS17 DQS17 VSS CB[7:4] DQS0 DQS0 VSS DQ[3:0] Vtt CS CS RAS CAS RAS CAS CAS CAS CAS RAS RAS RAS DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] CS CS CS RS0A RRASA RCASA RWEA PCK0A PCK0A RCKE0A RODT0A A[O:N]A /BA[O:N]A WE WE WE WE WE D0 CK CK CK CKE ODT A[N:O]/BA[N:O] CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT CK CKE CK CKE CK CK Rev. 1.0 / Dec. 2009 D10 D11 D12 D17 CK CK CKE ODT A[N:O]/BA[N:O] CS CS RAS CAS WE RAS CAS WE WE WE WE CAS CAS CAS RAS RAS RAS DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] CS CS CS RS1A D18 CK CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT CK CKE CK CKE CK CK D28 D29 D30 D35 CK CK CKE ODT A[N:O]/BA[N:O] CK CK CKE ODT PCK1A PCK1A RCKE1A R0DT1A A[N:O]/BA[N:O] DQS2 DQS2 VSS DQ[19:16] DQS3 DQS3 VSS DQ[27:24] DQS8 DQS8 VSS CB[3:0] DQS1 DQS1 VSS DQ[11:8] DQS9 DQS9 VSS DQ[7:4] 4GB, 512Mx72 Module(2Rank of x4) - page1 Vtt CS RAS CAS WE WE WE CAS CAS RAS RAS CS CS DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] CS RAS CAS WE CK CK CKE ODT CS RAS CAS WE DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] RS0A RRASA RCASA RWEA D9 CK CK CKE ODT A[N:O]/BA[N:O] ODT CK CKE CK CS RAS CAS WE CK CK CKE ODT A[N:O]/BA[N:O] CS RAS CAS WE DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] D1 D2 D3 D8 CK CK CKE ODT A[N:O]/BA[N:O] CK CK CKE ODT A[N:O]/BA[N:O] PCK0A PCK0A RCKE0A RODT0A A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[O:N]A /BA[O:N]A CS RAS CAS WE CS RAS CAS WE CS RAS CAS WE DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] RS1A D27 D19 D20 D21 D26 CK CK CKE ODT A[N:O]/BA[N:O] CK CK CKE ODT CK CK CKE ODT A[N:O]/BA[N:O] CK CK CKE ODT A[N:O]/BA[N:O] PCK1A PCK1A RCKE1A R0DT1A A[N:O]/BA[N:O] 17 4GB, 512Mx72 Module(2Rank of x4) - page2 A[N:O]B /BA[N:O]B RODT0B A[N:O]B /BA[N:O]B RODT0B PCK0B RCKE0B PCK0B RCKE0B R0DT1B RCKE1B RS0B RRASB RS0B RRASB RCASB PCK1B PCK1B PCK1B A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] D14 ODT CAS CK CKE WE CK D32 ODT CK CKE WE CK D13 ODT CAS CK CKE WE CK D31 ODT ODT ODT ODT CAS CK CKE CK CKE CK CKE CK CKE WE CK A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] D4 ODT CAS CK CKE WE CK D22 ODT CAS CK CKE WE CK D5 ODT CK CKE WE CK D23 WE CK A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] D16 ODT CK CKE CAS WE CK D34 ODT CK CKE CAS WE CK D15 ODT CK CKE WE CK D33 WE CK A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] D7 ODT CAS CK CKE WE CK D25 ODT CAS CK CKE WE CK D6 ODT CK CKE WE CK D24 WE CK Vtt Vtt VDDSPD VDD VTT VREFCA VREFDQ VSS SPD D0–D35 D0–D35 D0–D35 D0–D35 D0–D35 VDDSPD EVENT SCL SDA VDDSPD SA0 SA0 SA1 SA2 VSS EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative Note: 1. DQ-to-I/O wiring may be changed within a nibble. 2. See wiring diagrams for all resistors values. 3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms. Rev. 1.0 / Dec. 2009 A[N:O]/BA[N:O] DQS7 DQS7 VSS DQ[59:56] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS6 DQS6 VSS DQ[51:48] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] RAS RAS RAS RAS CAS CAS CS CS CS CS A[N:O]/BA[N:O] DQS16 DQS16 VSS DQ[63:60] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS15 DQS15 VSS DQ[55:52] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] RAS RAS RAS RAS CAS CAS CS CS CS CS A[N:O]/BA[N:O] DQS4 DQS4 VSS DQ[35:32] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS5 DQS5 VSS DQ[43:40] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] RAS RAS RAS RAS CAS CAS CS CS CS CS A[N:O]/BA[N:O] DQS14 DQS14 VSS DQ[47:44] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] RS1B DQS13 DQS13 VSS DQ[39:36] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] RAS RAS RAS RAS CAS CS CS CS CS PCK1B RS1B R0DT1B RCKE1B RCASB PCK0B RWEB PCK0B RWEB 18 4GB, 512Mx72 Module(2Rank of x4) - page3 S0 S1 BA[N:0] A[N:0] RAS CAS WE CKE0 CKE1 ODT0 ODT1 CK0 1:2 R E G I S T E R / P L L RS0A → CS0: SDRAMs D[3:0], D[12:8], D17 RS0B → CS0: SDRAMs D[7:4], D[16:13] RS1A → CS1: SDRAMs D[21:18], D[30:26], D35 RS1B → CS1: SDRAMs D[25:22], D[34:31] RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RRASA → RAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RRASB → RAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RCASA → CAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RCASB → CAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RWEA → WE: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RWEB → WE: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RCKE0A → CKE0: SDRAMs D[3:0], D[12:8], D17 RCKE0B → CKE0: SDRAMs D[7:4], D[16:13] RCKE1A → CKE1: SDRAMs D[21:18], D[30:26], D35 RCKE1B → CKE1: SDRAMs D[25:22], D[34:31] RODT0A → ODT0: SDRAMs D[3:0], D[12:8], D17 RODT0B → ODT0: SDRAMs D[7:4], D[16:13] RODT1A → ODT1: SDRAMs D[21:18], D[30:26], D35 RODT1A → ODT1: SDRAMs D[25:22], D[34:31] PCK0A → CK: SDRAMs D[3:0], D[12:8], D17 PCK0B → CK: SDRAMs D[7:4], D[16:13] PCK1A → CK: SDRAMs D[21:18], D[30:26], D35 PCK1B → CK: SDRAMs D[25:22], D[34:31] PCK0A → CK: SDRAMs D[3:0], D[12:8], D17 PCK0B → CK: SDRAMs D[7:4], D[16:13] PCK1A → CK: SDRAMs D[21:18], D[30:26], D35 PCK1B → CK: SDRAMs D[25:22], D[34:31] CK0 CK1 CK1 PAR_IN RESET RST 120Ω ± 5% Err_Out RST: SDRAMs D[35:0] * S[3:2], CK1 and CK1 are NC Rev. 1.0 / Dec. 2009 19 DQS0 DQS0 DM0/TDQS9 TDQS9 DQ[7:0] DQS8 DQS8 DM8/TDQS17 TDQS17 CB[7:0] DQS3 DQS3 DM3/TDQS12 TDQS12 DQ[31:24] DQS2 DQS2 DM2/TDQS11 TDQS11 DQ[32:16] DQS1 DQS1 DM1/TDQS10 TDQS10 DQ[15:8] Vtt CS CS CS CS CS CS0 WRAS WCAS WWE PCK0 PCK0 WCKE0 WODT0 WA[N:0] WBA[N:0] DQS DQS TDQS TDQS DQ [7:0] ZQ RAS CAS WE CK CK CK CK CK WE WE WE WE CAS CAS CAS CAS RAS RAS RAS RAS DQS DQS TDQS TDQS DQ [7:0] ZQ DQS DQS TDQS TDQS DQ [7:0] ZQ DQS DQS TDQS TDQS DQ [7:0] ZQ DQS DQS TDQS TDQS DQ [7:0] ZQ Rev. 1.0 / Dec. 2009 4GB, 512Mx72 Module(4Rank of x8) - page1 U6 CK CKE ODT A[N:O] BA[N:O] BA[N:O] BA[N:O] BA[N:O] BA[N:O] A[N:O] A[N:O] A[N:O] A[N:O] ODT ODT ODT ODT CKE CKE CKE CKE CK CK CK CK CS RAS CAS WE CK CK CK CK WE WE WE CAS CAS CAS RAS RAS RAS CS CS CS CS RAS CAS WE CK U5 CS1 U4 U3 U2 DQS DQS TDQS TDQS DQ [7:0] ZQ DQS DQS TDQS TDQS DQ [7:0] ZQ DQS DQS TDQS TDQS DQ [7:0] ZQ DQS DQS TDQS TDQS DQ [7:0] ZQ DQS DQS TDQS TDQS DQ [7:0] ZQ PCK0 U15 CK CKE ODT A[N:O] BA[N:O] BA[N:O] BA[N:O] BA[N:O] A[N:O] A[N:O] A[N:O] ODT ODT ODT CKE CKE CKE CK CK CK CS RAS CAS WE CK CK CK WE WE CAS CAS RAS RAS CS CS CS RAS CAS WE CK U14 U13 U12 U11 CK CKE ODT A[N:O] BA[N:O] PCK0 WCKE01 VDD CS RAS CAS WE CK DQS DQS TDQS TDQS DQ [7:0] ZQ DQS DQS TDQS TDQS DQ [7:0] ZQ DQS DQS TDQS TDQS DQ [7:0] ZQ DQS DQS TDQS TDQS DQ [7:0] ZQ DQS DQS TDQS TDQS DQ [7:0] ZQ CS2 PCK2 U24 CK CKE ODT A[N:O] BA[N:O] BA[N:O] BA[N:O] A[N:O] A[N:O] ODT ODT CKE CKE CK CK CS RAS CAS WE CK CK WE CAS RAS CS CS RAS CAS WE CK U23 U22 U21 U20 CK CKE ODT A[N:O] BA[N:O] CK CKE ODT A[N:O] BA[N:O] PCK2 WCKE0 WODT1 CS RAS CAS WE CK CS RAS CAS WE CK DQS DQS TDQS TDQS DQ [7:0] ZQ DQS DQS TDQS TDQS DQ [7:0] ZQ DQS DQS TDQS TDQS DQ [7:0] ZQ DQS DQS TDQS TDQS DQ [7:0] ZQ DQS DQS TDQS TDQS DQ [7:0] ZQ CS3 PCK2 U33 CK CKE ODT A[N:O] BA[N:O] A[N:O] BA[N:O] ODT CKE CK U32 U31 U30 U29 CK CKE ODT A[N:O] BA[N:O] CK CKE ODT A[N:O] BA[N:O] CK CKE ODT A[N:O] BA[N:O] PCK2 WCKE1 VDD 20 4GB, 512Mx72 Module(4Rank of x8) - page2 WBA[N:0] WA[N:0] WODT0 WCKE01 WODT1 WCKE0 WCKE0 WCKE1 WRAS WCAS WWE PCK0 PCK0 PCK2 PCK0 PCK0 PCK2 PCK2 VDD PCK2 CS0 CS1 CS2 A[N:O] A[N:O] A[N:O] CS3 VDD A[N:O] A[N:O] A[N:O] A[N:O] ODT ODT BA[N:O] BA[N:O] BA[N:O] ODT BA[N:O] ODT CK CK CK CK CK CK CK CK CK CK BA[N:O] BA[N:O] BA[N:O] CKE CKE CKE CK CK CK CK ODT ODT ODT RAS RAS RAS DQS4 DQS4 DM4/TDQS13 TDQS13 DQ[39:32] DQS DQS TDQS TDQS DQ [7:0] ZQ U7 DQS DQS TDQS TDQS DQ [7:0] ZQ U16 DQS DQS TDQS TDQS DQ [7:0] ZQ U25 DQS DQS TDQS TDQS DQ [7:0] ZQ RAS U34 BA[N:O] BA[N:O] BA[N:O] CK CK CK CK CK A[N:O] A[N:O] CK A[N:O] CKE CKE CKE ODT ODT ODT RAS RAS RAS DQS5 DQS5 DM5/TDQS14 TDQS14 DQ[47:40] DQS DQS TDQS TDQS DQ [7:0] ZQ U8 DQS DQS TDQS TDQS DQ [7:0] ZQ U17 DQS DQS TDQS TDQS DQ [7:0] ZQ U26 DQS DQS TDQS TDQS DQ [7:0] ZQ RAS U35 CKE CKE CKE ODT ODT ODT RAS RAS RAS A[N:O] A[N:O] BA[N:O] BA[N:O] A[N:O] DQS6 DQS6 DM6/TDQS15 TDQS15 DQ[55:48] DQS DQS TDQS TDQS DQ [7:0] ZQ U9 DQS DQS TDQS TDQS DQ [7:0] ZQ U18 DQS DQS TDQS TDQS DQ [7:0] ZQ BA[N:O] U27 DQS DQS TDQS TDQS DQ [7:0] ZQ RAS U36 CKE CKE CKE ODT ODT ODT CAS CAS CAS RAS RAS RAS A[N:O] A[N:O] BA[N:O] BA[N:O] A[N:O] DQS3 DQS3 DM3/TDQS12 TDQS12 DQ[31:24] DQS DQS TDQS TDQS DQ [7:0] ZQ U10 DQS DQS TDQS TDQS DQ [7:0] ZQ U19 DQS DQS TDQS TDQS DQ [7:0] ZQ BA[N:O] U28 DQS DQS TDQS TDQS DQ [7:0] ZQ RAS CAS U37 Vtt VDDSPD EVENT SCL SDA VDDSPD SA0 SA0 SA1 SA2 VSS EVENT SPD with SA1 Integrated SA2 SCL TS SDA VSS Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative VDDSPD CKE WE WE WE WE CS CS CS CK CK CK CK CK CK CS CKE WE WE WE CAS CAS CAS CAS WE CS CS CS CK CK CK CK CK CK CS CKE WE WE WE CAS CAS CAS CAS WE CS CS CS CS CKE WE WE WE CAS CAS CAS CAS WE CS CS CS CS Serial PD U1–U37 Notes: 1. DQ-to-I/O wiring may be changed within a byte. 2. See wiring diagrams for resistor values. 3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms. VDD VTT VREFCA VREFDQ VSS U1-U37 U1-U37 U1-U37 Rev. 1.0 / Dec. 2009 21 4GB, 512Mx72 Module(4Rank of x8) - page3 S0 S1 S2 S3 BA[N:0] A[N:0] RAS CAS WE CKE0 CKE1 ODT0 ODT1 CK0 1:2 R E G I S T E R / P L L CK0 CK1 CK1 PAR_IN RESET RST 120Ω ± 5% CS0 → CS0: SDRAMs U[10:2] CS1 → CS1: SDRAMs U[19:11] CS2 → CS2: SDRAMs U[28:20] CS3 → CS3: SDRAMs U[37:29] WBA[N:0] → BA[N:0]: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29] EBA[N:0] → BA[N:0]: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34] WA[N:0] → A[N:0]: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29] EA[N:0] → A[N:0]: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34] WRAS → RAS: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29] ERAS → RAS: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34] WCAS → CAS: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29] ECAS → CAS: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34] WWE → WE: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29] EWE → WE: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34] WCKE0 → CKE0: SDRAMs U[6:2], U[24:20] ECKE0 → CKE0: SDRAMs U[10:7], U[28:25] WCKE1 → CKE1: SDRAMs U[15:11], U[33:29] ECKE1 → CKE1: SDRAMs U[19:16], U[37:34] WODT0 → ODT0: SDRAMs U[6:2] EODT0 → ODT0: SDRAMs U[10:7] WODT0 → ODT1: SDRAMs U[24:20] EODT0 → ODT1: SDRAMs U[28:25] PCK0 → CK: SDRAMs U[6:2], U[15:11] PCK1 → CK: SDRAMs U[10:7], U[28:25] PCK2 → CK: SDRAMs U[24:20], U[33:29] PCK3 → CK: SDRAMs U[19:16], U[37:34] PCK0 → CK: SDRAMs U[6:2], U[15:11] PCK1 → CK: SDRAMs U[10:7], U[28:25] PCK2 → CK: SDRAMs U[24:20], U[33:29] PCK3 → CK: SDRAMs U[19:16], U[37:34] Err_Out RST: SDRAMs U[37:2] Rev. 1.0 / Dec. 2009 22 Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol VDD VDDQ Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Rating - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V -55 to +100 Units V V V o Notes 1, 1, 1 1, 2 VIN, VOUT Voltage on any pin relative to Vss TSTG Notes: Storage Temperature C 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than 0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. DRAM Component Operating Temperature Range Temperature Range Symbol TOPER Notes: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to the DIMM SPD for option availability b. Hynix DDR3L SDRAMs support Auto Self-Refresh and Extended Temperature Range and please refer to Hynix component datasheet and/or the DIMM SPD for tREFI requirement in the Extended Temperature Range. Parameter Normal Operating Temperature Range Extended Temperature Range Rating 0 to 85 85 to 95 Units oC oC Notes 1,2 1,3 Rev. 1.0 / Dec. 2009 23 AAC & DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions Symbol VDD VDDQ Supply Voltage Supply Voltage for Output Parameter Rating Min. 1.425 1.425 Typ. 1.500 1.500 Max. 1.575 1.575 Units V V Notes 1,2 1,2 Notes: 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. AC & DC Input Measurement Levels AC and DC Logic Input Levels for Single-Ended Signals AC and DC Input Levels for Signal-Ended Command and Address Signals Single Ended AC and DC Input Levels for Command and ADDress DDR3-800/1066/1333 Symbol VIH.CA(DC100) VIL.CA(DC100) VIH.CA(AC175) VIL.CA(AC175) VIH.CA(AC150) VIL.CA(AC150) VRefCA(DC) Parameter Min DC input logic high DC input logic low AC input logic high AC input logic low AC Input logic high AC input logic low Reference Voltage for ADD, CMD inputs Vref + 0.100 VSS Vref + 0.175 Note2 Vref + 0.150 Note2 0.49 * VDD Max VDD Vref - 0.100 Note2 Vref - 0.175 Note2 Vref - 0.150 0.51 * VDD V V V V V V V 1 1 1, 2 1, 2 1, 2 1, 2 3, 4 Unit Notes Notes: 1. For input only pins except RESET, Vref = VrefCA (DC). 2. Refer to “Overshoot and Undershoot Specifications” on page 37. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). 4. For reference: approx. VDD/2 +/- 15 mV. Rev. 1.0 / Dec. 2009 24 AC and DC Input Levels for Signal-Ended Signals DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as specified in the table below. DDR3 SDRAM will also support corresponding tDS values (Table 41 and Table 47 in “ DDR3 Device Operation”) as well as derating tables in Table 44 of “DDR3 Device Operation” depending on Vih/Vil AC levels. Single Ended AC and DC Input Levels for DQ and DM DDR3-800/1066 Symbol VIH.CA(DC100) VIL.CA(DC100) VIH.CA(AC175) VIL.CA(AC175) VIH.CA(AC150) VIL.CA(AC150) VRefDQ(DC) Parameter Min DC input logic high Vref + 0.100 DC input logic low VSS AC input logic high Vref + 0.175 AC input logic low Note2 AC Input logic high Vref + 0.150 AC input logic low Note2 Reference Voltage for DQ, 0.49 * VDD DM inputs Max VDD Vref - 0.100 Note2 Vref - 0.175 Note2 Vref - 0.150 0.51 * VDD Min Vref + 0.100 VSS Vref + 0.150 Note2 0.49 * VDD Max VDD Vref - 0.100 Note2 Vref - 0.150 0.51 * VDD V V V V V V V 1 1 1, 2 1, 2 1, 2 1, 2 3, 4 DDR3-1333 Unit Notes Notes: 1. Vref = VrefDQ (DC). 2. Refer to “Overshoot and Undershoot Specifications” on page 37. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). 4. For reference: approx. VDD/2 +/- 15 mV. Rev. 1.0 / Dec. 2009 25 Vref Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure below. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise). VRef (DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in the table “Differential Input Slew Rate Definition” on page 32. Furthermore VRef (t) may temporarily deviate from VRef (DC) by no more than +/- 1% VDD. voltage VDD VRef ac-noise VRef(DC) VRef(t) VRef(DC)max VDD/2 VRef(DC)min VSS time Illustration of VRef(DC) tolerance and VRef ac-noise limits The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on VRef. “VRef ” shall be understood as VRef(DC), as defined in figure above. This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VRef(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRefac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings. Rev. 1.0 / Dec. 2009 26 AC and DC Logic Input Levels for Differential Signals Differential signal definition tDVAC VIL.DIFF.AC.MIN Differential Input Voltage(i.e.DQS - DQS#, CK - CK#) VIL.DIFF.MIN 0 half cycle VIL.DIFF.MAX VIL.DIFF.AC.MAX tDVAC time Definition of differential ac-swing and “time above ac-level” tDVAC Rev. 1.0 / Dec. 2009 27 Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS) Differential AC and DC Input Levels DDR3-800, 1066, 1333 Symbol VIHdiff VILdiff VIHdiff (ac) VILdiff (ac) Notes: 1. Used to define a differential signal slew-rate. 2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL (ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level applies also here. 3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” on page 37. Parameter Min Differential input high Differential input logic low Differential input high ac Differential input low ac + 0.200 Note 3 2 x (VIH (ac) - Vref) Note 3 Max Note 3 - 0.200 Note 3 2 x (VIL (ac) - Vref) V V V V 1 1 2 2 Unit Notes Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS Slew Rate [V/ns] > 4.0 4.0 3.0 2.0 1.8 1.6 1.4 1.2 1.0 < 1.0 tDVAC [ps] @ |VIH/Ldiff (ac)| = 350mV min 75 57 50 38 34 29 22 13 0 0 max tDVAC [ps] @ |VIH/Ldiff (ac)| = 300mV min 175 170 167 163 162 161 159 155 150 150 max - Rev. 1.0 / Dec. 2009 28 Single-ended requirements for differential signals Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH (ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac) / VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition. Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-levels apply also for the singleended signals CK and CK. VDD or VDDQ VSEHmin VSEH VDD/2 or VDDQ/2 CK or DQS VSELmax VSS or VSSQ VSEL time Single-ended requirements for differential signals. Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended components of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. Rev. 1.0 / Dec. 2009 29 Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU DDR3-800, 1066, 1333 Symbol VSEH VSEL Notes: 1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac) of DQs. 2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” on page 37. Parameter Min Single-ended high level for strobes Single-ended high level for Ck, CK Single-ended low level for strobes Single-ended low level for CK, CK (VDD / 2) + 0.175 (VDD /2) + 0.175 Note 3 Note 3 Max Note 3 Note 3 (VDD / 2) = 0.175 (VDD / 2) = 0.175 V V V V 1,2 1,2 1,2 1,2 Unit Notes Rev. 1.0 / Dec. 2009 30 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in table below. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS VDD CK, DQS VIX VDD/2 VIX VIX CK, DQS VSS Vix Definition Cross point voltage for differential input signals (CK, DQS) DDR3-800, 1066, 1333 Symbol VIX VIX Parameter Min Differential Input Cross Point Voltage relative to VDD/2 for CK, CK Differential Input Cross Point Voltage relative to VDD/2 for DQS, DQS -150 -175 -150 Max 150 175 150 mV mV mV 1 Unit Notes Notes: 1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK - CK is larger than 3 V/ns. 2. Refer to the table “Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU” on page 30 for VSEL and VSEH standard values Rev. 1.0 / Dec. 2009 31 Slew Rate Definitions for Single-Ended Input Signals See 7.5 “Address / Command Setup, Hold and Derating” on page 137 in “DDR3 Device Operation” for single-ended slew rate definitions for address and command signals. See 7.6 “Data Setup, Hold and Slew Rate Derating” on page 144 in “DDR3 Device Operation” for singleended slew rate definition for data signals. Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in table and figure below. Differential Input Slew Rate Definition Measured Description Min Max Defined by Differential input slew rate for rising edge (CK-CK and DQS-DQS) Differential input slew rate for falling edge (CK-CK and DQS-DQS) Notes: VILdiffmax VIHdiffmin VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds. Differential Input Voltage (i.e. DQS-DQS; CK-CK) Delta TRdiff vIHdiffmin 0 vILdiffmax Delta TFdiff Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# Differential Input Slew Rate Definition for DQS, DQS and CK, CK Rev. 1.0 / Dec. 2009 32 AC & DC Output Measurement Levels Single Ended AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals. Single-ended AC and DC Output Levels Symbol VOH(DC) VOM(DC) VOL(DC) VOH(AC) VOL(AC) Parameter DC output high measurement level (for IV curve linearity) DC output mid measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) AC output high measurement level (for output SR) AC output low measurement level (for output SR) DDR3-800, 1066, 1333 0.8 x VDDQ 0.5 x VDDQ 0.2 x VDDQ VTT + 0.1 x VDDQ VTT - 0.1 x VDDQ Unit V V V V V 1 1 Notes Notes: 1. The swing of ± 0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ / 2. Differential AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals. Differential AC and DC Output Levels Symbol VOHdiff (AC) VOLdiff (AC) Parameter AC differential output high measurement level (for output SR) AC differential output low measurement level (for output SR) DDR3-800, 1066, 1333 + 0.2 x VDDQ - 0.2 x VDDQ Unit V V Notes 1 1 Notes: 1. The swing of ± 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ/2 at each of the differential outputs. Rev. 1.0 / Dec. 2009 33 Single Ended Output Slew Rate When the Reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals are shown in table and figure below. Single-ended Output slew Rate Definition Measured Description From Single-ended output slew rate for rising edge Single-ended output slew rate for falling edge VOL(AC) VOH(AC) To VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / DeltaTRse [VOH(AC)-VOL(AC)] / DeltaTFse Defined by Notes: 1. Output slew rate is verified by design and characterisation, and may not be subject to production test. Delta TRse Single Ended Output Voltage(l.e.DQ) vOH(AC) V∏ vOl(AC) Delta TFse Single Ended Output Slew Rate Definition Single Ended Output slew Rate Definition Output Slew Rate (single-ended) DDR3-800 Parameter Single-ended Output Slew Rate Symbol SRQse Min 2.5 Max 5 DDR3-1066 Min 2.5 Max 5 DDR3-1333 Min 2.5 Max 5 Units V/ns Description: SR; Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting Rev. 1.0 / Dec. 2009 34 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and figure below. Differential Output Slew Rate Definition Measured Description From Differential output slew rate for rising edge Differential output slew rate for falling edge VOLdiff (AC) VOHdiff (AC) To VOHdiff (AC) VOLdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTRdiff [VOHdiff (AC)-VOLdiff (AC)] / DeltaTFdiff Defined by Notes: 1. Output slew rate is verified by design and characterization, and may not be subject to production test. Differential Output Voltage(i.e. DQS-DQS) Delta TRdiff vOHdiff(AC) O vOLdiff(AC) Delta TFdiff Differential Output Slew Rate Definition Differential Output slew Rate Definition Differential Output Slew Rate DDR3-800 Parameter Differential Output Slew Rate Symbol SRQdiff Min 5 Max 10 DDR3-1066 Min 5 Max 10 DDR3-1333 Min 5 Max 10 Units V/ns Description: SR; Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting Rev. 1.0 / Dec. 2009 35 Reference Load for AC Timing and Output Slew Rate Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. VDDQ CK, CK DUT DQ DQS DQS 25 Ohm VTT = VDDQ/2 Reference Load for AC Timing and Output Slew Rate Rev. 1.0 / Dec. 2009 36 Overshoot and Undershoot Specifications Address and Control Overshoot and Undershoot Specifications AC Overshoot/Undershoot Specification for Address and Control Pins Parameter Maximum peak amplitude allowed for overshoot area. (See figure below) Maximum peak amplitude allowed for undershoot area. (See figure below) Maximum overshoot area above VDD (See figure below) Maximum undershoot area below VSS (See figure below) DDR3-800 DDR3-1066 DDR3-1333 Units 0.4 0.4 0.67 0.67 0.4 0.4 0.5 0.5 0.4 0.4 0.4 0.4 V V V-ns V-ns (A0-A15, BA0-BA3, CS, RAS, CAS, WE, CKE, ODT) See figure below for each parameter definition Maximum Amplitude Overshoot Area Volts (V) VDD VSS Undershoot Area Maximum Amplitude Time (ns) Address and Control Overshoot and Undershoot Definition Address and Control Overshoot and Undershoot Definition Rev. 1.0 / Dec. 2009 37 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask Parameter Maximum peak amplitude allowed for overshoot area (See figure below) Maximum peak amplitude allowed for undershoot area (See figure below) Maximum overshoot area above VDD (See figure below) Maximum undershoot area below VSS (See figure below) DDR3-800 DDR3-1066 DDR3-1333 Units 0.4 0.4 0.25 0.25 0.4 0.4 0.19 0.19 0.4 0.4 0.15 0.15 V V V-ns V-ns (CK, CK, DQ, DQS, DQS, DM) See figure below for each parameter definition Maximum Amplitude Overshoot Area Volts (V) VDDQ VSSQ Undershoot Area Maximum Amplitude Time (ns) Clock, Data Strobe and Mask Overshoot and Undershoot Definition Clock, Data, Strobe and Mask Overshoot and Undershoot Definition Rev. 1.0 / Dec. 2009 38 Refresh parameters by device density Refresh parameters by device density Parameter REF command ACT or REF command time Average periodic refresh interval RTT_Nom Setting tRFC tREFI 85 °C < TCASE ≤ 95 °C 0 °C ≤ TCASE ≤ 85 °C 512Mb 90 7.8 3.9 1Gb 110 7.8 3.9 2Gb 160 7.8 3.9 4Gb 300 7.8 3.9 8Gb 350 7.8 3.9 Units ns us us Standard Speed Bins DDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. DDR3-800 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 42. Speed Bin CL - nRCD - nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CL = 6 CWL = 5 CWL = 5 Supported CL Settings Supported CWL Settings Symbol min 15 15 15 52.5 37.5 Reserved 2.5 6 5 3.3 DDR3-800E 6-6-6 max 20 — — — 9 * tREFI ns ns ns ns ns ns ns 1, 2, 3, 4 1, 2, 3 Unit Notes tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) nCK nCK Rev. 1.0 / Dec. 2009 39 DDR3-1066 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 42. Speed Bin CL - nRCD - nRP Parameter Symbol Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CL = 6 CL = 7 CL = 8 CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 min 13.125 13.125 13.125 50.625 37.5 Reserved Reserved 2.5 Reserved Reserved 1.875 Reserved 1.875 6, 7, 8 5, 6 < 2.5 < 2.5 3.3 DDR3-1066F 7-7-7 max 20 — — — 9 * tREFI ns ns ns ns ns ns ns ns ns ns ns ns ns 1, 2, 3, 4, 5 4 1, 2, 3, 5 1, 2, 3, 4 4 1, 2, 3, 4 4 1, 2, 3 Unit Note tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) Supported CL Settings Supported CWL Settings nCK nCK Rev. 1.0 / Dec. 2009 40 DDR3-1333 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 42. Speed Bin CL - nRCD - nRP Parameter Symbol Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 6, 7 CWL = 5 CL = 6 CWL = 6 CWL = 7 CWL = 5 CL = 7 CWL = 6 CWL = 7 CWL = 5 CL = 8 CWL = 6 CWL = 7 CL = 9 CWL = 5, 6 CWL = 7 CWL = 5, 6 CL = 10 CWL = 7 min 13.5 (13.125)8 13.5 (13.125)8 13.5 (13.125)8 49.5 (49.125)8 36 Reserved Reserved 2.5 Reserved Reserved Reserved 1.875 Reserved Reserved Reserved 1.875 Reserved Reserved 1.5 Reserved 1.5 Reserved 6, 8, (7), 9, (10) 5, 6, 7