HMT125U7AFR8C-S5

240pin DDR3 SDRAM Unbuffered DIMMs DDR3 SDRAM Unbuffered DIMMs Based on 1Gb A version HMT164U6AFP(R)6C HMT112U6AFP(R)8C HMT112U7AFP(R)8C HMT125U6AFP(R)8C HMT125U7AFP(R)8C ** Contents are subject to change without prior notice. Rev. 0.1 / Dec 2008 1 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Revision History Revision No. 0.01 0.02 0.1 History Initial draft for internal review Added IDD & Halogen-free products Initial Specification Release. Corrected typo on package ball feature. Draft Date Nov. 2007 Mar. 2008 Dec 2008 Remark Preliminary Preliminary Rev. 0.1 / Dec 2008 2 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table of Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Speed Grade & Key Parameters 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 512MB, 64Mx64 Module(1Rank of x16) 3.2 1GB, 128Mx64 Module(1Rank of x8) 3.3 1GB, 128Mx72 ECC Module(1Rank of x8) 3.4 2GB, 256Mx64 Module(2Rank of x8) 3.5 2GB, 256Mx72 ECC Module(2Rank of x8) 4. Address Mirroring Feature 4.1 DRAM Pin Wiring for Mirroring 5. Absolute Maximum Ratings 5.1 Absolute Maximum DC Ratings 5.2 Operating Temperature Range 6. AC & DC Operating Conditions 6.1 Recommended DC Operating Conditions 6.2 DC & AC Logic Input Levels 6.2.1 For Single-ended Signals 6.2.2 For Differential Signals 6.2.3 Differential Input Cross Point 6.3 Slew Rate Definition 6.3.1 For Ended Input Signals 6.3.2 For Differential Input Signals 6.4 DC & AC Output Buffer Levels 6.4.1 Single Ended DC & AC Output Levels 6.4.2 Differential DC & AC Output Levels 6.4.3 Single Ended Output Slew Rate 6.4.4 Differential Ended Output Slew Rate 6.5 Overshoot/Undershoot Specification 6.6 Input/Output Capacitance & AC Parametrics 6.7 IDD Specifications & Measurement Conditions 7. Electrical Characteristics and AC Timing 7.1 Refresh Parameters by Device Density 7.2 DDR3 Standard speed bins and AC para 8. DIMM Outline Diagram 8.1 512MB, 64Mx64 Module(1Rankx16) 8.2 1GB, 128Mx64 Module(1Rank of x8) 8.3 1GB, 128Mx72 ECC Module(1Rank of x8) 8.4 2GB, 256Mx64 Module(2Rank of x8) 8.5 2GB, 256Mx72 ECC Module(2Rank of x8) Rev. 0.1 / Dec 2008 3 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 1. Description This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb A version. DDR3 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240 pin glass-epoxy substrate. This DDR3 Unbuffered DIMM series based on 1Gb A ver. provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. 1.1 Device Features & Ordering Information 1.1.1 Features • VDD=VDDQ=1.5V • VDDSPD=3.3V to 3.6V • Fully differential clock inputs (CK, /CK) operation • Differential Data Strobe (DQS, /DQS) • On chip DLL align DQ, DQS and /DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11) supported • Programmable additive latency 0, CL-1, and CL-2 sup ported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8banks • 8K refresh cycles /64ms • DDR3 SDRAM Package: JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16) with support balls • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • TDQS (Termination Data Strobe) supported (x8 only) • Write Levelization supported • Auto Self Refresh supported • On Die Thermal Sensor supported (JEDEC optional) Rev. 0.1 / Dec 2008 4 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 1.1.2 Ordering Information # of # of DRAMs ranks 4 4 8 8 9 9 16 16 18 18 1 1 1 1 1 1 2 2 2 2 Part Name HMT164U6AFP6C-S6/S5/G8/G7/H9/H8 HMT164U6AFR6C-S6/S5/G8/G7/H9/H8 HMT112U6AFP8C-S6/S5/G8/G7/H9/H8 HMT112U6AFR8C-S6/S5/G8/G7/H9/H8 HMT112U7AFP8C-S6/S5/G8/G7/H9/H8 HMT112U7AFR8C-S6/S5/G8/G7/H9/H8 HMT125U6AFP8C-S6/S5/G8/G7/H9/H8 HMT125U6AFR8C-S6/S5/G8/G7/H9/H8 HMT125U7AFP8C-S6/S5/G8/G7/H9/H8 HMT125U7AFR8C-S6/S5/G8/G7/H9/H8 Density 512MB 512MB 1GB 1GB 1GB 1GB 2GB 2GB 2GB 2GB Org. 64Mx64 64Mx64 128Mx64 128Mx64 128Mx72 128Mx72 256Mx64 256Mx64 256Mx72 256Mx72 Materials Lead-free ECC None TS No No No No Yes Yes No No Yes Yes Halogen-free None Lead free None Halogen-free None Lead free Halogen-free Lead free ECC ECC None Halogen-free None Lead free Halogen-free ECC ECC Rev. 0.1 / Dec 2008 5 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 1.2 Speed Grade & Key Parameters MT/S Grade tCK(min) CAS Latency tRCD(min) tRP(min) tRAS(min) tRC(min) CL-tRCD-tRP 6 15 15 37.5 52.5 6-6-6 DDR3-800 -S6 2.5 5 12.5 12.5 37.5 50 5-5-5 8 15 15 37.5 52.5 8-8-8 -S5 DDR3-1066 -G8 1.875 7 13.125 13.125 37.5 50.625 7-7-7 9 13.5 13.5 36 49.5 9-9-9 -G7 DDR3-1333 -H9 1.5 8 12 12 36 48 8-8-8 10 12.5 12.5 35 47.25 10-10-10 -H8 DDR3-1600 Unit -P1 1.25 9 11.25 11.25 35 46.25 9-9-9 -P9 ns tCK ns ns ns ns tCK 1.3 Address Table 512MB Organization Refresh Method Row Address Column Address Bank Address Page Size # of Rank # of Device 64M x 64 8K/64ms A0-A12 A0-A9 BA0-BA2 2KB 1 4 1GB 128M x 64 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 1 8 1GB 128M x 72 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 1 9 2GB 256M x 64 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 2 16 2GB 256M x 72 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 2 18 Rev. 0.1 / Dec 2008 6 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 2. Pin Architecture 2.1 Pin Definition Pin Name A0–A13 BA0–BA2 RAS CAS WE S0–S1 CKE0–CKE1 ODT0–ODT1 DQ0–DQ63 CB0–CB7 DQS0–DQS8 DQS0–DQS8 DM0–DM8 CK0–CK1 CK0–CK1 Description SDRAM address bus SDRAM bank select SDRAM row address strobe SDRAM column address strobe SDRAM write enable DIMM Rank Select Lines SDRAM clock enable lines On-die termination control lines DIMM memory data bus DIMM ECC check bits SDRAM data strobes (positive line of differential pair) SDRAM data strobes (negative line of differential pair) SDRAM data masks/high data strobes (x8-based x72 DIMMs) SDRAM clocks (positive line of differential pair) SDRAM clocks (negative line of differential pair) Pin Name SCL SDA SA0–SA2 VDD* VDDQ* VREFDQ VREFCA VSS VDDSPD NC TEST RESET VTT RFU Description I2C serial bus clock for EEPROM I2C serial bus data line for EEPROM I2C slave address select for EEPROM SDRAM core power supply SDRAM I/O Driver power supply SDRAM I/O reference supply SDRAM command/address reference supply Power supply return (ground) Serial EEPROM positive power supply Spare pins (no connect) Memory bus analysis tools (unused on memory DIMMS) Set DRAMs to Known State SDRAM I/O termination supply Reserved for future use - *The VDD and VDDQ pins are tied common to a single power-plane on these designs Rev. 0.1 / Dec 2008 7 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 2.2 Input/Output Functional Description Symbol CK0–CK1 CK0–CK1 Type Polarity Differential crossing Function CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing). Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. This signal provides for external rank selection on systems with multiple ranks. RAS, CAS, and WE (ALONG WITH S) define the command being entered. When high, termination resistance is enabled for all DQ, DQS, DQS and DM pins, assuming this function is enabled in the Mode Register 1 (MR1). Reference voltage for SSTL15 I/O inputs. Reference voltage for SSTL 15 command/address inputs. Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. — Selects which SDRAM bank of eight is activated. During a Bank Activate command cycle, Address input defines the row address (RA0–RA15). During a Read or Write command cycle, Address input defines the column address. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to define which bank to precharge. A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-the-fly) will be performed (HIGH, no burst chop; LOW, burst chopped). Data and Check Bit Input/Output pins. DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Power and ground for the DDR3 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules. SSTL CKE0–CKE1 SSTL Active High S0–S1 SSTL Active Low RAS, CAS, WE ODT0–ODT1 VREFDQ VREFCA VDDQ BA0–BA2 SSTL SSTL Supply Supply Supply SSTL Active Low Active High A0–A13 SSTL — DQ0–DQ63, CB0–CB7 SSTL — DM0–DM8 SSTL Active High VDD, VSS Supply Rev. 0.1 / Dec 2008 8 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Symbol DQS0–DQS8 DQS0–DQS8 SA0–SA2 Type SSTL Polarity Differential crossing — Function Data strobe for input and output data. These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external resistor may be connected from the SDA bus line to VDDSPD to act as a pullup on the system board. This signal is used to clock data into and out of the SPD EEPROM. An external resistor may be connected from the SCL bus time to VDDSPD to act as a pullup on the system board. Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable from 3.0V to 3.6V. SDA — SCL — VDDSPD Supply 2.3 Pin Assignment Front Side(left 1–60) Pin x64 # Non-ECC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VREFDQ VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 x72 ECC VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 Back Side(right 121–180) Pin x64 # Non-ECC VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 x72 ECC VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS Front Side(left 61–120) Back Side(right 181–240) Pin # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 x64 Non-ECC A2 VDD CK1 CK1 VDD VDD VREFCA NC VDD A10 BA02 VDD WE CAS VDD S1 x72 ECC A2 VDD CK1 CK1 VDD VDD VREFCA NC VDD A10 BA02 VDD WE CAS VDD S1 Pin # 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 x64 Non-ECC A1 VDD VDD CK0 CK0 VDD NC A0 VDD BA12 VDD RAS S0 VDD ODT0 A13 x72 ECC A1 VDD VDD CK0 CK0 VDD NC A0 VDD BA12 VDD RAS S0 VDD ODT0 A13 VREFDQ 121 NC = No Connect; RFU = Reserved Future Use 1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group. 2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored. Please refer to Section 4.1 for more information on mirrored addresses. Rev. 0.1 / Dec 2008 9 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Front Side(left 1–60) Pin x64 # Non-ECC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 VSS NC NC VSS NC NC VSS NC NC VSS x72 ECC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8 DQS8 VSS CB2 CB3 VSS Back Side(right 121–180) Pin x64 # Non-ECC 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS NC NC VSS DM8 NC VSS NC NC VSS NC x72 ECC DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8 NC VSS CB6 CB7 VSS NC Front Side(left 61–120) Back Side(right 181–240) Pin # 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 x64 Non-ECC ODT1 VDD NC VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS x72 ECC ODT1 VDD NC VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS Pin # 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 x64 Non-ECC VDD NC VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 x72 ECC VDD NC VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 NC = No Connect; RFU = Reserved Future Use 1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group. 2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored. Please refer to Section 4.1 for more information on mirrored addresses. Rev. 0.1 / Dec 2008 10 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Front Side(left 1–60) Pin x64 # Non-ECC 48 49 50 51 52 53 54 55 56 57 58 59 60 NC KEY NC CKE0 VDD BA2 NC VDD All A72 VDD A52 A42 VDD NC CKE0 VDD BA2 NC VDD All A72 VDD A52 A42 VDD x72 ECC NC Back Side(right 121–180) Pin x64 # Non-ECC 168 169 170 171 172 173 174 175 176 177 178 179 180 Reset KEY CKE1/NC VDD NC NC VDD A12 A9 VDD A82 A62 VDD A32 CKE1/NC VDD NC NC VDD A12 A9 VDD A82 A62 VDD A32 x72 ECC Reset Front Side(left 61–120) Back Side(right 181–240) Pin # 108 109 110 111 112 113 114 115 116 117 118 119 120 x64 Non-ECC DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SA0 SCL SA2 VTT x72 ECC DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SA0 SCL SA2 VTT Pin # 228 229 230 231 232 233 234 235 236 237 238 239 240 x64 Non-ECC DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT x72 ECC DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT NC = No Connect; RFU = Reserved Future Use 1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group. 2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored. Please refer to Section 4.1 for more information on mirrored addresses. Rev. 0.1 / Dec 2008 11 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 3. Functional Block Diagram 3.1 512MB, 64Mx64 Module(1Rank of x16) S0 DQS0 DQS0 DM0 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS D0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS4 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS D2 DQS1 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS5 DQS5 DM5 ZQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 ZQ DQS2 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS CS D1 DQS6 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS CS D3 DQS3 DQS3 DM3 CS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS7 DQS7 DM7 CS ZQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 ZQ Serial PD SCL BA0–BA2 A0–A14 RAS CAS CKE0 WE ODT0 CK0 CK0 RESET BA0–BA2: SDRAMs D0–D3 A0–A14: SDRAMs D0–D3 RAS: SDRAMs D0–D3 CAS: SDRAMs D0–D3 CKE: SDRAMs D0–D3 WE: SDRAMs D0–D3 ODT: SDRAMs D0–D3 CK: SDRAMs D0–D3 CK: SDRAMs D0–D3 RESET:SDRAMs D0-D3 WP A0 SA0 A1 SA1 A2 SA2 SDA VDDSPD VDD/VDDQ VREFDQ VSS VREFCA SPD D0–D3 D0–D3 D0–D3 D0–D3 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,DM,DQS,DQS resistors;Refer to associated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document. 5. The pair CK1 and CK1# is terminated in 75ohm but is not used on the module. 6. A15 is not routed on the module. 7. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% 8. One SPD exists per module. Rev. 0.1 / Dec 2008 12 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 3.2 1GB, 128Mx64 Module(1Rank of x8) DQS0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 S0 DQS4 DQS4 DM4 I/O I/O I/O I/O I/O I/O I/O I/O DM CS DQS DQS 0 1 D0 2 3 4 5 6 ZQ 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D4 ZQ DQS1 DQS1 DM1 DQS5 DQS5 DM5 DQS2 DQS2 DM2 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS DQS DQS I/O 0 I/O 1 D1 I/O 2 I/O 3 I/O 4 I/O 5 ZQ I/O 6 I/O 7 DQS6 DQS6 DM6 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D5 ZQ DQS3 DQS3 DM3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O I/O I/O I/O I/O I/O I/O I/O DM CS DQS DQS 0 1 D2 2 3 4 5 6 7 ZQ DQS7 DQS7 DM7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D6 ZQ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS DQS DQS I/O 0 I/O 1 D3 I/O 2 I/O 3 I/O 4 I/O 5 ZQ I/O 6 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D7 ZQ Serial PD WP A0 SDA A1 SA1 A2 SA2 SCL BA0–BA2 A0–A15 RAS CAS CKE0 WE ODT0 CK0 CK0 RESET BA0–BA2: SDRAMs D0–D7 A0–A15: SDRAMs D0–D7 RAS: SDRAMs D0–D7 CAS: SDRAMs D0–D7 CKE: SDRAMs D0–D7 WE: SDRAMs D0–D7 ODT: SDRAMs D0–D7 CK: SDRAMs D0–D7 CK: SDRAMs D0–D7 RESET:SDRAMs D0-D7 SA0 VDDSPD VDD/VDDQ VREFDQ VSS VREFCA SPD D0–D7 D0–D7 D0–D7 D0–D7 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,DM,DQS/DQS resistors;Refer to associated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document. 5. Refer to Section 3.1 of this document for details on address mirroring. 6. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% 7. One SPD exists per module. Rev. 0.1 / Dec 2008 13 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 3.3 1GB, 128Mx72 Module(1Rank of x8) DQS0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 S0 DQS4 DQS4 DM4 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D0 ZQ DQS1 DQS1 DM1 DQS5 DQS5 DM5 CS DQS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D4 ZQ DQS2 DQS2 DM2 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D1 ZQ DQS6 DQS6 DM6 CS DQS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D5 ZQ DQS3 DQS3 DM3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 ZQ DQS7 DQS7 DM7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D6 ZQ DQS8 DQS8 DM8 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D3 ZQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D7 ZQ CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS SPD(TS integrated) SCL D8 EVENT ZQ EVENT A0 SA0 SDA A1 SA1 A2 SA2 BA0–BA2 A0–A15 RAS CAS CKE0 WE ODT0 CK0 CK0 RESET BA0–BA2: SDRAMs D0–D8 A0–A15: SDRAMs D0–D8 VDDSPD RAS: SDRAMs D0–D8 VDD/VDDQ CAS: SDRAMs D0–D8 CKE: SDRAMs D0–D8 VREFDQ WE: SDRAMs D0–D8 VSS ODT: SDRAMs D0–D8 CK: SDRAMs D0–D8 VREFCA CK: SDRAMs D0–D8 RESET:SDRAMs D0-D8 SPD D0–D8 D0–D8 D0–D8 D0–D8 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,CB,DM,DQS/DQS resistors;Refer to associated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document. 5. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% 6. One SPD exists per module. Rev. 0.1 / Dec 2008 14 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 3.4 2GB, 256Mx64 Module(2Rank of x8) S0 DQS0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS S1 DQS4 DQS4 DM4 DM CS DQS DQS I/O 0 I/O 1 D8 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 ZQ I/O 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS DQS DQS I/O 0 I/O 1 D4 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 D12 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D0 DQS1 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DQS5 DQS5 DM5 DM CS DQS DQS I/O 0 I/O 1 D9 I/O 2 I/O 3 I/O 4 I/O 5 ZQ I/O 6 I/O 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 ZQ ZQ CS DQS DQS D1 DQS2 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DM CS DQS DQS I/O 0 I/O 1 D5 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS6 DQS6 DM6 ZQ DM CS DQS DQS I/O 0 I/O 1 D13 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ CS DQS DQS D2 DQS3 DQS3 DM3 ZQ DM CS DQS DQS I/O 0 I/O 1 D10 I/O 2 I/O 3 I/O 4 I/O 5 ZQ I/O 6 I/O 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS DQS DQS I/O 0 I/O 1 D6 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DM CS DQS DQS I/O 0 I/O 1 D14 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DQS7 DQS7 DM7 DM CS DQS DQS I/O 0 I/O 1 D11 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 ZQ I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS DQS DQS I/O 0 I/O 1 D7 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 D15 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D3 ZQ ZQ ZQ Serial PD BA0–BA2 A0–A15 CKE1 CKE0 RAS CAS WE ODT0 ODT1 CK0 CK0 CK1 CK1 BA0–BA2: SDRAMs D0–D15 SCL A0-A15: SDRAMs D0–D15 WP CKE: SDRAMs D8–D15 A0 CKE: SDRAMs D0–D7 SA0 RAS: SDRAMs D0–D15 CAS: SDRAMs D0–D15 VDDSPD WE: SDRAMs D0–D15 VDD/VDDQ ODT: SDRAMs D0–D7 VREFDQ ODT: SDRAMs D8–D15 CK: SDRAMs D0–D7 VSS CK: SDRAMs D0–D7 VREFCA CK: SDRAMs D8–D15 CK: SDRAMs D8–D15 SDA A1 SA1 A2 SA2 SPD D0–D15 D0–D15 D0–D15 D0–D15 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,DM,DQS,DQS resistors;Refer to associated topology diagram. 4. Refer to Section 3.1 of this document for details on address mirroring. 5. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% 6. One SPD exists per module. RESET RESET:SDRAMs D0-D3 Rev. 0.1 / Dec 2008 15 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 3.5 2GB, 256Mx72 Module(2Rank of x8) DQS0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 S0 S1 DQS4 DQS4 DM4 DM CS DQS DQS I/O 0 I/O 1 D0 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D9 ZQ DQS1 DQS1 DM1 DQS5 DQS5 DM5 CS DQS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS DQS DQS I/O 0 I/O 1 D4 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D13 ZQ DM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D1 DQS2 DQS2 DM2 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D10 ZQ DQS6 DQS6 DM6 CS DQS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS DQS DQS I/O 0 I/O 1 D5 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D14 ZQ DQS3 DQS3 DM3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS DQS DQS I/O 0 I/O 1 D2 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D11 ZQ DQS7 DQS7 DM7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS DQS DQS I/O 0 I/O 1 D6 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D15 ZQ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS DQS DQS I/O 0 I/O 1 D3 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D12 DQS8 DQS8 DM8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 ZQ ZQ SCL DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS DQS DQS I/O 0 I/O 1 D7 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D16 ZQ SPD VDDSPD SPD(TS integrated) DM CS DQS DQS I/O 0 I/O 1 D8 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS VDD/VDDQ D0–D17 D0–D17 D0–D17 D0–D17 EVENT EVENT A0 SA0 SDA A1 SA1 VREFDQ Vss VREFCA D17 A2 SA2 ZQ ZQ ODT: SDRAMs D0–D8 ODT: SDRAMs D9–D17 CK: SDRAMs D0–D8 CK: SDRAMs D0–D8 CK: SDRAMs D9–D17 CK: SDRAMs D9–D17 RESET:SDRAMs D0-D17 BA0–BA2 A0–A15 CKE0 CKE1 RAS CAS WE BA0-BA2: SDRAMs D0–D17 A0-A15: SDRAMs D0–D17 CKE: SDRAMs D0–D8 CKE: SDRAMs D9–D17 RAS: SDRAMs D0–D17 CAS: SDRAMs D0–D17 WE: SDRAMs D0–D17 ODT0 ODT1 CK0 CK0 CK1 CK1 RESET Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,CB,DM/DQS/DQS resistors;Refer to associated topology diagram. 4. Refer to Section 3.1 of this document for details on address mirroring. 5. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% 6. One SPD exists per module. Rev. 0.1 / Dec 2008 16 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 4. Address Mirroring Feature There is a via grid located under the SDRAMs for wiring the CA signals (address, bank address, command, and control lines) to the SDRAM pins. The length of the traces from the via to the SDRAMs places limitations on the bandwidth of the module. The shorter these traces, the higher the bandwidth. To extend the bandwidth of the CA bus for DDR3 modules, a scheme was defined to reduce the length of these traces.The pins on the SDRAM are defined in a manner that allows for these short trace lengths. The CA bus pins in Columns 2 and 8, ignoring the mechanical support pins, do not have any special functions (secondary functions). This allows the most flexibility with these pins. These are address pins A3, A4, A5, A6, A7, A8 and bank address pins BA0 and BA1. Refer to Table . Rank 0 SDRAM pins are wired straight, with no mismatch between the connector pin assignment and the SDRAM pin assignment. Some of the Rank 1 SDRAM pins are cross wired as defined in the table. Pins not listed in the table are wired straight. 4.1 DRAM Pin Wiring for Mirroring Connector Pin A3 A4 A5 A6 A7 A8 BA0 BA1 SDRAM Pin Rank 0 A3 A4 A5 A6 A7 A8 BA0 BA1 The table 4.1 illustrates the wiring in both the mirrored and non-mirrored case. The lengths of the traces to the SDRAM pins, is obviously shorter. The via grid is smaller as well. Rank 1 A4 A3 A6 A5 A8 A7 BA1 BA0 Rev. 0.1 / Dec 2008 17 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C No Mirroring Mirroring < Figure 4.1: Wiring Differences for Mirrored and Non-Mirrored Addresses > Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is read the same way. There are limitations however. When writing to the internal registers with a "load mode" operation, the specific address is required. This requires the controller to know if the rank is mirrored or not. This requires a few rules. Mirroring is done on 2 rank modules and can only be done on the second rank. There is not a requirement that the second rank be mirrored. There is a bit assignment in the SPD that indicates whether the module has been designed with the mirrored feature or not. See the DDR3 UDIMM SPD specification for these details. The controller must read the SPD and have the capability of de-mirroring the address when accessing the second rank. Rev. 0.1 / Dec 2008 18 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 5. ABSOLUTE MAXIMUM RATINGS 5.1 Absolute Maximum DC Ratings Symbol VDD VDDQ VIN, VOUT TSTG Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on any pin relative to Vss Storage Temperature Rating - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V -55 to +100 ℃ Units V V V ℃ ,2 Notes ,3 ,3 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. 5.2 DRAM Component Operating Temperature Range Symbol TOPER Parameter Normal Temperature Range Extended Temperature Range Rating 0 to 85 85 to 95 Units ℃ ℃ Notes ,2 1,3 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85°… and 95°… case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. (This double refresh requirement may not apply for some devices.) It is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to supplier data sheet and/ or the DIMM SPD for option avail ability. b) If Self-Refresh operation is required in the Extended Temperature Range, than it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0band MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Rev. 0.1 / Dec 2008 19 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 6. AC & DC Operating Conditions 6.1 Recommended DC Operating Conditions Rating Min. 1.425 1.425 Typ. 1.500 1.500 Max. 1.575 1.575 Symbol VDD VDDQ Parameter Supply Voltage Supply Voltage for Output Units V V Notes 1,2 1,2 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD abd VDDQ tied together. 6.2 DC & AC Logic Input Levels 6.2.1 DC & AC Logic Input Levels for Single-Ended Signals DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600 Symbol VIH(DC) VIL(DC) VIH(AC) VIL(AC) VRefDQ(DC) VRefCA(DC) VTT Parameter Min DC input logic high DC input logic low AC input logic high AC input logic low Reference Voltage for DQ, DM inputs Reference Voltage for ADD, CMD inputs Termination voltage for DQ, DQS outputs 0.49 * VDD 0.49 * VDD VDDQ/2 - TBD Vref + 0.175 Vref + 0.100 Max Vref - 0.100 Vref - 0.175 0.51 * VDD 0.51 * VDD VDDQ/2 + TBD V V V V V V V 1, 2 1, 2 1, 2 1, 2 3, 4 3, 4 Unit Notes 1. For DQ and DM, Vref = VrefDQ. For input ony pins except RESET#, Vref = VrefCA. 2. The “t.b.d.” entries might change based on overshoot and undershoot specification. 3. The ac peak noise on VRef may not allow VRef to deviate from VRef(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). For reference: approx. VDD/2 +/- 15 mV. The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure 6.2.1. It shows a valid reference voltage VRef(t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise).VRef(DC) is the linear average of VRef(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in Table 1. Furthermore VRef(t) may temporarily deviate from VRef(DC) by no more than +/- 1% VDD. Rev. 0.1 / Dec 2008 20 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C voltage VDD VRef ac-noise VRef(DC) VRef(t) VRef(DC)max VDD/2 VRef(DC)min VSS time < Figure 6.2.1: Illustration of Vref(DC) tolerance and Vref AC-noise limits > The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VRef. "VRef " shall be understood as VRef(DC), as defined in Figure 6.2.1 This clarifies, that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VRef(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings. 6.2.2 DC & AC Logic Input Levels for Differential Signals DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600 Min + 0.200 Max - 0.200 Symbol VIHdiff VILdiff Note1: Parameter Differential input logic high Differential input logic low Unit V V Notes 1 1 Refer to “Overshoot and Undershoot Specification section 6.5 on 26 page Rev. 0.1 / Dec 2008 21 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 6.2.3 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the requirements in Table 6.2.3 The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the midlevel between of VDD and VSS. VDD CK#, DQS# VIX VDD/2 VIX VIX CK, DQS VSS < Figure 6.2.3 Vix Definition > DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600 Symbol Parameter Min VIX Differential Input Cross Point Voltage relative to VDD/2 - 150 Max + 150 mV Unit Notes < Table 6.2.3: Cross point voltage for differential input signals (CK, DQS) > Rev. 0.1 / Dec 2008 22 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 6.3 Slew Rate Definitions 6.3.1 For Single Ended Input Signals - Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS) Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VRef and the first crossing of VIH(AC)min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VRef and the first crossing of VIL(AC)max. - Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH) Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VRef. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VRef. Measured Min Vref Vref VIL(DC)max VIH(DC)min Max VIH(AC)min VIL(AC)max Vref Vref Description Input slew rate for rising edge Input slew rate for falling edge Input slew rate for rising edge Input slew rate for falling edge Defined by VIH(AC)min-Vref Delta TRS Vref-VIL(AC)max Delta TFS Vref-VIL(DC)max Delta TFH VIH(DC)min-Vref Delta TRH Applicable for Setup (tIS, tDS) Hold (tIH, tDH) < Table 6.3.1: Single-Ended Input Slew Rate Definition > Part A: Set up Delta TRS Single Ended input Voltage(DQ,ADD, CMD) vIH(AC)min vIH(DC)min vRefDQ or vRefCA vIL(DC)max vIL(AC)max Delta TFS Rev. 0.1 / Dec 2008 23 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C P a rt B : H o ld D e lta T R H Single Ended input Voltage(DQ,ADD, CMD) v IH (A C )m in v IH (D C )m in v R e fD Q o r v R e fC A v IL (D C )m a x v IL (A C )m a x D e lta T F H < Figure 6.3.1: Input Nominal Slew Rate Definition for Single-Ended Signals > 6.3.2 Differential Input Signals Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown in below Table and Figure . Measured Min VILdiffmax VIHdiffmin Max VIHdiffmin VILdiffmax Description Differential input slew rate for rising edge (CK-CK and DQS-DQS) Differential input slew rate for falling edge (CK-CK and DQS-DQS) Note: Defined by VIHdiffmin-VILdiffmax DeltaTRdiff VIHdiffmin-VILdiffmax DeltaTFdiff The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds. Rev. 0.1 / Dec 2008 24 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Differential Input Voltage (i.e. DQS-DQS; CK-CK) D e lta T R d iff vIH d iffm in 0 vILd iffm a x D e lta T F d iff < Figure 6.3.2: Differential Input Slew Rate Definition for DQS,DQS# and CK,CK# > 6.4 DC & AC Output Buffer Levels 6.4.1 Single Ended DC & AC Output Levels Below table shows the output levels used for measurements of single ended signals. Symbol VOH(DC) VOM(DC) VOL(DC) VOH(AC) VOL(AC) Parameter DC output high measurement level (for IV curve linearity) DC output mid measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) AC output high measurement level (for output SR) AC output low measurement level DDR3-800, 1066, 1333 and 1600 0.8 x VDDQ 0.5 x VDDQ 0.2 x VDDQ VTT + 0.1 x VDDQ Unit V V V V 1 Notes VTT - 0.1 x VDDQ V 1 (for output SR) 1. The swing of ± 0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ / 2. Rev. 0.1 / Dec 2008 25 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 6.4.2 Differential DC & AC Output Levels Below table shows the output levels used for measurements of differential signals. Symbol VOHdiff (AC) VOLdiff (AC) Parameter AC differential output high measurement level (for output SR) DDR3-800, 1066, 1333 and 1600 + 0.2 x VDDQ Unit V Notes 1 AC differential output low - 0.2 x VDDQ V 1 measurement level (for output SR) 1. The swing of °æ 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swingwith a driver impedance of 40ߟ and an effective test load of 25ߟ to VTT = VDDQ/2 at each of the differential output 6.4.3 Single Ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in below Table and Figure 6.4.3. Measured From VOL(AC) VOH(AC) To VOH(AC) VOL(AC) Description Single ended output slew rate for rising edge Single ended output slew rate for falling edge Note: Defined by VOH(AC)-VOL(AC) DeltaTRse VOH(AC)-VOL(AC) DeltaTFse Output slew rate is verified by design and characterization, and may not be subject to production test. D e lt a T R s e Single Ended Output Voltage(l.e.DQ) vO H (A C ) V∏ vO L(A C ) D e lt a T F s e < Figure 6.4.3: Single Ended Output Slew Rate Definition > Rev. 0.1 / Dec 2008 26 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Parameter Single-ended Output Slew Rate Symbol SRQse DDR3-800 Min 2.5 Max 5 DDR3-1066 Min 2.5 Max 5 DDR3-1333 Min 2.5 Max 5 DDR3-1600 Min TBD Max 5 Units V/ns *** Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) For Ron = RZQ/7 setting < Table 6.4.3: Output Slew Rate (single-ended) > 6.4.4 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in below Table and Figure 6.4.4 Measured From VOLdiff(AC) VOHdiff(AC) To VOHdiff(AC) VOLdiff(AC) Description Differential output slew rate for rising edge Differential output slew rate for falling edge Defined by VOHdiff(AC)-VOLdiff(AC) DeltaTRdiff VOHdiff(AC)-VOLdiff(AC) DeltaTFdiff Note: Output slew rate is verified by design and characterization, and may not be subject to production test. Differential Output Voltage(i.e. DQS-DQS) D e lta T R d iff v O H d iff(A C ) O v O L d iff(A C ) D e lta T F d iff < Figure 6.4.4: Differential Output Slew Rate Definition > Rev. 0.1 / Dec 2008 27 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C DDR3-800 Parameter Differential Output Slew Rate Symbol Min SRQdiff 5 DDR3-1066 Min 5 DDR3-1333 Min 5 DDR3-1600 Min TBD Max 10 Max 10 Max 10 Max 10 Units V/ns ***Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) diff: Differential Signals For Ron = RZQ/7 setting < Table 6.6.4: Differential Output Slew Rate > 6.5 Overshoot and Undershoot Specifications 6.5.1 Address and Control Overshoot and Undershoot Specifications Description Maximum peak amplitude allowed for overshoot area (see Figure) Maximum peak amplitude allowed for undershoot area (see Figure) Maximum overshoot area above VDD (See Figure) Maximum undershoot area below VSS (See Figure) Specification DDR3-800 0.4V 0.4V 0.67 V-ns 0.67 V-ns DDR3-1066 0.4V 0.4V 0.5 V-ns 0.5 V-ns DDR3-1333 0.4V 0.4V 0.4 V-ns 0.4 V-ns DDR3-1600 0.4V 0.4V 0.33 V-ns 0.33 V-ns < Table 6.5.1: AC Overshoot/Undershoot Specification for Address and Control Pins > < Figure 6.5.1: Address and Control Overshoot and Undershoot Definition > Maximum Amplitude Overshoot Area Volts (V) VDD VSS Undershoot Area Maximum Amplitude Time (ns) Rev. 0.1 / Dec 2008 28 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 6.5.2 Clock,Data,Strobe and Mask Overshoot and Undershoot Specifications Specification DDR3-800 0.4V 0.4V 0.25 V-ns 0.25 V-ns DDR3-1066 0.4V 0.4V 0.19 V-ns 0.19 V-ns DDR3-1333 0.4V 0.4V 0.15 V-ns 0.15 V-ns DDR3-1600 0.4V 0.4V 0.13 V-ns 0.13 V-ns Description Maximum peak amplitude allowed for overshoot area (see Figure) Maximum peak amplitude allowed for undershoot area (see Figure) Maximum overshoot area above VDDQ (See Figure) Maximum undershoot area below VSSQ (See Figure) < Table 6.5.2: AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask > M a x im u m A m p litu d e O v e rsh o o t A re a V o lts (V ) VDDQ VSSQ U n d e rsh o o t A re a M a x im u m A m p litu d e T im e (n s) C lo c k , D a ta S tro b e a n d M a sk O v e rsh o o t a n d U n d e rsh o o t D e fin itio n < Figure 6.5.2: Clock, Data, Strobe and Mask Overshoot and Undershoot Definition > Rev. 0.1 / Dec 2008 29 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 6.6 Pin Capacitance Parameter Input/output capacitance (DQ, DM, DQS, DQS#, TDQS, TDQS#) Input capacitance, CK and CK# Input capacitance delta CK and CK# Input capacitance (All other input-only pins) Input capacitance delta, DQS and DQS# Input capacitance delta (All CTRL input-only pins) Symbol DDR3-800 Min 1.5 Max 3.0 DDR3-1066 DDR3-1333 DDR3-1600 Min 1.5 Max 3.0 Min 1.5 Max 2.5 Min TBD Max TBD Units Notes CIO CCK CDCK CI CDDQS CDI_CTRL pF 1,2,3 TBD 0 TBD 0 -0.5 -0.5 -0.5 1.6 0.15 1.5 0.20 0.3 0.5 0.3 TBD 0 TBD 0 -0.5 -0.5 -0.5 1.6 0.15 1.5 0.20 0.3 0.5 0.3 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD pF pF pF pF pF pF pF 2,3,5 2,3,4 2,3,6 2,3,12 2,3,7,8 2,3,9, 10 2,3,11 Input capacitance delta CDI_ADD_ (All ADD/CMD input-only pins) CMD Input/output capacitance delta (DQ, DM, DQS, DQS#) Notes: CDIO 1. TDQS/TDQS# are not necessarily input function but since TDQS is sharing DM pin and the parasitic characterization of TDQS/TDQS# should be close as much as possible, Cio&Cdio requirement is applied (recommend deleting note or changing to “Although the DM, TDQS and TDQS# pins have different functions, the loading matches DQ and DQS.”) 2. This parameter is not subject to production test. It is verified by design and characterization. Input capacitance is measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE, RESET# and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK#. 5. The minimum CCK will be equal to the minimum CI. 6. Input only pins include: ODT, CS, CKE, A0-A15, BA0-BA2, RAS#, CAS#, WE#. 7. CTRL pins defined as ODT, CS and CKE. 8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK#)) 9. ADD pins defined as A0-A15, BA0-BA2 and CMD pins are defined as RAS#, CAS# and WE#. 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK#)) 11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS#)) 12. Absolute value of CIO(DQS) - CIO(DQS#) Rev. 0.1 / Dec 2008 30 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 6.7 IDD Specifications(TCASE: 0 to 95oC) 512MB, 64M x 64 U-DIMM: HMT164U6AFP6C Symbol IDD0 IDD1 IDD2P(F) IDD2P(S) IDD2Q IDD2N IDD3P IDD3N IDD4W IDD4R IDD5B IDD6(D) IDD6(S) IDD7 DDR3 800 360 480 100 40 180 200 140 220 700 700 740 40 24 1300 DDR3 1066 420 540 120 40 240 240 180 280 880 860 780 40 24 1420 DDR3 1333 480 580 140 40 280 300 200 340 1060 1020 840 40 24 1720 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1 1 note 1GB, 128M x 64 U-DIMM: HMT112U6AFP8C Symbol IDD0 IDD1 IDD2P(F) IDD2P(S) IDD2Q IDD2N IDD3P IDD3N IDD4W IDD4R IDD5B IDD6(D) IDD6(S) IDD7 DDR3 800 640 760 200 80 360 400 280 440 1120 1040 1480 80 48 1800 DDR3 1066 760 880 240 80 480 480 360 560 1440 1320 1560 80 48 2000 DDR3 1333 840 960 280 80 560 600 400 680 1560 1680 1720 80 48 2440 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1 1 note Rev. 0.1 / Dec 2008 31 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 1GB, 128M x 72 U-DIMM: HMT112U7AFP8C Symbol IDD0 IDD1 IDD2P(F) IDD2P(S) IDD2Q IDD2N IDD3P IDD3N IDD4W IDD4R IDD5B IDD6(D) IDD6(S) IDD7 DDR3 800 720 855 225 90 405 450 315 495 1260 1170 1665 90 54 2025 DDR3 1066 855 990 270 90 540 540 405 630 1620 1485 1755 90 54 2250 DDR3 1333 945 1080 315 90 630 675 450 765 1755 1890 1935 90 54 2745 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1 1 note 2GB, 256M x 64 U-DIMM: HMT125U6AFP8C Symbol IDD0 IDD1 IDD2P(F) IDD2P(S) IDD2Q IDD2N IDD3P IDD3N IDD4W IDD4R IDD5B IDD6(D) IDD6(S) IDD7 DDR3 800 1040 1160 400 160 720 800 560 880 1520 1440 1880 160 96 2200 DDR3 1066 1240 1360 480 160 960 960 720 1120 1920 1800 2040 160 96 2480 DDR3 1333 1440 1560 560 160 1120 1200 800 1360 2160 2280 2320 160 96 3040 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1 1 note Rev. 0.1 / Dec 2008 32 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 2GB, 256M x 72 U-DIMM: HMT125U7AFP8C Symbol IDD0 IDD1 IDD2P(F) IDD2P(S) IDD2Q IDD2N IDD3P IDD3N IDD4W IDD4R IDD5B IDD6(D) IDD6(S) IDD7 DDR3 800 1170 1305 450 180 810 900 630 990 1710 1620 2115 180 108 2475 DDR3 1066 1395 1530 540 180 1080 1080 810 1260 2160 2025 2295 180 108 2790 DDR3 1333 1620 1755 630 180 1260 1350 900 1530 2430 2565 2610 180 108 3420 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1 1 note 6.7 IDD Measurement Conditions Within the tables provided further down, an overview about the IDD measurement conditions is provided as follows: Table 1 — Overview of Tables providing IDD Measurement Conditions and DRAM Behavior Measurement Conditions IDD0 and IDD1 IDD2N, IDD2Q, IDD2P(0), IDD2P(1) IDD3N and IDD3P IDD4R, IDD4W, IDD7 IDD7 for different Speed Grades and different tRRD, tFAW conditions IDD5B IDD6, IDD6ET Table number Table 5 on page 33 Table 6 on page 36 Table 7 on page 38 Table 8 on page 39 Table 9 on page 42 Table 10 on page 43 Table 11 on page 44 Within the tables about IDD measurement conditions, the following definitions are used: - LOW is defined as VIN = VIHAC(min.). - STABLE is defined as inputs are stable at a HIGH or LOW level. - FLOATING is defined as inputs are VREF = VDDQ / 2. - SWITCHING is defined as described in the following 2 tables. Rev. 0.1 / Dec 2008 33 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 2 — Definition of SWITCHING for Address and Command Input Signals SWITCHING for Address (row, column) and Command Signals (CS, RAS, CAS, WE) is defined as: If not otherwise mentioned the inputs are stable at HIGH or LOW during 4 clocks and change Address (row, column): then to the opposite value (e.g. Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax..... please see each IDDx definition for details Bank address: If not otherwise mentioned the bank addresses should be switched like the row/column addresses - please see each IDDx definition for details Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW} Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH,HIGH,HIGH} Define Command Background Pattern = D D D D D D D D D D D D... If other commands are necessary (e.g. ACT for IDD0 or Read for IDD4R), the Background Pattern Command is substituted by the respective CS, RAS, CAS, WE levels of the necessary command. See each IDDx definition for details and figures 1,2,3 as examples. Command (CS, RAS, CAS, WE): Table 3 — Definition of SWITCHING for Data (DQ) SWITCHING for Data (DQ) is defined as Data DQ is changing between HIGH and LOW every other data transfer (once per clock) for DQ signals, which means that data DQ is stable during one clock; see each IDDx definition for exceptions from this rule and for further details. See figures 1,2,3 as examples. NO Switching; DM must be driven LOW all the time Data (DQ) Data Masking (DM) Rev. 0.1 / Dec 2008 34 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Timing parameters are listed in the following table: Table 4 — Parameter Bin For IDD testing the following parameters are utilized. DDR3-800 5-5-5 5 12.5 50 37.5 12.5 x4/ x8 x16 x4/ x8 x16 40 50 10 10 90 110 160 tbd 6-6-6 6 15 52.5 37.5 15 40 50 10 10 90 110 160 tbd 2.5 6 11.25 48.75 37.5 11.25 37.5 50 7.5 10 90 110 160 tbd DDR3-1066 6-6-6 7-7-7 1.875 7 13.13 50.63 37.5 13.13 37.5 50 7.5 10 90 110 160 tbd 8 15 52.50 37.5 15 37.5 50 7.5 10 90 110 160 tbd 7 10.5 46.5 36 10.5 30 45 6.0 7.5 90 110 160 tbd 8-8-8 DDR3-1333 7-7-7 8-8-8 1.5 8 12 48 36 12 30 45 6.0 7.5 90 110 160 tbd 9 13.5 49.5 36 13.5 30 45 6.0 7.5 90 110 160 tbd 8 10 tbd tbd 10 30 40 6.0 7.5 90 110 160 tbd 9-9-9 DDR3-1600 8-8-8 9-9-9 1.25 9 11.25 tbd tbd 11.25 30 40 6.0 7.5 90 110 160 tbd 10 12.5 tbd tbd 12.5 30 40 6.0 7.5 90 110 160 tbd 101010 Unit ns clk ns ns ns ns ns ns ns ns ns ns ns ns tCKmin(IDD) CL(IDD) tRCDmin(IDD) tRCmin(IDD) tRASmin(IDD) tRPmin(IDD) tFAW(IDD) tRRD(IDD) tRFC(IDD) 512Mb Gb Gb Gb tRFC(IDD) - 1 tRFC(IDD) - 2 tRFC(IDD) - 4 The following conditions apply: - IDD specifications are tested after the device is properly initialized. - Input slew rate is specified by AC Parametric test conditions. - IDD parameters are specified with ODT and output buffer disabled (MR1 Bit A12). Rev. 0.1 / Dec 2008 35 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 5 — IDD Measurement Conditions for IDD0 and IDD1 IDD0 Operating Current 0 Current IDD1 Operating Current 1 -> One Bank Activate -> Read -> Precharge Figure 1 Name -> One Bank Activate -> Precharge Measurement Condition Timing Diagram Example CKE External Clock HIGH on HIGH on tCK tRC tRAS tRCD tRRD CL AL CS Command Inputs (CS,RAS, CAS, WE) tCKmin(IDD) tRCmin(IDD) tRASmin(IDD) n.a. n.a. n.a. n.a. HIGH between. Activate and Precharge Commands SWITCHING as described in Table 2 only exceptions are Activate and Precharge commands; example of IDD0 pattern: A0DDDDDDDDDDDDDD P0 (DDR3-800: tRAS = 37.5ns between (A)ctivate and (P)recharge to bank 0; Definition of D and D: see Table 2 tCKmin(IDD) tRCmin(IDD) tRASmin(IDD) tRCDmin(IDD) n.a. CL(IDD) 0 HIGH between Activate, Read and Precharge SWITCHING as described in Table 2; only exceptions are Activate, Read and Precharge commands; example of IDD1 pattern: A0DDDDR0DDDDDDDDD P0 (DDR3-800 -555: tRCD = 12.5ns between (A)ctivate and (R)ead to bank 0; Definition of D and D: see Table 2) Rev. 0.1 / Dec 2008 36 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 5 — IDD Measurement Conditions for IDD0 and IDD1 IDD0 Operating Current 0 Name -> One Bank Activate -> Precharge Row, Column Addresses Current IDD1 Operating Current 1 -> One Bank Activate -> Read -> Precharge in Table 2; Address Input A10 must be LOW all the time! bank address is fixed (bank 0) Read Data: output data switches every clock, which means that Read data is stable during one clock cycle. To achieve Iout = 0mA, the output buffer should be switched off by MR1 Bit A12 set to “1”. When there is no read data burst from DRAM, the DQ I/O should be FLOATING. Row addresses SWITCHING as described Row addresses SWITCHING as described in Table 2; Address Input A10 must be LOW all the time! Bank Addresses Data I/O bank address is fixed (bank 0) SWITCHING as described in Table 3 Output Buffer DQ,DQS / MR1 bit A12 ODT / MR1 bits [A6, A2] Burst length Active banks Idle banks Mode Register Bit 12 off / 1 disabled / [0,0] n.a. one ACT-PRE loop all other off / 1 disabled / [0,0] 8 fixed / MR0 Bits [A1, A0] = {0,0} one ACT-RD-PRE loop all other n.a. Precharge Power Down Mode / n.a. Rev. 0.1 / Dec 2008 37 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C T0 CK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T12 T14 T16 T18 BA[2:0] 000 000 3FF 000 3FF 000 3F ADDR_a[9:0] ADDR_b[10] ADDR_c[12:11] 00 11 00 11 00 CS RAS CAS WE CMD ACT D D# D# D RD D# D# D D D# D# D D D# PRE D D D# DQ DM 00110011 IDD1 Measurment Loop < Figure 1. IDD1 Example > (DDR3-800-555, 512Mb x8): Data DQ is shown but the output buffer should be switched off (per MR1 Bit A12 =”1”) to achieve Iout = 0mA. Address inputs are split into 3 parts. a. In DDR3, the MRS Bit 12 defines DLL on/off behaviour ONLY for precharge power down. There are 2 different Precharge Power Down states possible: one with DLL on (fast exit, bit 12 = 1) and one with DLL off (slow exit, bit 12 = 0). b. Because it is an exit after precharge power down, the valid commands are: Activate, Refresh, Mode-Register Set, Enter - Self Refresh Rev. 0.1 / Dec 2008 38 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 6 — IDD Measurement Conditions for IDD2N, IDD2P(1), IDD2P(0) and IDD2Q Current Name IDD2N IDD2P(1) a IDD2P(0) Precharge Power Down Current Slow Exit MRS A12 Bit = 0 IDD2Q Precharge Quiet Standby Current Precharge Power Precharge Standby Down Current Current Fast Exit MRS A12 Bit = 1 Measurement Condition Timing Diagram Example CKE External Clock Figure 2 HIGH on LOW on LOW on HIGH on tCK tRC tRAS tRCD tRRD CL AL CS Bank Address, Row Addr. and Command Inputs Data inputs Output Buffer DQ,DQS / MR1 bit A12 ODT / MR1 bits [A6, A2] Burst length Active banks Idle banks Precharge Power Down Mode / Mode Register Bit a a. b. tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. HIGH SWITCHING as described in Table 2 SWITCHING off / 1 disabled / [0,0] n.a. none all n.a. tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. STABLE STABLE FLOATING off / 1 disabled / [0,0] n.a. none all Fast Exit / 1 (any valid command after tXPb) tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. STABLE STABLE FLOATING off / 1 disabled / [0,0] n.a. none all tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. HIGH STABLE FLOATING off / 1 disabled / [0,0] n.a. none all Slow Exit / 0 Slow exit (RD and n.a. ODT commands must satisfy tXPDLL-AL) Rev. 0.1 / Dec 2008 39 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C T0 CK T1 T2 T3 T4 T5 T6 T7 T8 T9 BA[2:0] 0 7 0 ADDR[12:0] 0 7 0 CS RAS CAS WE CMD D# D# D D D# D# D D D# D# DQ[7:0] FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF DM (DDR3-800-555, 512Mb x8) Rev. 0.1 / Dec 2008 40 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 7 — IDD Measurement Conditions for IDD3N and IDD3P(fast exit) IDD3N Active Standby Current Measurement Condition Current Name IDD3P Active Power-Down Currenta Always Fast Exit Timing Diagram Example CKE External Clock Figure 2 HIGH on LOW on tCK tRC tRAS tRCD tRRD CL AL CS Addr. and cmd Inputs Data inputs Output Buffer DQ,DQS / MR1 bit A12 ODT / MR1 bits [A6, A2] Burst length Active banks Idle banks Precharge Power Down Mode / Mode Register Bit a tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. HIGH SWITCHING as described in Table 2 SWITCHING as described in Table 3 off / 1 disabled / [0,0] n.a. all none n.a. tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. STABLE STABLE FLOATING off / 1 disabled / [0,0] n.a. all none n.a. (Active Power Down Mode is always “Fast Exit” with DLL on a. DDR3 will offer only ONE active power down mode with DLL on (-> fast exit). MRS bit 12 will not be used for active power down. Instead bit 12 will be used to switch between two different precharge power down modes. Rev. 0.1 / Dec 2008 41 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 8 — IDD Measurement Conditions for IDD4R, IDD4W and IDD7 Current Name IDD4R Operating Current Burst Read IDD4W Operating Current Burst Write IDD7 All Bank Interleave Read Current Measurement Condition Timing Diagram Example CKE External Clock Figure 3 HIGH on HIGH on HIGH on tCK tRC tRAS tRCD tRRD CL AL CS Command Inputs (CS, RAS, CAS, WE) tCKmin(IDD) n.a. n.a. n.a. n.a. CL(IDD) 0 HIGH btw. valid cmds SWITCHING as described in Table 2; exceptions are Read commands => IDD4R Pattern: tCKmin(IDD) n.a. n.a. n.a. n.a. CL(IDD) 0 HIGH btw. valid cmds SWITCHING as described in Table 2; exceptions are Write commands => IDD4W Pattern: tCKmin(IDD) tRCmin(IDD) tRASmin(IDD) tRCDmin(IDD) tRRDmin(IDD) CL(IDD) tRCDmin - 1 tCK HIGH btw. valid cmds For patterns see Table 9 R0DDDR1DDDR2DDDR3.DD W0DDDW1DDDW2DDDW3 DDD W4... D R4..... Rx = Read from bank x; Wx = Write to bank x; Definition of D and D: see Definition of D and D: see Table 2 Table 2 Rev. 0.1 / Dec 2008 42 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 8 — IDD Measurement Conditions for IDD4R, IDD4W and IDD7 Current Name IDD4R Operating Current Burst Read column addresses IDD4W Operating Current Burst Write column addresses SWITCHING as described in Table 2; Address Input A10 must be LOW all the time! IDD7 All Bank Interleave Read Current Row, Column Addresses SWITCHING as described in Table 2; Address Input A10 must be LOW all the time! STABLE during DESELECTs Bank Addresses bank address cycling (0 -> 1 - bank address cycling (0 -> 1 > 2 -> 3...) Seamless Read Data Burst (BL8): output data switches every clock, which means that Read data is stable during one clock cycle. To achieve Iout = 0mA the output buffer should be switched off by MR1 Bit A12 set to “1”. > 2 -> 3...) bank address cycling (0 -> 1 > 2 -> 3...), see pattern in Table 9 Read Data (BL8): output data switches every clock, which means that Read data is stable during one clock cycle. To achieve Iout = 0mA the Seamless Write Data Burst (BL8): input data switches every clock, which means that Write data is stable during one clock cycle. DM is low all the time. DQ I/O output buffer should be switched off by MR1 Bit A12 set to “1”. Output Buffer DQ,DQS / MR1 bit A12 ODT / MR1 bits [A6, A2] Burst length Active banks Idle banks Precharge Power Down Mode / Mode Register Bit n.a. n.a. n.a. disabled / [0,0] 8 fixed / MR0 Bits [A1, A0] = {0,0} all none disabled / [0,0] 8 fixed / MR0 Bits [A1, A0] = {0,0} all none disabled / [0,0] 8 fixed / MR0 Bits [A1, A0] = {0,0} all, rotational none off / 1 off / 1 off / 1 Rev. 0.1 / Dec 2008 43 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C CK BA[2:0] 000 001 010 011 ADDR[12:0] 000 3FF 000 3FF ADDR_b[10] ADDR_c[12:11] 00 11 00 11 CS RAS CAS WE CMD[2:0] RD D D# D# RD D D# D# RD D D# D# RD DQ[7:0] 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF DM -> Start of Measurement Loop < Figure 3. IDD4R Example > (DDR3-800-555, 512Mb x8): data DQ is shown but the output buffer should be switched off (per MR1 Bit A12=”1”) to achieve Iout = 0mA. Address inputs are split into 3 parts. Rev. 0.1 / Dec 2008 44 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 9 — Speed Mb/s IDD7 Pattern for different Speed Grades and different tRRD, tFAW conditions Bin Org. tFAW [ns] tFAW [CLK] tRRD [ns] tRRD IDD7 Patterna [CLK] (Note this entire sequence is repeated.) all 800 all x4/x8 x16 40 50 16 20 10 10 4 4 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D DDDD A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D DDDD A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D A4 RA4 D D D D A5 RA5 D D D D A6 RA6 D D D D A7 RA7 D D D D D D D A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D DDDD A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D D D D D D D D A4 RA4 D D D A5 RA5 D D D A6 RA6 D D D A7 RA7 D D D D D D D D D D D D D A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D D A4 RA4 D D D A5 RA5 D D D A6 RA6 D D D A7 RA7 D D D D D D D A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D D D A4 RA4 D D D D A5 RA5 D D D D A6 RA6 D D D D A7 RA7 D D D D D D D D D DDD all 1066 all x4/x8 37.5 20 7.5 4 x16 50 27 10 6 all 1333 all x4/x8 30 20 6 4 x16 45 30 7.5 5 all 1600 all x4/x8 30 24 6 5 x16 40 32 7.5 6 a. A0 = Activation of Bank 0; RA0 = Read with Auto-Precharge of Bank 0; D = Deselect Rev. 0.1 / Dec 2008 45 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 10 — IDD Measurement Conditions for IDD5B Current IDD5B Burst Refresh Current Name Measurement Condition CKE External Clock HIGH on tCK tRC tRAS tRCD tRRD tRFC CL AL CS Addr. and cmd Inputs Data inputs Output Buffer DQ,DQS / MR1 bit A12 ODT / MR1 bits [A6, A2] Burst length Active banks Idle banks Precharge Power Down Mode / Mode Register Bit tCKmin(IDD) n.a. n.a. n.a. n.a. tRFCmin(IDD) n.a. n.a. HIGH btw. valid cmds SWITCHING SWITCHING off / 1 disabled / [0,0] n.a. Refresh command every tRFC=tRFCmin none n.a. Rev. 0.1 / Dec 2008 46 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 11 — IDD Measurement Conditions for IDD6 and IDD6ET Current Name IDD6 Self-Refresh Current Normal Temperature Range TCASE = 0. 85 °C Measurement Condition IDD6ET Self-Refresh Current Extended Temperature Range a TCASE = 0. 95 °C Temperature Auto Self Refresh (ASR) / MR2 Bit A6 Self Refresh Temperature Range (SRT) / MR2 Bit A7 CKE External Clock TCASE = 85 °C Disabled / “0” TCASE = 95 °C Disabled / “0” Normal / “0” LOW OFF; CK and CK at LOW n.a. n.a. n.a. n.a. n.a. n.a. n.a. FLOATING FLOATING FLOATING FLOATING FLOATING off / 1 disabled / [0,0] n.a. all during self-refresh actions all btw. Self-Refresh actions n.a. Extended / “1” LOW OFF; CK and CK at LOW n.a. n.a. n.a. n.a. n.a. n.a. n.a. FLOATING FLOATING FLOATING FLOATING FLOATING off / 1 disabled / [0,0] n.a. all during self-refresh actions all btw. Self-Refresh actions n.a. tCK tRC tRAS tRCD tRRD CL AL CS Command Inputs (RAS, CAS, WE) Row, Column Addresses Bank Addresses Data I/O Output Buffer DQ,DQS / MR1 bit A12 ODT / MR1 bits [A6, A2] Burst length Active banks Idle banks Precharge Power Down Mode / MR0 bit A12 a. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material. Rev. 0.1 / Dec 2008 47 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 7. Electrical Characteristics and AC Timing 7.1 Refresh Parameters by Device Density Parameter Symbol 512Mb 1Gb 2Gb 4Gb 8Gb Units REF command to ACT or REF command time Average periodic refresh interval tREFI tRFC 90 110 160 300 350 ns 0 ×C < TCASE < 85 ×C 85 ×C < TCASE < 95 ×C 7.8 3.9 7.8 3.9 7.8 3.9 7.8 3.9 7.8 3.9 ms ms 7.2 DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin DDR3 800 Speed Bin CL - nRCD - nRP Parameter Symbol min DDR3-800D 5-5-5 max min DDR3-800E 6-6-6 max Unit Notes Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CL = 6 CWL = 5 CWL = 5 tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) 12.5 12.5 12.5 50 37.5 2.5 2.5 5, 6 5 20 — — — 9 * tREFI 3.3 3.3 15 15 15 52.5 37.5 20 — — — 9 * tREFI ns ns ns ns ns ns ns 1)2)3)4) 1)2)3) Reserved 2.5 6 5 3.3 Supported CL Settings Supported CWL Settings nCK nCK Rev. 0.1 / Dec 2008 48 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C DDR3 1066 Speed Bin CL - nRCD - nRP Parameter Symbol DDR3-1066E 6-6-6 min max DDR3-1066F 7-7-7 min max DDR3-1066G 8-8-8 min max Unit Note Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 6 CWL = 5 CL = 6 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 11.25 11.25 11.25 48.75 37.5 2.5 20 — — — 9 * tREFI 3.3 13.125 13.125 13.125 50.625 37.5 20 — — — 9 * tREFI 15 15 15 52.5 37.5 20 — — — 9 * tREFI ns ns ns ns ns ns ns ns ns ns ns ns ns 1)2)3)4)6) 4) 1)2)3)6) 1)2)3)4) 4) 1)2)3)4) 4) 1)2)3) Reserved Reserved 2.5 3.3 Reserved Reserved 2.5 3.3 Reserved 2.5 1.875 3.3 < 2.5 Reserved Reserved 1.875 < 2.5 Reserved Reserved Reserved Reserved 1.875 < 2.5 6, 8 5, 6 CL = 7 Reserved 1.875 < 2.5 CL = 8 Reserved 1.875 < 2.5 Reserved 1.875 < 2.5 Supported CL Settings Supported CWL Settings 5, 6, 7, 8 5, 6 6, 7, 8 5, 6 nCK nCK Rev. 0.1 / Dec 2008 49 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C DDR3 1333 Speed Bin CL - nRCD - nRP Parameter Symbol DDR3-1333F (optional) 7-7-7 min max DDR3-1333G DDR3-1333H 8-8-8 min max 9-9-9 min max DDR3-1333J (optional) Unit 10-10-10 min max Note Internal read command to first ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 5 CL = 6 CWL = 6 CWL = 7 CWL = 5 CL = 7 CWL = 6 CWL = 7 CWL = 5 CL = 8 CWL = 6 CWL = 7 CL = 9 CWL = 7 tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 10.5 10.5 10.5 46.5 36 2.5 2.5 1.875 20 — — — 9* tREFI 3.3 3.3 < 2.5 12 12 12 48 36 2.5 2.5 20 — — — 9* tREFI 3.3 3.3 13.5 13.5 13.5 49.5 36 20 — — — 9* tREFI 15 15 15 51 36 20 — — — 9* tREFI ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1,2,3,4,7 4 1,2,3,7 1,2,3,4,7 4 4 1,2,3,4,7 1,2,3,4 4 1,2,3,7 1,2,3,4 4 1,2,3,4 4 1,2,3 5 Reserved Reserved 2.5 3.3 Reserved Reserved Reserved Reserved Reserved Reserved 1.875 < 2.5 Reserved Reserved 1.5 1.5