240pin DDR3 SDRAM Registered DIMM
DDR3 SDRAM Registered DIMM Based on 1Gb A version
HMT112R7AFP8C HMT125R7AFP8C HMT125R7AFP4C HMT151R7AFP4C HMT151R7AFP8C HMT31GR7AMP4C
** Contents may be changed at any time without any notice.
Rev. 0.4 /Jul. 2009
1
Revision History
Revision No. 0.1 0.2 0.3 0.4 History Initial Release Added IDD Specification Reflected the actual measurement, nonphysical change (max thickness) Added Environment Parameter Draft Date 2008-8 2008-11 2009-02 2009-07 Remark
Rev. 0.4 / Jul. 2009
2
Table of Contents
1. Description 1.1 Device Features and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Key Parameters 1.3 Speed Grade 1.4 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 1GB, 128Mx72 Module(1Rank of x8) 3.2 2GB, 256Mx72 Module(2Rank of x8) 3.3 2GB, 256Mx72 Module(1Rank of x4) 3.4 4GB, 512Mx72 Module(2Rank of x4) 3.5 4GB, 512Mx72 Module(4Rank of x8) 3.6 8GB, 1Gx72 Module(4Rank of x4) 4. Environment Parameter 5. Input/Output Capacitance & AC Parametrics 6. IDD Specifications 7. DIMM Outline Diagram 7.1 1GB, 128Mx72 Module(1Rank of x8) 7.2 2GB, 256Mx72 Module(2Rank of x8) 7.3 2GB, 256Mx72 Module(1Rank of x4) 7.4 4GB, 512Mx72 Module(2Rank of x4) 7.5 4GB, 512Mx72 Module(4Rank of x8) 7.6 8GB, 1Gx72 Module(4Rank of x4)
Rev. 0.4 / Jul. 2009
3
1. Description
This Hynix DDR3 SDRAM Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb A generation. These are intended for use as main memory in server and workstation systems, providing a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition.
1.1 Product Features & Ordering Information
1.1.1 Features
• VDD=VDDQ=1.5V • VDDSPD=3.3V to 3.6V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and /DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11) supported • Programmable additive latency 0, CL-1, and CL-2 sup ported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8 banks • 8K refresh cycles /64ms • DDR3 SDRAM Package: JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16) with support balls • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • TDQS (Termination Data Strobe) supported (x8 device based only) • Write Levelization supported • Auto Self Refresh supported • 8 bit pre-fetch • Heat Spreader installed for 4GB/8GB • SPD with Integrated TS of Class B
* This product in compliance with the directive petaining of RoHS.
1.1.2 Ordering Information
# of DRAMs 9 18 18 36 36 72 # of ranks 1 2 1 2 4 4
Part Number HMT112R7AFP8C-G7/H9 HMT125R7AFP8C-G7/H9 HMT125R7AFP4C-G7/H9 HMT151R7AFP4C-G7/H9 HMT151R7AFP8C-G7/H9 HMT31GR7AMP4C-G7/H9
Density 1GB 2GB 2GB 4GB 4GB 8GB
Organization 128Mx72 256Mx72 256Mx72 512Mx72 512Mx72 1Gx72
Materials Lead free Lead free Lead free Lead free Lead free Lead free
FDHS X X X O O O
* Please Contact local sales administrator for more details of part number Rev. 0.4 / Jul. 2009 4
1.2 Key Parameters
MT/s Grade tCK(min) CAS Latency tRCD(min) tRP(min) tRAS(min) tRC(min) CL-tRCD-tRP DDR3-1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7 DDR3-1333 Unit -H9 1.5 9 13.5 13.5 36 49.5 9-9-9 ns tCK ns ns ns ns tCK
1.3 Speed Grade
Frequency [MHz] Grade CL5 -G7 -H9 CL6 800 800 CL7 1066 1066 CL8 1066 1066 1333 1333 CL9 CL10 Remark
1.4 Address Table
1GB(1Rx8) Organization Refresh Method Row Address Column Address Bank Address Page Size # of Rank # of Device
Rev. 0.4 / Jul. 2009
2GB(2Rx8) 256M x 72 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 2 18
2GB(1Rx4) 256M x 72 8K/64ms A0-A13 A0-A9,A11 BA0-BA2 1KB 1 18
4GB(2Rx4) 512M x 72 8K/64ms A0-A13 A0-A9,A11 BA0-BA2 1KB 2 36
4GB(4Rx8) 512M x 72 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 4 36
8GB(4Rx4) 1G x 72 8K/64ms A0-A13 A0-A9,A11 BA0-BA2 1KB 4 72
5
128M x 72 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 1 9
2. Pin Architecture
2.1 Pin Definition
Pin Name A0–A9,A11 A13-A15 BA0–BA2 RAS CAS WE S0–S3 CKE0–CKE1 ODT0–ODT1 DQ0–DQ63 CB0–CB7 DQS0–DQS8 DQS0–DQS8 Description Address Inputs SDRAM Bank Addresses Row Address Strobe Column Address Strobe Write Enable Chip Selects Clock Enables On-die termination Inputs Data Input/Output Data Check Bits Input/Output Data Strobes Data Strobes, Negative Line Num -ber 14 3 1 1 1 4 2 2 64 8 9 9 9 Pin Name A10/AP A12/BC SCL SDA SA0–SA2 Par_in ERR_OUT EVENT TEST RESET VDD VSS VREFDQ VREFCA VTT 9 1 1 VDDSPD CK1 CK1 Description Address Input/Autoprecharge Address Input/Autoprecharge Serial Presence Detect (SPD) Clock Input SPD Data Input/Output SPD Address Inputs Parity Bit For The Address and Control Bus Parity Error Found on the Address and Control Bus Reserved for Optional Hardware temperature Sensing Memory Bus Test Tool (Not Connected and Not Usable on DIMMs) Register and SDRAM control pin Power Supply Ground Reference Voltage for DQ Reference Voltage for CA Termination Voltage SPD Power Clock Input, positive line Clock Input, negative line Num -ber 1 1 1 1 3 1 1 1 1 1 22 59 1 1 4 1 1 1
Data Masks DM0–DM8 DQS9-DQS17 Data Strobes TDQS9-TDQS17 Termination Data Strobes DQS9–DQS17 Data Strobes, Negative Line TDQS9–TDQS17 Termination Data Strobes CK0 CK0 Clock Input, positive line Clock Input, positive Line
Rev. 0.4 / Jul. 2009
6
2.2 Input/Output Functional Description
Symbol CK0 CK0 CK1 CK1 Type IN IN IN IN Polarity Positive Line Negative Line Function Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock Driver. Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver.
Positive Line Terminated but not used on RDIMMs Negative Line Terminated but not used on RDIMMs CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank) Enables the command decoders for the associated rank of SDRAM when low and disables decoders.When decoders are disabled, new commands are ignored and previous operations continue.Other combinations of these input signals perform unique functions, including disabling all outputs (except CKE and ODT) of the register(s) on the DIMM or accessing internal control words in the register device(s).For modules with two registers,S[3:2] operate similarly to S[1:0] for the second set of register outputs or register control words. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. On-Die Termination control signals Reference voltage for DQ0-DQ63 and CB0-CB7 Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In, ODT0 and ODT1. Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. Selects which SDRAM bank of eight is activated. BA0-BA2 define to which bank an Active, Read, Write or Precharge command is being applied.Bank address also determines mode register is to be accessed during an MRS cycle. Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank.A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH).If only one bank is to be precharged, the bank is selected by BA.A12 is also utilized for BL 4/8 identification for “BL on the fly” during CAS command. The address inputs also provide the op-code during Mode Register Set commands. Data and Check Bit Input/Output pins.
CKE0–CKE1
IN
Active High
S0–S3
IN
Active Low
RAS, CAS, WE ODT0–ODT1 VREFDQ VREFCA
IN IN Supply Supply
Active Low Active High
VDDQ
Supply
BA0–BA2
IN
—
A0-A9 A10/AP A11 A12/BC A13-A15
IN
—
DQ0–DQ63, CB0–CB7
I/O
—
Rev. 0.4 / Jul. 2009
7
Symbol DM0–DM8 VDD, VSS VTT DQS0-DQS17 DQS0–DQS17
Type IN Supply Supply I/O I/O
Polarity Active High
Function Masks write data when high, issued concurrently with input data. Power and ground for the DDR3 SDRAM input buffers, and core logic. Termination Voltage for Address/Command/Control/Clock nets.
Positive Edge Positive line of the differential data strobe for input and output data. Negative Edge Negative line of the differential data strobe for input and output data. TDQS/TDQS is applicable for x8 DRAMs only. WHen enabled via Mode Register A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used.x4/x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1. — These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external resistor may be connected from the SDA bus line to VDDSPD to act as a pullup on the system board. This signal is used to clock data into and out of the SPD EEPROM. An external resistor may be connected from the SCL bus time to VDDSPD to act as a pull up. Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation. Active Low This signal indicates that a thermal event has been detected in the thermal sensing device. The system should guarantee the electrical level requirement is met for the EVENT pin on TS/SPD part. The RESET pin is connected to the RESET pin on the register and to the RESET pin on the DRAM. When low, all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register(s) will be set to low level (the Clock Driver will remain synchronized with the input clock) Parity bit for the Address and Control bus.(“1”:Odd, “0”:Even) Parity error detected on the Address and Control bus.A resistor may be connected from Err_Out bus line to VDD on the system planar to act as a pull up. Used by memory bus analysis tools (unused (NC) on memory DIMMs)
TDQS9-TDQS17 TDQS9-TDQS17
OUT
SA0–SA2
SDA
I/O
—
SCL
IN
—
VDDSPD
Supply OUT (open drain)
EVENT
RESET
IN
Par_In Err_Out TEST
IN OUT (open drain)
Rev. 0.4 / Jul. 2009
8
2.3 Pin Assignment
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Front Side (left 1–60) VREFDQ VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 Pin # 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 Back Side (right 121–180) VSS DQ4 DQ5 VSS DM0,DQS9,TDQS9 NC, DQS9,TDQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1,DQS10,TDQS10 NC,DQS10,TDQS10 VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2,DQS11,TDQS11 NC,DQS11,TDQS11 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3,DQS12,TDQS12 NC, DQS12,TDQS12 Pin # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 Front Side (left 61–120) A2 VDD NC, CK1 NC, CK1 VDD VDD VREFCA Par_in, NC VDD A10 / AP BA0 VDD WE CAS VDD S1, NC ODT1, NC VDD S2, NC VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 Pin # 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 Back Side (right 181–240) A1 VDD VDD CK0 CK0 VDD EVENT, NC A0 VDD BA1 VDD RAS S0 VDD ODT0 A13 VDD S3, NC VSS DQ36 DQ37 VSS DM4,DQS13,TDQS13 NC, DQS13,TDQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5,DQS14,TDQS14 NC, DQS14,TDQS14
NC = No Connect; RFU = Reserved Future Use
Rev. 0.4 / Jul. 2009 9
Pin # 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Front Side (left 1–60) DQS3 VSS DQ26 DQ27 VSS CB0, NC CB1, NC VSS DQS8 DQS8 VSS CB2, NC CB3, NC VSS VTT, NC KEY VTT, NC CKE0 VDD BA2 Err_Out, NC VDD A11 A7 VDD A5 A4 VDD
Pin # 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
Back Side (right 121–180) VSS DQ30 DQ31 VSS CB4, NC CB5, NC VSS DM8,DQS17,TDQS17 NC NC,DQS17,TDQS17 VSS CB6, NC CB7, NC VSS NC(TEST) RESET KEY CKE1, NC VDD A15 A14 VDD A12 / BC A9 VDD A8 A6 VDD A3
Pin # 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Front Side (left 61–120) DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SA0 SCL SA2 VTT
Pin # 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
Back Side (right 181–240) VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6,DQS15,TDQS15 NC, DQS15,TDQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7,DQS16,TDQS16 NC, DQS16,TDQS16 VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT
NC = No Connect; RFU = Reserved Future Use
Rev. 0.4 / Jul. 2009
10
3. Functional Block Diagram
3.1 1GB, 128Mx72 Module(1Rank of x8)
A[N:O]A /BA[N:O]A A[N:O]B /BA[N:O]B ZQ RODT0A RS0A RRASA RS0B RRASB RODT0B ODT ODT PCK0A RCKE0A PCK0B RCKE0B CK CKE CK CKE RCASA RCASB PCK0A PCK0B RWEA RWEB
A[N:O]/BA[N:O]
D8
ODT CK CKE WE CK
D4
CAS WE CK
A[O:N]/BA[N:O]
D3
ODT CK CKE WE CK
D5
WE CK
RAS
CAS
CS
A[O:N]/BA[N:O]
D2
ODT CK CKE WE CK
D6
ODT CK CKE WE CK
RAS
CAS
CS
A[N:O]/BA[N:O]
D1
ODT CK CKE WE CK
D7
ODT CK CKE WE CK
A[N:O]/BA[N:O]
DQS1 DQS1 DM1/DQS10 DQS10 DQ[15:8]
DQS DQS TDQS TDQS DQ [7:0] RAS CAS CS
ZQ
DQS7 DQS7 DM7/DQS16 DQS16 DQ[63:56]
DQS DQS TDQS TDQS DQ [7:0] RAS CAS CS
A[O:N]/BA[N:O]
ZQ
DQS2 DQS2 DM2/DQS11 DQS11 DQ[23:16]
DQS DQS TDQS TDQS DQ [7:0]
ZQ
DQS6 DQS6 DM6/DQS15 DQS15 DQ[55:48]
DQS DQS TDQS TDQS DQ [7:0]
RAS
CAS
CS
A[O:N]/BA[N:O] ZQ
DQS3 DQS3 DM3/DQS12 DQS12 DQ[31:24]
DQS DQS TDQS TDQS DQ [7:0]
ZQ
DQS5 DQS5 DM5/DQS14 DQS14 DQ[47:40]
DQS DQS TDQS TDQS DQ [7:0] RAS CAS CS
A[O:N]/BA[O:N] ZQ
DQS8 DQS8 DM8/DQS17 DQS17 CB[7:0]
DQS DQS TDQS TDQS DQ [7:0] RAS CAS CS
ZQ
DQS4 DQS4 DM4/DQS13 DQS13 DQ[39:32]
DQS DQS TDQS TDQS DQ [7:0] RAS CS
VDDSPD VDD VTT VREFCA VREFDQ VSS
SPD
D0–D8
D0–D8 D0–D8 D0–D8
D0
ODT CK CKE WE CK
A[N:O]/BA[N:O]
DQS0 DQS0 DM0/DQS9 DQS9 DQ[7:0]
DQS DQS TDQS TDQS DQ [7:0] RAS CAS CS
ZQ
Vtt
Note:
1.DQ-to-I/O wiring may be changed within byte. 2.ZQ resistors are 240Ω ± 1%.For all other resistor values refer to the appropriate wiring diagram.
Vtt
S0 S1 BA[N:0] A[N:0] RAS CAS WE CKE0 ODT0 CK0 CK0 CK0 CK0 PAR_IN
120Ω ± 1% 120Ω ± 1%
1: 2 R E G I S T E R / P L L
OERR RST
RS0A → CS0: SDRAMs D[3:0], D8 RS0B → CS0: SDRAMs D[7:4] RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D8 RBA[N:0]A → BA[N:0]: SDRAMs D[7:4] RA[N:0]A → A[N:0]: SDRAMs D[3:0], D8 RA[N:0]A → A[N:0]: SDRAMs D[7:4] RRASA → RAS: SDRAMs D[3:0], D8 RRASA → RAS: SDRAMs D[7:4] RCASA → CAS: SDRAMs D[3:0], D8 RCASA → CAS: SDRAMs D[7:4] RWEA → WE: SDRAMs D[3:0], D8 RWEA → WE: SDRAMs D[7:4] RCKE0A → CKE0: SDRAMs D[3:0], D8 RCKE0B → CKE0: SDRAMs D[7:4] RODT0A → ODT0: SDRAMs D[3:0], D8 RODT0B → ODT0: SDRAMs D[7:4] PCK0A → CK: SDRAMs D[3:0], D8 PCK0B → CK: SDRAMs D[7:4] PCK0A → CK: SDRAMs D[3:0], D8 PCK0B → CK: SDRAMs D[7:4] Err_Out
VDDSPD EVENT SCL SDA
VDDSPD
SA0
SA0 SA1 SA2 VSS
EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA
Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative
RST: SDRAMs D[8:0] S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 330Ω resistor to ground
RESET
Rev. 0.4 / Jul. 2009
11
A[N:O]A /BA[N:O]A
RODT1A
A[N:O]B /BA[N:O]B
3.2 2GB, 256Mx72 Module(2Rank of x8) - page1
RODT0A RODT0B PCK0A RCKE0A PCK0B RCKE0B PCK1A RCKE1A RCASA RS0A RRASA RS0B RRASB RCASB PCK0A PCK1A PCK0B RWEA RWEB RS1A
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D8
ODT CAS CK CKE WE CK
D17
ODT CK CKE CAS WE CK
D4
ODT CAS CK CKE WE CK
D13
ODT ODT ODT ODT CK CKE CK CKE CK CKE CK CKE CAS WE CK
RAS
RAS
RAS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D3
ODT CAS CK CKE WE CK
D12
ODT CAS CK CKE WE CK
D5
ODT CAS CK CKE WE CK
D14
CAS WE CK
RAS
RAS
RAS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D2
ODT CAS CK CKE WE CK
D11
ODT CK CKE CAS WE CK
D6
ODT CAS CK CKE WE CK
D15
CAS WE CK
RAS
RAS
RAS
A[O:N]/BA[N:O]
A[O:N]/BA[N:O]
A[N:O]/BA[N:O]
D1
ODT CAS CK CKE WE CK
D10
ODT CAS CK CKE WE CK
D7
ODT CAS CK CKE WE CK
D16
CAS WE CK
RAS
RAS
RAS
A[N:O]/BA[N:O]
D0
ODT CAS CK CKE WE CK
D9
ODT CAS CK CKE WE CK
RAS
RAS
ZQ
CS
ZQ
CS
A[N:O]/BA[N:O]
DQS0 DQS0 DM0/DQS9 DQS9 DQ[7:0]
DQS DQS TDQS TDQS DQ [7:0]
DQS DQS TDQS TDQS DQ [7:0]
Vtt
RAS
ZQ
CS
ZQ
CS
ZQ
CS
ZQ
CS
VDDSPD EVENT
Vtt
VDDSPD
SA0
SA0 SA1 SA2 VSS
SCL SDA
EVENT SPD with SA1 Integrated SA2 SCL TS SDA VSS
Note: 1. DQ-to-I/O wiring may be changed within a byte. 2. Unless otherwise noted, resistor values are 15Ω ± 5%. 3. ZQ resistors are 240Ω ± 1%. For all other resistor values refer to the appropriate wiring diagram. 4. See the wiring diagrams for all resistors associated with the command, address and control bus.
Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative
VDDSPD VDD VTT VREFCA VREFDQ VSS
Serial PD
D0–D17 D0–D17 D0–D17 D0–D17 D0–D17
Rev. 0.4 / Jul. 2009
A[O:N]/BA[N:O]
DQS1 DQS1 DM1/DQS10 DQS10 DQ[15:8]
DQS DQS TDQS TDQS DQ [7:0]
DQS DQS TDQS TDQS DQ [7:0]
DQS7 DQS7 DM7/DQS16 DQS16 DQ[63:56]
DQS DQS TDQS TDQS DQ [7:0]
DQS DQS TDQS TDQS DQ [7:0]
RAS
ZQ
CS
ZQ
CS
ZQ
CS
ZQ
CS
A[N:O]/BA[N:O]
DQS2 DQS2 DM2/DQS11 DQS11 DQ[23:16]
DQS DQS TDQS TDQS DQ [7:0]
DQS DQS TDQS TDQS DQ [7:0]
DQS6 DQS6 DM6/DQS15 DQS15 DQ55:48]
DQS DQS TDQS TDQS DQ [7:0]
DQS DQS TDQS TDQS DQ [7:0]
RAS
ZQ
CS
ZQ
CS
ZQ
CS
ZQ
CS
A[N:O]/BA[N:O]
DQS3 DQS3 DM3/DQS12 DQS12 DQ[31:24]
DQS DQS TDQS TDQS DQ [7:0]
DQS DQS TDQS TDQS DQ [7:0]
DQS5 DQS5 DM5/DQS14 DQS14 DQ[47:40]
DQS DQS TDQS TDQS DQ [7:0]
DQS DQS TDQS TDQS DQ [7:0]
RAS
ZQ
CS
ZQ
CS
ZQ
CS
ZQ
CS
A[N:O]/BA[N:O]
DQS8 DQS8 DM8/DQS17 DQS17 CB[7:0]
DQS DQS TDQS TDQS DQ [7:0]
DQS DQS TDQS TDQS DQ [7:0]
DQS4 DQS4 DM4/DQS13 DQS13 DQ[39:32]
DQS DQS TDQS TDQS DQ [7:0]
DQS DQS TDQS TDQS DQ [7:0]
RS1B
RODT1B
PCK1B RCKE1B
PCK1B
12
3.2.2 2GB, 256Mx72 Module(2Rank of x8)-page2
S0 S1 S[3:2] NC BA[N:0] A[N:0] RAS CAS WE CKE0 CKE1 ODT0 ODT1 CK0 120Ω ± 5% CK0 CK1 CK1 PAR_IN RESET
1:2 R E G I S T E R / P L L
RS0A → CS0: SDRAMs D[3:0], D8 RS0B → CS0: SDRAMs D[7:4] RS1A → CS1: SDRAMs D[12:9], D17 RS1B → CS1: SDRAMs D[16:13] RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D17 RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13] RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D17 RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13] RRASA → RAS: SDRAMs D[3:0], D[12:8], D17 RRASB → RAS: SDRAMs D[7:4], D[16:13] RCASA → CAS: SDRAMs D[3:0], D[12:8], D17 RCASB → CAS: SDRAMs D[7:4], D[16:13] RWEA → WE: SDRAMs D[3:0], D[12:8], D17 RWEB → WE: SDRAMs D[7:4], D[16:13] RCKE0A → CKE0: SDRAMs D[3:0], D8 RCKE0B → CKE0: SDRAMs D[7:4] RCKE1A → CKE1: SDRAMs D[12:9], D17 RCKE1B → CKE1: SDRAMs D[16:13] RODT0A → ODT0: SDRAMs D[3:0], D8 RODT0B → ODT0: SDRAMs D[7:4] RODT1A → ODT1: SDRAMs D[12:9], D17 RODT1A → ODT1: SDRAMs D[16:13] PCK0A → CK: SDRAMs D[3:0], D8 PCK0B → CK: SDRAMs D[7:4] PCK1A → CK: SDRAMs D[12:9], D17 PCK1B → CK: SDRAMs D[16:13] PCK0A → CK: SDRAMs D[3:0], D8 PCK0B → CK: SDRAMs D[7:4] PCK1A → CK: SDRAMs D[12:9], D17 PCK1B → CK: SDRAMs D[16:13]
120Ω ± 5%
OERR Err_Out RST RST: SDRAMs D[17:0]
* S[3:2], CK1 and CK1 are NC
Rev. 0.4 / Jul. 2009
13
3.3 2GB, 256Mx72 Module(1Rank of x4)-page1
A[O:N]A /BA[O:N]A A[O:N]B /BA[O:N]B
ZQ
RODT0A
RS0A RRASA
RS0B RRASB
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
D8
ODT CK CKE CAS WE CK
D17
ODT CK CKE CAS WE CK
D4
ODT CK CKE CAS WE CK
D13
ODT ODT ODT ODT CK CKE CAS WE CK
A[O:N]/BA[O:N]
ZQ
VSS
VSS
VSS
RAS
RAS
RAS
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
D3
ODT CAS CK CKE WE CK
D12
ODT CAS CK CKE WE CK
D5
ODT CAS CK CKE WE CK
D14
CAS CK CKE WE CK
A[O:N]/BA[O:N]
ZQ
VSS
VSS
VSS
RAS
RAS
RAS
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
D2
ODT CAS CK CKE WE CK
D11
ODT CAS CK CKE WE CK
D6
ODT CAS CK CKE WE CK
D15
CAS CK CKE WE CK
A[O:N]/BA[O:N]
ZQ
VSS
VSS
VSS
RAS
RAS
RAS
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
D1
ODT CK CKE CAS WE CK
D10
ODT CK CKE CAS WE CK
D7
ODT CK CKE CAS WE CK
D16
CK CKE CAS WE CK
A[O:N]/BA[O:N]
VSS
VSS
VSS
RAS
RAS
RAS
A[O:N]/BA[O:N]
D0
ODT CAS CK CKE WE CK
D9
ODT CAS CK CKE WE CK
A[O:N]/BA[O:N]
VSS
RAS
Vtt
RAS
CS
CS
VDDSPD EVENT SCL SDA
VDDSPD EVENT SCL SDA
SA0
SA0 SA1 SA2 VSS
VSS
DQS0 DQS0 VSS DQ[3:0]
DQS DQS DM DQ [3:0]
ZQ
DQS9 DQS9 VSS DQ[7:4]
DQS DQS DM DQ [3:0]
ZQ
Vtt
SPD with SA1 Integrated SA2 TS VSS
Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative
VDDSPD VDD VTT VREFCA VREFDQ VSS SPD
D0–D17 D0–D17 D0–D17 D0–D17 D0–D17
Note:
1. DQ-to-I/O wiring may be changed within a nibble. 2. Unless otherwise noted, resistor values are 15%.± 5 Ω 3. See the wiring diagrams for all resistors associated with the command, address and control bus. 4. ZQ resistors are 240 Ω ±For all other resistor values refer to the %. 1 appropriate wiring diagram.
Rev. 0.4 / Jul. 2009
RAS
CS
CS
CS
CS
VSS
DQS1 DQS1 VSS DQ[11;8]
DQS DQS DM DQ [3:0]
ZQ
DQS10 DQS10 VSS DQ[15:12]
DQS DQS DM DQ [3:0]
ZQ
DQS7 DQS7 VSS DQ[59:56]
DQS DQS DM DQ [3:0]
ZQ
DQS16 DQS16 VSS DQ[63:60]
DQS DQS DM DQ [3:0]
RAS
CS
CS
CS
CS
VSS
DQS2 DQS2 VSS DQ[19:16]
DQS DQS DM DQ [3:0]
ZQ
DQS11 DQS11 VSS DQ23:20]
DQS DQS DM DQ [3:0]
ZQ
DQS6 DQS6 VSS DQ[51:48]
DQS DQS DM DQ [3:0]
ZQ
DQS15 DQS15 VSS DQ[55;52]
DQS DQS DM DQ [3:0]
RAS
CS
CS
CS
CS
VSS
DQS3 DQS3 VSS DQ[27:24]
DQS DQS DM DQ [3:0]
ZQ
DQS12 DQS12 VSS DQ[31:28]
DQS DQS DM DQ [3:0]
ZQ
DQS5 DQS5 VSS DQ[43:40]
DQS DQS DM DQ [3:0]
ZQ
DQS14 DQS14 VSS DQ[47:44]
DQS DQS DM DQ [3:0]
RAS
CS
CS
CS
CS
VSS
DQS8 DQS8 VSS CB[3:0]
DQS DQS DM DQ [3:0]
ZQ
DQS17 DQS17 VSS CB[7:4]
DQS DQS DM DQ [3:0]
ZQ
RODT0B
PCK0A RCKE0A
PCK0B RCKE0B
RCASA
RCASB
PCK0A
PCK0B
RWEA
RWEB
DQS4 DQS4 VSS DQ[35:32]
DQS DQS DM DQ [3:0]
DQS13 DQS13 VSS DQ[39:36]
DQS DQS DM DQ [3:0]
ZQ
14
3.3 2GB, 256Mx72 Module(1Rank of x4)-page2
S0 S1 BA[N:0] A[N:0] RAS CAS WE CKE0 ODT0 CK0 RS0A → CS0: SDRAMs D[3:0], D[12:8], D17 RS0B → CS0: SDRAMs D[7:4], D[16:13] RS1A → CS1: SDRAMs D[12:9], D17 RS1B → CS1: SDRAMs D[16:13] RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D17 RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13] RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D17 RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13] RRASA → RAS: SDRAMs D[3:0], D[12:8], D17 RRASB → RAS: SDRAMs D[7:4], D[16:13] RCASA → CAS: SDRAMs D[3:0], D[12:8], D17 RCASB → CAS: SDRAMs D[7:4], D[16:13] RWEA → WE: SDRAMs D[3:0], D[12:8], D17 RWEB → WE: SDRAMs D[7:4], D[16:13] RCKE0A → CKE0: SDRAMs D[3:0], D[12:8], D17 RCKE0B → CKE0: SDRAMs D[7:4], D[16:13] RODT0A → ODT0: SDRAMs D[3:0], D[12:8]. D17 RODT0B → ODT0: SDRAMs D[7:4], D[16:13] PCK0A → CK: SDRAMs D[3:0], D8 PCK0B → CK: SDRAMs D[7:4] PCK0A → CK: SDRAMs D[3:0], D8 PCK0B → CK: SDRAMs D[7:4] OERR Err_Out RESET RST RST: SDRAMs D[17:0]
1:2 R E
G
I S T E R / P L L
CK0 PAR_IN
* S[3:2], CKE1, ODT1, CK1 and CK1 are NC (Unused register inputs ODT1 and CKE1 have a 330Ω resistor to ground.)
Rev. 0.4 / Jul. 2009
15
DQS17 DQS17 VSS CB[7:4]
DQS10 DQS10 VSS DQ[15:12]
DQS11 DQS11 VSS DQ[23:20]
DQS12 DQS12 VSS DQ[31:28]
DQS0 DQS0 VSS DQ[3:0]
Vtt
CS CS RAS CAS RAS CAS CAS CAS CAS RAS RAS RAS
DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0]
CS
CS
CS
RS0A RRASA RCASA RWEA PCK0A PCK0A RCKE0A RODT0A A[O:N]A /BA[O:N]A
Rev. 0.4 / Jul. 2009
WE WE WE WE WE
D0 D17
CK CK CK CKE ODT A[N:O]/BA[N:O] CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT CK CKE CK CKE CK CK CS CS RAS CAS WE RAS CAS WE WE WE CAS CAS RAS RAS CS CS
D10
D11
D12
CK CK CKE ODT A[N:O]/BA[N:O]
CS RAS CAS WE
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
RS1A
D18
CK CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT CK CKE CK CKE CK CK
D28
D29
D30
D35
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT
PCK1A PCK1A RCKE1A R0DT1A
A[N:O]/BA[N:O]
DQS2 DQS2 VSS DQ[19:16]
DQS3 DQS3 VSS DQ[27:24]
DQS8 DQS8 VSS CB[3:0]
DQS1 DQS1 VSS DQ[11:8]
DQS9 DQS9 VSS DQ[7:4]
3.4 4GB, 512Mx72 Module(2Rank of x4)-page1
Vtt
CS RAS CAS WE WE WE CAS CAS RAS RAS CS CS
DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0]
CS RAS CAS WE
CS RAS CAS WE
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
RS0A RRASA RCASA RWEA
CK CK CKE ODT A[N:O]/BA[N:O]
D9
CK CK CKE ODT A[N:O]/BA[N:O] ODT CK CKE CK CS RAS CAS WE CS RAS CAS WE
DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0]
D1
D2
D3
D8
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT
PCK0A PCK0A RCKE0A RODT0A
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[O:N]A /BA[O:N]A
CS RAS CAS WE
CS RAS CAS WE
CS RAS CAS WE
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
RS1A
D27
D19
D20
D21
D26
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT A[N:O]/BA[N:O]
PCK1A PCK1A RCKE1A R0DT1A
A[N:O]/BA[N:O]
16
3.4 4GB, 512Mx72 Module(2Rank of x4)-page2
A[N:O]B /BA[N:O]B RODT0B A[N:O]B /BA[N:O]B RODT0B PCK0B RCKE0B PCK0B RCKE0B R0DT1B RCKE1B RS0B RRASB RS0B RRASB RCASB PCK1B PCK1B RS1B PCK1B RS1B R0DT1B
A[N:O]/BA[N:O] ODT A[N:O]/BA[N:O] ODT A[N:O]/BA[N:O] ODT A[N:O]/BA[N:O] ODT
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D14
ODT CAS CK CKE WE CK
D32
ODT CAS CK CKE WE CK
D13
ODT CAS CK CKE WE CK
A[N:O]/BA[N:O]
DQS14 DQS14 VSS DQ[47:44]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
DQS13 DQS13 VSS DQ[39:36]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
D31
CAS CK CKE CK CKE CK CKE CK CKE WE CK CK CK CK
RAS
RAS
RAS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D4
ODT CK CKE CAS WE CK
D22
ODT CK CKE CAS WE CK
D5
ODT CK CKE CAS WE CK
A[N:O]/BA[N:O]
DQS4 DQS4 VSS DQ[35:32]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
DQS5 DQS5 VSS DQ[43:40]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
RAS
CS
CS
CS
CS
D23
CAS WE
RAS
RAS
RAS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D16
ODT CAS CK CKE WE CK
D34
ODT CAS CK CKE WE CK
D15
ODT CAS CK CKE WE CK
A[N:O]/BA[N:O]
DQS16 DQS16 VSS DQ[63:60]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
DQS15 DQS15 VSS DQ[55:52]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
RAS
CS
CS
CS
CS
D33
CAS WE
RAS
RAS
RAS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D7
ODT CK CKE CAS WE CK
D25
ODT CK CKE CAS WE CK
D6
ODT CK CKE CAS WE CK
A[N:O]/BA[N:O]
DQS7 DQS7 VSS DQ[59:56]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
DQS6 DQS6 VSS DQ[51:48]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
RAS
CS
CS
CS
CS
D24
CAS WE
RAS
RAS
RAS
Vtt
Vtt
VDDSPD VDD VTT VREFCA VREFDQ VSS
SPD
D0–D35 D0–D35 D0–D35 D0–D35 D0–D35
RAS
CS
CS
CS
CS
VDDSPD EVENT SCL SDA
VDDSPD
SA0
SA0 SA1 SA2 VSS
EVENT SPD with SA1 Integrated SA2 SCL TS SDA VSS
Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative
Note:
1. DQ-to-I/O wiring may be changed within a nibble. 2. See wiring diagrams for all resistors values. 3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.
Rev. 0.4 / Jul. 2009
RCKE1B
RCASB
PCK0B
PCK0B
PCK1B
RWEB
RWEB
17
3.4 4GB, 512Mx72 Module(2Rank of x4)-page3
S0 S1 BA[N:0] A[N:0] RAS CAS WE CKE0 CKE1 ODT0 ODT1 CK0
1:2 R E G I S T E R / P L L
RS0A → CS0: SDRAMs D[3:0], D[12:8], D17 RS0B → CS0: SDRAMs D[7:4], D[16:13] RS1A → CS1: SDRAMs D[21:18], D[30:26], D35 RS1B → CS1: SDRAMs D[25:22], D[34:31] RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RRASA → RAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RRASB → RAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RCASA → CAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RCASB → CAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RWEA → WE: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RWEB → WE: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RCKE0A → CKE0: SDRAMs D[3:0], D[12:8], D17 RCKE0B → CKE0: SDRAMs D[7:4], D[16:13] RCKE1A → CKE1: SDRAMs D[21:18], D[30:26], D35 RCKE1B → CKE1: SDRAMs D[25:22], D[34:31] RODT0A → ODT0: SDRAMs D[3:0], D[12:8], D17 RODT0B → ODT0: SDRAMs D[7:4], D[16:13] RODT1A → ODT1: SDRAMs D[21:18], D[30:26], D35 RODT1A → ODT1: SDRAMs D[25:22], D[34:31] PCK0A → CK: SDRAMs D[3:0], D[12:8], D17 PCK0B → CK: SDRAMs D[7:4], D[16:13] PCK1A → CK: SDRAMs D[21:18], D[30:26], D35 PCK1B → CK: SDRAMs D[25:22], D[34:31] PCK0A → CK: SDRAMs D[3:0], D[12:8], D17 PCK0B → CK: SDRAMs D[7:4], D[16:13] PCK1A → CK: SDRAMs D[21:18], D[30:26], D35 PCK1B → CK: SDRAMs D[25:22], D[34:31]
CK0 CK1 CK1 PAR_IN RESET RST
120Ω ± 5%
Err_Out RST: SDRAMs D[35:0]
* S[3:2], CK1 and CK1 are NC
Rev. 0.4 / Jul. 2009
18
DQS0 DQS0 DM0/TDQS9 TDQS9 DQ[7:0]
DQS8 DQS8 DM8/TDQS17 TDQS17 CB[7:0]
DQS3 DQS3 DM3/TDQS12 TDQS12 DQ[31:24]
DQS2 DQS2 DM2/TDQS11 TDQS11 DQ[32:16]
DQS1 DQS1 DM1/TDQS10 TDQS10 DQ[15:8]
Vtt
CS CS CS CS CS
CS0 WRAS WCAS WWE PCK0 PCK0 WCKE0 WODT0 WA[N:0] WBA[N:0]
DQS DQS TDQS TDQS DQ [7:0] ZQ
RAS CAS WE CK CK CK CK CK WE WE WE WE CAS CAS CAS CAS RAS RAS RAS RAS
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
Rev. 0.4 / Jul. 2009
3.5 4GB, 512Mx72 Module(4Rank of x8)-page1
U6
CK CKE ODT A[N:O] BA[N:O] BA[N:O] BA[N:O] BA[N:O] BA[N:O] A[N:O] A[N:O] A[N:O] A[N:O] ODT ODT ODT ODT CKE CKE CKE CKE CK CK CK CK CS RAS CAS WE CK CK CK CK WE WE WE CAS CAS CAS RAS RAS RAS CS CS CS CS RAS CAS WE CK
U5
CS1
U4
U3
U2
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
PCK0
U15
CK CKE ODT A[N:O] BA[N:O] BA[N:O] BA[N:O] BA[N:O] A[N:O] A[N:O] A[N:O] ODT ODT ODT CKE CKE CKE CK CK CK CS RAS CAS WE CK CK CK WE WE CAS CAS RAS RAS CS CS CS RAS CAS WE CK
U14
U13
U12
U11
CK CKE ODT A[N:O] BA[N:O]
PCK0 WCKE01 VDD
CS RAS CAS WE CK
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
CS2
PCK2
U24
CK CKE ODT A[N:O] BA[N:O] BA[N:O] BA[N:O] A[N:O] A[N:O] ODT ODT CKE CKE CK CK CS RAS CAS WE CK CK WE CAS RAS CS CS RAS CAS WE CK
U23
U22
U21
U20
CK CKE ODT A[N:O] BA[N:O]
CK CKE ODT A[N:O] BA[N:O]
PCK2 WCKE0 WODT1
CS RAS CAS WE CK
CS RAS CAS WE CK
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
CS3
PCK2
U33
CK CKE ODT A[N:O] BA[N:O] BA[N:O] A[N:O] ODT CKE CK
U32
U31
U30
U29
CK CKE ODT A[N:O] BA[N:O]
CK CKE ODT A[N:O] BA[N:O]
CK CKE ODT A[N:O] BA[N:O]
PCK2 WCKE1 VDD
19
3.5 4GB, 512Mx72 Module(4Rank of x8)-page2
WBA[N:0] WA[N:0] WODT0 WCKE01 WODT1 WCKE0 WCKE0 WRAS VDD WCKE1 WCAS WWE PCK0 PCK0 PCK2 PCK0 PCK0 PCK2 PCK2 PCK2
CK
CS0
CS1
CS2
CAS
CAS
CAS
CS3
RAS
RAS
RAS
RAS
CAS
CS
CS
CS
CK
CK
CK
CK
CK
CK
CS
BA[N:O]
BA[N:O]
BA[N:O]
CK
VDD
A[N:O] A[N:O] ODT BA[N:O] BA[N:O] ODT BA[N:O] A[N:O] ODT BA[N:O] A[N:O] ODT
A[N:O]
A[N:O]
A[N:O]
CKE
CKE
CKE
ODT
ODT
DQS4 DQS4 DM4/TDQS13 TDQS13 DQ[39:32]
DQS DQS TDQS TDQS DQ [7:0] ZQ
U7
DQS DQS TDQS TDQS DQ [7:0] ZQ
U16
DQS DQS TDQS TDQS DQ [7:0] ZQ
ODT
U25
DQS DQS TDQS TDQS DQ [7:0] ZQ
U34
CK
CK
CK
CK
CK
CK
CK CK CK
BA[N:O]
BA[N:O]
BA[N:O]
A[N:O]
A[N:O]
A[N:O]
CKE
CKE
CKE
CK CK CK
ODT
ODT
ODT
RAS
RAS
RAS
DQS5 DQS5 DM5/TDQS14 TDQS14 DQ[47:40]
DQS DQS TDQS TDQS DQ [7:0] ZQ
U8
DQS DQS TDQS TDQS DQ [7:0] ZQ
U17
DQS DQS TDQS TDQS DQ [7:0] ZQ
U26
DQS DQS TDQS TDQS DQ [7:0] ZQ
RAS
U35
A[N:O]
A[N:O]
BA[N:O]
BA[N:O]
A[N:O]
CK
CK
CK
CK
CK
CK
BA[N:O]
CKE
CKE
CKE
ODT
ODT
ODT
RAS
RAS
RAS
DQS6 DQS6 DM6/TDQS15 TDQS15 DQ[55:48]
DQS DQS TDQS TDQS DQ [7:0] ZQ
U9
DQS DQS TDQS TDQS DQ [7:0] ZQ
U18
DQS DQS TDQS TDQS DQ [7:0] ZQ
U27
DQS DQS TDQS TDQS DQ [7:0] ZQ
RAS
U36
CK
CK
CK
CK
CK
CKE
CKE
CK
CKE
ODT
ODT
ODT
RAS
RAS
RAS
A[N:O]
A[N:O]
BA[N:O]
BA[N:O]
A[N:O]
DQS3 DQS3 DM3/TDQS12 TDQS12 DQ[31:24]
DQS DQS TDQS TDQS DQ [7:0] ZQ
U10
DQS DQS TDQS TDQS DQ [7:0] ZQ
U19
DQS DQS TDQS TDQS DQ [7:0] ZQ
BA[N:O]
U28
DQS DQS TDQS TDQS DQ [7:0] ZQ
RAS
U37
Vtt
VDDSPD EVENT SCL SDA
VDDSPD
SA0
SA0 SA1 SA2 VSS
EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA
Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative
VDDSPD
CKE
WE
WE
WE
CAS
CAS
CAS
CAS
WE
CS
CS
CS
CS
CKE
WE
WE
WE
CAS
CAS
CAS
CAS
WE
CS
CS
CS
CS
CKE
WE
WE
WE
CAS
CAS
CAS
CAS
WE
CS
CS
CS
CS
CKE
WE
WE
WE
WE
Serial PD
U1–U37
Notes: 1. DQ-to-I/O wiring may be changed within a byte. 2. See wiring diagrams for resistor values. 3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.
VDD VTT VREFCA VREFDQ VSS
U1-U37 U1-U37 U1-U37
Rev. 0.4 / Jul. 2009
20
3.5 4GB, 512Mx72 Module(4Rank of x8)-page3
S0 S1 S2 S3 BA[N:0] A[N:0] RAS CAS WE CKE0 CKE1 ODT0 ODT1 CK0
1:2 R E G I S T E R / P L L
CK0 CK1 CK1 PAR_IN RESET RST
120Ω ± 5%
CS0 → CS0: SDRAMs U[10:2] CS1 → CS1: SDRAMs U[19:11] CS2 → CS2: SDRAMs U[28:20] CS3 → CS3: SDRAMs U[37:29] WBA[N:0] → BA[N:0]: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29] EBA[N:0] → BA[N:0]: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34] WA[N:0] → A[N:0]: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29] EA[N:0] → A[N:0]: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34] WRAS → RAS: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29] ERAS → RAS: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34] WCAS → CAS: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29] ECAS → CAS: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34] WWE → WE: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29] EWE → WE: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34] WCKE0 → CKE0: SDRAMs U[6:2], U[24:20] ECKE0 → CKE0: SDRAMs U[10:7], U[28:25] WCKE1 → CKE1: SDRAMs U[15:11], U[33:29] ECKE1 → CKE1: SDRAMs U[19:16], U[37:34] WODT0 → ODT0: SDRAMs U[6:2] EODT0 → ODT0: SDRAMs U[10:7] WODT0 → ODT1: SDRAMs U[24:20] EODT0 → ODT1: SDRAMs U[28:25] PCK0 → CK: SDRAMs U[6:2], U[15:11] PCK1 → CK: SDRAMs U[10:7], U[28:25] PCK2 → CK: SDRAMs U[24:20], U[33:29] PCK3 → CK: SDRAMs U[19:16], U[37:34] PCK0 → CK: SDRAMs U[6:2], U[15:11] PCK1 → CK: SDRAMs U[10:7], U[28:25] PCK2 → CK: SDRAMs U[24:20], U[33:29] PCK3 → CK: SDRAMs U[19:16], U[37:34] Err_Out RST: SDRAMs U[37:2]
Rev. 0.4 / Jul. 2009
21
VSS DQS8 DQS8 VSS CB[3:0]
VSS DQS0 DQS0 VSS DQ[3:0]
VSS DQS1 DQS1 VSS DQ[11:8]
VSS DQS2 DQS2 VSS DQ[19:16]
VSS DQS3 DQS3 VSS DQ[27:24]
Vtt
CS CS RAS CAS WE RAS CAS WE CAS WE CAS WE CAS WE RAS RAS RAS
ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0]
CS
CS
CS
ARS0A ARRASA ARCASA ARWEA APCK0A APCK0A ARCKE0A ARODT0A ARA[N:O]A /ARBA[N:O]A
Rev. 0.4 / Jul. 2009
D1 D9
CK CK CK CKE ODT A[N:O]/BA[N:O] CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT CK CKE CK CKE CK CK
VSS VSS VSS VSS VSS
D3
D5
D7
CK CK CKE ODT A[N:O]/BA[N:O]
CS CS RAS CAS WE RAS CAS WE WE WE WE CAS CAS CAS RAS RAS RAS
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
CS
CS
CS
ARS1A
D0
CK CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT CK CKE CK CKE CK CK
VSS VSS VSS VSS
D2
D4
D6
D8
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT
ARCKE1A VDD
A[N:O]/BA[N:O]
3.6 8GB, 1Gx72 Module(4Rank of x4)-page1
VSS
CS RAS CAS WE WE WE CK CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT A[N:O]/BA[N:O] CK CKE CK CKE CK CK CAS CAS RAS RAS
CS
CS
CS RAS CAS WE CK CK CKE ODT
CS RAS CAS WE
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
BRS2A BRRASA BRCASA BRWEA
D53
VSS VSS
D51
D49
VSS
A[N:O]/BA[N:O]
D47
VSS
D45
CK CK CKE ODT A[N:O]/BA[N:O]
VSS
BPCK0A BPCK0A BRCKE0A BRODT1A BRA[N:O]A /BRBA[N:O]A
CS RAS CAS WE WE CAS CK CK CKE ODT RAS
CS
CS RAS CAS WE
CS RAS CAS WE
CS RAS CAS WE
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
BRS3A
D52
D50
D48
D46
D44
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT A[N:O]/BA[N:O]
BRCKE1A VDD
A[N:O]/BA[N:O]
22
VSS DQS17 DQS17 VSS CB[7:4]
VSS DQS9 DQS9 VSS DQ[7:4]
VSS DQS10 DQS10 VSS DQ[11:8]
VSS DQS11 DQS11 VSS DQ[23:20]
VSS DQS12 DQS12 VSS DQ[31:28]
Vtt
CS CS RAS CAS WE RAS CAS WE CAS WE CAS WE CAS WE RAS RAS RAS
ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0]
CS
CS
CS
ARS0A ARRASA ARCASA ARWEA APCK0A APCK0A ARCKE0A ARODT0A ARA[N:O]A /ARBA[N:O]A
Rev. 0.4 / Jul. 2009
D19 D27
CK CK CK CKE ODT A[N:O]/BA[N:O] CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT CK CKE CK CKE CK CK
VSS VSS VSS VSS VSS
D21
D23
D25
CK CK CKE ODT A[N:O]/BA[N:O]
CS CS RAS CAS WE RAS CAS WE WE WE WE CAS CAS CAS RAS RAS RAS
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
CS
CS
CS
ARS1A
D18
CK CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT CK CKE CK CKE CK CK
VSS VSS VSS VSS
D20
D22
D24
D26
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT
ARCKE1A VDD
A[N:O]/BA[N:O]
3.6 8GB, 1Gx72 Module(4Rank of x4)-page2
VSS
CS RAS CAS WE WE WE CK CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT A[N:O]/BA[N:O] CK CKE CK CKE CK CK CAS CAS RAS RAS
CS
CS
CS RAS CAS WE CK CK CKE ODT
CS RAS CAS WE
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
BRS2A BRRASA BRCASA BRWEA
D71
VSS VSS
D69
D67
VSS
A[N:O]/BA[N:O]
D65
VSS
D63
CK CK CKE ODT A[N:O]/BA[N:O]
VSS
BPCK0A BPCK0A BRCKE0A BRODT1A BRA[N:O]A /BRBA[N:O]A
CS RAS CAS WE WE CAS CK CK CKE ODT RAS
CS
CS RAS CAS WE
CS RAS CAS WE
CS RAS CAS WE
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
BRS3A
D70
D68
D66
D64
D62
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT A[N:O]/BA[N:O]
BRCKE1A VDD
A[N:O]/BA[N:O]
23
VSS DQS7 DQS7 VSS DQ[59:56
VSS DQS6 DQS6 VSS DQ[51:48]
VSS DQS5 DQS5 VSS DQ[43:40]
VSS DQS4 DQS4 VSS DQ[35:32]
Vtt
CS CS RAS CAS WE RAS CAS WE CAS WE CAS WE RAS RAS
ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0]
CS
CS
ARS0B ARRASB ARCASB ARWEB APCK0B APCK0B ARCKE0B ARODT0B ARA[N:O]B /ARBA[N:O]B
Rev. 0.4 / Jul. 2009
D17 D11
CK CK CK CKE ODT A[N:O]/BA[N:O] CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT CK CKE CK
VSS VSS VSS VSS
D15
D13
CK CK CKE ODT A[N:O]/BA[N:O]
CS CS RAS CAS WE RAS CAS WE WE WE CAS CAS RAS RAS
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
CS
CS
ARS1B
D16
CK CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT CK CKE CK
VSS VSS VSS
D14
D12
D10
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT
ARCKE1B VDD
A[N:O]/BA[N:O]
3.6 8GB, 1Gx72 Module(4Rank of x4)-page3
VSS
CS RAS CAS WE WE CK CK CKE ODT A[N:O]/BA[N:O] ODT A[N:O]/BA[N:O] CK CKE CK CAS RAS
CS
CS RAS CAS WE CK CK CKE ODT
CS RAS CAS WE
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
BRS2B BRRASB BRCASB BRWEB
D37
VSS
D39
VSS
A[N:O]/BA[N:O]
D41
VSS
D13
CK CK CKE ODT A[N:O]/BA[N:O]
VSS
BPCK0B BPCK0B BRCKE0B BRODT1B BRA[N:O]B /BRBA[N:O]B
CS RAS CAS WE CK CK CKE ODT
CS RAS CAS WE
CS RAS CAS WE
CS RAS CAS WE
A[N:O]/BA[N:O]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
BRS3B
D36
D38
CK CK CKE ODT A[N:O]/BA[N:O]
D40
CK CK CKE ODT A[N:O]/BA[N:O]
D42
CK CK CKE ODT A[N:O]/BA[N:O]
BRCKE1B VDD
24
3.6 8GB, 1Gx72 Module(4Rank of x4)-page4
ARA[N:O]B /ARBA[N:O]B BRA[N:O]B /BRBA[N:O]B ARODT0B ARCKE1B BRODT1B APCK0B ARCKE0B BPCK0B BRCKE0B BRCKE1B ARS0B ARRASB ARCASB BRS2B BRRASB BRCASB APCK0B ARS1B BPCK0B ARWEB BRWEB BRS3B VDD VDD
A[N:O]/BA[N:O] ODT A[N:O]/BA[N:O] ODT A[N:O]/BA[N:O] ODT A[N:O]/BA[N:O] ODT
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D29
ODT CK CKE CAS WE CK
D28
ODT CK CKE CAS WE CK
D61
ODT CK CKE CAS WE CK
A[N:O]/BA[N:O]
VSS DQS13 DQS13 VSS DQ[39:36]
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
D60
CK CKE CK CKE CK CKE CK CKE CAS WE WE WE WE CK CK CK CK
RAS
RAS
RAS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D31
ODT CK CKE CK
D30
ODT CK CKE WE CK
D59
ODT CK CKE WE CK
A[N:O]/BA[N:O]
VSS DQS14 DQS14 VSS DQ[47:44]
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
RAS
CS
CS
CS
CS
D58
RAS
RAS
RAS
RAS
CAS WE
CAS
CAS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D33
ODT CK CKE CK
D32
ODT CK CKE WE CK
D57
ODT CK CKE WE CK
A[N:O]/BA[N:O]
VSS DQS15 DQS15 VSS DQ[55:52]
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
CAS CAS CAS
CS
CS
CS
CS
D56
RAS
RAS
RAS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D35
ODT CK CKE CK
D34
ODT CK CKE WE CK
D55
ODT CK CKE WE CK
A[N:O]/BA[N:O]
VSS DQS16 DQS16 VSS DQ[63:60]
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
RAS
CAS WE
CAS
CAS
CS
CS
CS
CS
D54
RAS
RAS
RAS
Vtt
VDDSPD VDD VTT VREFCA VREFDQ VSS
SPD
D0–D71
VDDSPD EVENT SCL SDA
VDDSPD
RAS
CAS WE
CAS
CAS
CS
CS
CS
CS
SA0
SA0 SA1 SA2 VSS
D0–D71 D0–D71 D0–D71
EVENT SPD with SA1 Integrated SA2 SCL TS SDA VSS
Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative
Note:
1. DQ-to-I/O wiring may be changed within a nibble. 2. Unless otherwise noted, resistor values are 15 Ohms ± 5%. 3. See the wiring diagrams for all resistors associated with the command, address and control bus. 4. ZQ resistors are 240 Ohms ± 1%. For all other resistor values refer to the appropriate wiring diagram.
Rev. 0.4 / Jul. 2009
25
3.6 8GB, 1Gx72 Module(4Rank of x4)-page5
S0
1:2 R E G I S T E R / P L L A
ARS0A → CS1: SDRAMs D1,D3,D5,D7 D9, D19, D21, D23, D25, D27 ARS0B → CS1: SDRAMs D11, D13, D15, D17, D29, D31, D33, D35
S2
1:2 R E G I S T E R / P L L B
BRS2A → CS1: SDRAMs D45,D47,D49,D51,D53 D63,D65,D67,D69,D71 BRS2B → CS1: SDRAMs D37,D39,D41,D43, D55,D57,D59,D61 BRS3A → CS0: SDRAMs D44.D46,D48,D50,D52, D62,D64,D66,D68,D70 BRS3B → CS0: SDRAMs D36,D38,D40,D42, D54,D56,D58,D60 BRBA[N:0]A → BA[N:0]: SDRAMs D[53:44],D[71:62] BRBA[N:0]B → BA[N:0]: SDRAMs D[43:36],D[61:54] BRA[N:0]A → A[N:0]: SDRAMs D[55:44],D[71:62] BRA[N:0]B → A[N:0]: SDRAMs D[43:36],D[61:54] BRRASA → RAS: SDRAMs D[53:44],D[71:62] BRRASB → RAS: SDRAMs D[43:36],D[61:54] BRCASA → CAS: SDRAMs D[53:44],D[71:62] BRCASB → CAS: SDRAMs D[43:36],D[61:54] BRWEA → WE: SDRAMs D[53:44],D[71:62] BRWEB → WE: SDRAMs D[43:36],D[61:54] BRCKE0A → CKE1: SDRAMs D45,D47,D49,D51,D53, D63,D65,D67,D69,D71 BRCKE0B → CKE1: SDRAMs D37,D39,D41,D43, D55,D57,D59,D61 BRCKE1A → CKE0: SDRAMs D44.D46,D48,D50,D52, D62,D64,D66,D68,D70 BRCKE1B → CKE0: SDRAMs D36,D38,D40,D42, D54,D56,D58,D60 BRODT1A → ODT1: SDRAMs D45,D47,D49,D51,D53 D63,D65,D67,D69,D71 BRODT1B → ODT0: SDRAMs D37,D39,D41,D43 D55,D57,D59,D61 BPCK0A → CK: SDRAMs D[53:44] BPCK0B → CK: SDRAMs D[43:36] BPCK1A → CK: SDRAMs D[71:62] BPCK1B → CK: SDRAMs D[61:54] BPCK0A → CK: SDRAMs D[53:44] BPCK0B → CK: SDRAMs D[43:36] BPCK1A → CK: SDRAMs D[71:62] BPCK1B → CK: SDRAMs D[61:54] Err_Out
S1
BA[N:0] A[N:0] RAS CAS WE CKE0
CKE1
ODT0
CK0
120Ω ± 5%
CK0
S3 ARS1A → CS0: SDRAMs D0, D2, D4, D6, D8, D18, D20, D22, D24, D26 ARS1B → CS0: SDRAMs D10, D12, D14, D16, D28, D30, D32, D34 ARBA[N:0]A → BA[N:0]: SDRAMs D[9:0],D[27:18] BA[N:0] ARBA[N:0]B → BA[N:0]: SDRAMs D[17:10],D[35:28] ARA[N:0]A → A[N:0]: SDRAMs D[9:0],D[27:18] A[N:0] ARA[N:0]B → A[N:0]: SDRAMs D[17:10],D[35:28] RAS ARRASA → RAS: SDRAMs D[9:0],D[27:18] ARRASB → RAS: SDRAMs D[17:10],D[35:28] ARCASA → CAS: SDRAMs D[9:0],D[27:18] CAS ARCASB → CAS: SDRAMs D[17:10],D[35:28] ARWEA → WE: SDRAMs D[9:0],D[27:18] WE ARWEB → WE: SDRAMs D[17:10],D[35:28] ARCKE0A → CKE1: SDRAMs D1,D3,D5,D7,D9, CKE0 D19, D21, D23, D25, D27 ARCKE0B → CKE1: SDRAMs D11,D13,D15,D17, D29, D31, D33, D35 CKE1 ARCKE1A → CKE0: SDRAMs D0,D2,D4,D6,D8, D18, D20, D22, D24, D26 ARCKE1B → CKE0: SDRAMs D10,D12,D14,D16, D28, D30, D32, D34 ARODT0A → ODT1: SDRAMs D1,D3,D5,D7,D9, ODT1 D19, D21, D23, D25, D27 ARODT0B → ODT0: SDRAMs D11,D13,D15,D17, D29, D31, D33, D35 APCK0A → CK: SDRAMs D[9:0] CK0 APCK0B → CK: SDRAMs D[17:10] 120Ω APCK1A → CK: SDRAMs D[27:18] ± 5% APCK1B → CK: SDRAMs D[35:28] APCK0A → CK: SDRAMs D[9:0] CK0 APCK0B → CK: SDRAMs D[17:10] APCK1A → CK: SDRAMs D[27:18] APCK1B → CK: SDRAMs D[35:28] Err_Out PAR_IN RESET RST: SDRAMs D[35:0]
PAR_IN RESET RST
RST
* S[3:2], CK1 and CK1 are NC
CK1 CK1
120Ω ± 5%
Rev. 0.4 / Jul. 2009
26
4. Environmental Parameter
Environmental Parameters
Symbol
TOPR HOPR TSTG HSTG PBAR
Note: 1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating conditions for extended periods may affect reliablility. 2. Up to 9850 ft. 3. The designer must meet the case temperature specifications for individual module components.
Parameter
Operating temperature Operating humidity (relative) Storage temperature Storage humidity (without condensation) Barometric Pressure (operating & storage)
Rating
See Note 10 to 90 -50 to +100 5 to 95 105 to 69
Units
Notes
3
%
o
1 1 1 1, 2
C
% K Pascal
Rev. 0.4 / Jul. 2009
27
5. Pin Capacitance (VDD=1.5V, VDDQ=1.5V)
1GB: HMT112R7AFP8C
Pin CK0, CK0 CKE, ODT CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF pF
CCK CI1 CI2 CI3 CIO
TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD
2GB: HMT125R7AFP8C
Pin CK0, CK0 CKE, ODT CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF pF
CCK CI1 CI2 CI3 CIO
TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD
2GB: HMT125R7AFP4C
Pin CK0, CK0 CKE, ODT CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF pF
CCK CI1 CI2 CI3 CIO
TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD
4GB: HMT151R7AFP4C
Pin CK0, CK0 CKE, ODT CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF pF
CCK CI1 CI2 CI3 CIO
TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD
Rev. 0.4 / Jul. 2009
28
4GB: HMT151R7AFP8C
Pin CK0, CK0 CKE, ODT CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF pF
CCK CI1 CI2 CI3 CIO
TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD
8GB: HMT31GR7AMP4C
Pin CK0, CK0 CKE, ODT CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Note: 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only.
Symbol Min Max Unit pF pF pF pF pF
CCK CI1 CI2 CI3 CIO
TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD
Rev. 0.4 / Jul. 2009
29
6. IDD Specifications (Tcase: 0 to 95oC)
1GB, 128M x 72 R-DIMM: HMT112R7AFP8C Symbol IDD0 IDD1 IDD2N IDD2NT IDDQ2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDDQ4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7 DDR3 800 1484 1664 1259 1304 1502 318 462 1259 1349 498 2024 1304 2204 2474 318 336 336 2654 DDR3 1066 1592 1799 1349 1394 1502 318 480 1349 1439 588 2294 1304 2564 2564 318 336 336 3014 DDR3 1333 1664 1889 1439 1484 1502 318 498 1439 1529 633 2654 1304 2834 2654 318 336 336 3464 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
2GB, 256M x 72 R-DIMM: HMT125R7AFP8C Symbol IDD0 IDD1 IDD2N IDD2NT IDDQ2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDDQ4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7 DDR3 800 1979 2159 1754 1844 2240 408 696 1754 1934 798 2519 1799 2699 2969 408 444 444 3149 DDR3 1066 2177 2384 1934 2024 2240 408 732 1934 2114 948 2879 1889 3149 3149 408 444 444 3599 DDR3 1333 2399 2564 2114 2204 2240 408 768 2114 2294 1038 3329 1979 3509 3329 408 444 444 4139 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
Rev. 0.4 / Jul. 2009
30
2GB, 256M x 72 R-DIMM: HMT125R7AFP4C Symbol IDD0 IDD1 IDD2N IDD2NT IDDQ2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDDQ4R IDD4W IDD5B IDD6 IDDET IDD6TC IDD7 DDR3 800 2204 2564 1754 1844 2240 408 696 1754 1934 768 3284 1844 3644 4184 408 444 444 4544 DDR3 1066 2420 2834 1934 2024 2240 408 732 1934 2114 948 3824 1844 4364 4364 408 444 444 5264 DDR3 1333 2564 3014 2114 2204 2240 408 768 2114 2294 1038 4544 1844 4904 4544 408 444 444 6164 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
4GB, 512M x 72 R-DIMM: HMT151R7AFP4C Symbol IDD0 IDD1 IDD2N IDD2NT IDDQ2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDDQ4R IDD4W IDD5B IDD6 IDDET IDD6TC IDD7 DDR3 800 3194 3554 2744 2924 3716 588 1164 2744 3104 1308 4274 2834 4634 5174 588 660 660 5534 DDR3 1066 3590 4004 3104 3284 3716 588 1236 3104 3464 1668 4994 3014 5534 5534 588 660 660 6434 DDR3 1333 3914 4364 3464 3644 3716 588 1308 3464 3824 1848 5894 3194 6254 5894 588 660 660 7514 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
Rev. 0.4 / Jul. 2009
31
4GB, 512M x 72 R-DIMM: HMT151R7AFP8C Symbol IDD0 IDD1 IDD2N IDD2NT IDDQ2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDDQ4R IDD4W IDD5B IDD6 IDDET IDD6TC IDD7 DDR3 800 2969 3149 2744 2924 3716 588 1164 2744 3104 1308 3509 2789 3689 3959 588 660 660 4139 DDR3 1066 3347 3554 3104 3284 3716 588 1236 3104 3464 1668 4049 3059 4319 4319 588 660 660 4769 DDR3 1333 3689 3914 3464 3644 3716 588 1308 3464 3824 1848 4679 3329 4859 4679 588 660 660 5489 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
8GB, 1G x 72 R-DIMM: HMT31GR7AMP4C Symbol IDD0 IDD1 IDD2N IDD2NT IDDQ2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDDQ4R IDD4W IDD5B IDD6 IDDET IDD6TC IDD7 DDR3 800 5174 5534 4724 5084 6668 948 2100 4724 5444 2388 6254 4814 6614 7154 948 1092 1092 7514 DDR3 1066 5930 6344 5444 5804 6668 948 2244 5444 6164 3108 7334 5354 7874 7874 948 1092 1092 8774 DDR3 1333 6614 7064 6164 6524 6668 948 2388 6164 6884 3468 8594 5894 8954 8594 948 1092 1092 10214 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
Rev. 0.4 / Jul. 2009
32
7.1 128Mx72 - HMT112R7AFP8C
Front
133.35
128.95 2.10 ± 0.15
SPD/TS
4X3.00 ± 0.10 Detail A
1
Registering Clock Driver
Detail B
Detail C
120
2X3.00 ± 0.10
1
5.175
47.00
5.0
71.00
Back
240
121 1
Side
3.43mm max
Detail of Contacts A
1.20 ± 0.15
Detail of Contacts B
0.80 ± 0.05
Detail of Contacts C
2.50
0.3 ± 0.15
2.50 ± 0.20
0.20
3 ± 0.1
0.3~0.1
1.00
1.50 ± 0.10 5.00
2.50 ± 0.20
3.80
1.27 ± 010mm max
Rev. 0.4 / Jul. 2009
9.50 17.30
30.00
33
7.2 256Mx72 - HMT125R7AFP8C
Front
133.35
128.95 2.10 ± 0.15
SPD/TS
4X3.00 ± 0.10 Detail A
1
Registering Clock Driver
Detail B
Detail C
120
2X3.00 ± 0.10
1
5.175
47.00
5.0
71.00
Back
240
121 1
Side
3.43mm max
Detail of Contacts A
1.20 ± 0.15
Detail of Contacts B
0.80 ± 0.05
Detail of Contacts C
2.50
0.3 ± 0.15
2.50 ± 0.20
0.20
3 ± 0.1
0.3+0.1
1.00
1.50 ± 0.10 5.00
2.50 ± 0.20
3.80
1.27 ± 010mm max
6.3 256Mx72 - HMT125R7AFP4C
Rev. 0.4 / Jul. 2009 34
9.50 17.30
30.00
7.3 256Mx72 - HMT125R7AFP4C
Front
133.35
128.95 2.10 ± 0.15
SPD/TS
4X3.00 ± 0.10
Registering Clock Driver
Detail A
1
Detail B
Detail C
120
2X3.00 ± 0.10
1
5.175
47.00
5.0
71.00
Back
240
121 1
Side
3.43mm max
Detail of Contacts A
1.20 ± 0.15
Detail of Contacts B
0.80 ± 0.05
Detail of Contacts C
2.50
0.3 ± 0.15
2.50 ± 0.20
0.20
3 ± 0.1
0.3~0.1
1.00
1.50 ± 0.10 5.00
2.50 ± 0.20
3.80
1.27 ± 010mm max
Rev. 0.4 / Jul. 2009
9.50 17.30
30.00
35
7.4 512Mx72 - HMT151R7AFP4C
Front
133.35
Detail B
2.10 ± 0.15
128.95
SPD/TS
4X3.00 ± 0.10
Registering Clock Driver
Detail A
1 120
2X3.00 ± 0.10
1
5.175
47.00 Detail C
5.0 Detail D
71.00
Back
240
121 1
Side
Detail of Contacts A
1.20 ± 0.15 14.90 0.4
2.50 ± 0.20 0.20
Detail of Contacts B
Detail of Contacts C
0.80 ± 0.05
Detail of Contacts D
2.50
3.46mm max
0.3 ± 0.15
3 ± 0.1
3.80
13.60
0.3~0.1
1.00
1.50 ± 0.10 5.00
2.50 ± 0.20
1.27 ± 010mm max
Rev. 0.4 / Jul. 2009
9.50 17.30
30.00
36
7.4 512Mx72 - HMT151R7AFP4C - Heat Spreader
Front
133.75 133.35 127
42.7 20.9 6.35 3.69 5.39 8 7.74
2.786
10
14.214
120
36.7
1
7.36 46.46 80.54
33.4
33.4
119.64
Back
57.2
2.7
121
240
Side
7.19mm max
1.27 ± 010mm max
Rev. 0.4 / Jul. 2009
15.36
22.00
22.00 30.00
2.15
6.3
Registering Clock Driver
Registering Clock Driver
37
7.5 512Mx72 - HMT151R7AFP8C
Front
Detail B
2.10 ± 0.15 14.90 13.60
SPD/TS
3 ± 0.1
Min 1.45
Detail A
1 120
2X3.0 ± 0.10
1
5.175
47.00
Detail C
5.0
Detail D
128.95 133.35
71.00
Back
240
121 1
Side
3.46mm max
Detail of Contacts A
1.20 ± 0.15
Detail of Contacts B
Detail of Contacts C
0.80 ± 0.05
Detail of Contacts D
2.50
14.90 0.4
2.50 ± 0.20 0.20
0.3 ± 0.15
3 ± 0.1
3.80
13.60
0.3~0.1
1.00
1.50 ± 0.10 5.00
2.50 ± 0.20
1.27 ± 010mm max
Rev. 0.4 / Jul. 2009
9.50 17.30 23.30 30.00
3 ± 0.1
Registering Clock Driver
38
7.5 512Mx72 - HMT151R7AFP8C - Heat Spreader
Front
133.75 133.35 127
42.7 20.9 6.35 3.69 5.39 8 7.74
2.786
10
14.214
120
36.7
1
7.36 46.46 80.54
33.4
33.4
119.64
Back
57.2
2.7
121
240
Side
7.19mm max
1.27 ± 010mm max
Rev. 0.4 / Jul. 2009
15.36
22.00
22.00 30.00
2.15
6.3
Registering Clock Driver
Registering Clock Driver
39
7.6
1Gx72 - HMT31GR7AMP4C
Front
133.35
Detail B 2.10 ± 0.15
128.95
SPD/TS
DDP
DDP
DDP
4X3.00 ± 0.10
Registering Clock Driver
DDP
DDP
DDP
DDP
DDP
DDP
Detail A
1
DDP
DDP
DDP
DDP
120
2X3.00 ± 0.10
1
5.175
47.00 Detail C
5.0 Detail D
71.00
Back
DDP DDP DDP DDP DDP
DDP
DDP
DDP
DDP
Registering Clock Driver
DDP
DDP
DDP
DDP
240
DDP
DDP
DDP
DDP
DDP
121 1
Side
Detail of Contacts A
1.20 ± 0.15 14.90 0.4
2.50 ± 0.20 0.20
Detail of Contacts B
Detail of Contacts C
0.80 ± 0.05
Detail of Contacts D
2.50
3.69mm max
0.3 ± 0.15
3 ± 0.1
3.80
13.60
0.3~0.1
1.00
1.50 ± 0.10 5.00
2.50 ± 0.20
1.27 ± 010mm max
Rev. 0.4 / Jul. 2009
9.50 17.30
30.00
DDP
DDP
DDP
DDP
DDP
40
7.6
1Gx72 - HMT31GR7AMP4C - Heat Spreader
Front
133.75 133.35 127
42.7 7.74 17.2 6.1 20.9 6.35 4.06 5.16 1.1 10 2.15 36.7 8.2
2.786
Registering Clock Driver
10.1
12.02
14.214
120 240
6.8
1
7.36 46.46 80.54
33.4
33.4
119.64
Back
57.2
2.7
121
Side
7.35mm max
1.27 ± 010mm max
Rev. 0.4 / Jul. 2009
15.36
22.00
22.00
Registering Clock Driver
41
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