HY57V283220T-6

HY57V283220(L)T(P)/ HY5V22(L)F(P) 4 Banks x 1M x 32Bit Synchronous DRAM Revision History Revision No. History 0.1 Defined Preliminary Specification 0.2 1) 2) 3) 4) 5) 6) 0.3 Defined IDD Spec. 0.4 Delited Preliminary. 0.5 Changed IDD Spec. 0.6 133MHz Speed Added 0.7 Changed FBGA Package Size from 11x13 to 8x13. 0.8 1) Changed VDD min from 3.135V to 3.0V. 2) Changed VIL min from VSSQ-0.3V to -0.3V. 0.9 Modified of size erra. (Page15) (Equation : 13.00 ± 10 -> 13.00 ± 0.10) Remark Modified FBGA Ball Configuration Typo. Changed Functional Block Diagram from A10 to A11. Changed VDD min from 3.0V to 3.135V. Changed Cap. Value from C11, 3, 5 to 4pf & C12, 3.8 to 4pf. Insert tAC2 Value. Insdrt tRAS & CLK Value. This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.9 / July 2004 HY57V283220(L)T(P)/ HY5V22(L)F(P) 4 Banks x 1M x 32Bit Synchronous DRAM DESCRIPTION The Hynix HY57V283220(L)T(P) / HY5V22(L)F(P) is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V283220(L)T(P) / HY5V22(L)F(P) is organized as 4banks of 1,048,576x32. HY57V283220(L)T(P) / HY5V22(L)F(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES • JEDEC standard 3.3V power supply • Auto refresh and self refresh • All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms • 86TSOP-II, 90Ball FBGA with 0.8mm of pin pitch • Programmable Burst Length and Burst Type • All inputs and outputs referenced to positive edge of system clock • Data mask function by DQM0,1,2 and 3 • Internal four banks operation - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst • Programmable CAS Latency ; 2, 3 Clocks • Burst Read Single Write operation ORDERING INFORMATION Part No. Clock Frequency HY57V283220(L)T(P)-5 HY5V22(L)F(P)-5 200MHz HY57V283220(L)T(P)-55 HY5V22(L)F(P)-55 183MHz HY57V283220(L)T(P)-6 HY5V22(L)F(P)-6 166MHz HY57V283220(L)T(P)-7 HY5V22(L)F(P)-7 143MHz HY57V283220(L)T(P)-H HY5V22(L)F(P)-H 133MHz HY57V283220(L)T(P)-8 HY5V22(L)F(P)-8 125MHz HY57V283220(L)T(P)-P HY5V22(L)F(P)-P 100MHz HY57V283220(L)T(P)-S HY5V22(L)F(P)-S 100MHz Organization Interface Package 4Banks x 1Mbits x32 LVTTL 86TSOP-II 90Ball FBGA Note) Hynix supports lead free part for each speed grade with same specification. This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.9 / July 2004 HY57V283220(L)T(P) / HY5V22(L)F(P) PIN CONFIGURATION ( HY57V283220(L)T(P) Series) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 /W E /C A S /R A S /C S A11 BA0 BA1 A 1 0 /A P A0 A1 A2 DQM2 VDD NC D Q 16 VSSQ D Q 17 D Q 18 VDDQ D Q 19 D Q 20 VSSQ D Q 21 D Q 22 VDDQ D Q 23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 8 6 p in T S O P II 4 0 0 m il x 8 7 5 m i l 0 .5 m m p i n p i t c h 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS D Q 15 VSSQ D Q 14 D Q 13 VDDQ D Q 12 D Q 11 VSSQ D Q 10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC C LK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC D Q 31 VDDQ D Q 30 D Q 29 VSSQ D Q 28 D Q 27 VDDQ D Q 26 D Q 25 VSSQ D Q 24 VSS PIN DESCRIPTION PIN PIN NAME DESCRIPTION CLK Clock The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK. CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh CS Chip Select Enables or disables all inputs except CLK, CKE and DQM BA0, BA1 Bank Address Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity A0 ~ A11 Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 RAS, CAS, WE Row Address Strobe, Column Address Strobe, Write Enable RAS, CAS and WE define the operation Refer function truth table for details DQM0~3 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ31 Data Input/Output Multiplexed data input / output pin VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers NC No Connection No connection Rev. 0.9 / July 2004 3 HY57V283220(L)T(P) / HY5V22(L)F(P) Ball CONFIGURATION ( HY5V22(L)F(P) Series) 1 2 3 DQ26 DQ24 DQ28 4 5 6 7 8 9 VSS VDD DQ23 DQ21 VDDQ VSSQ VDDQ VSSQ DQ19 VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ VDDQ DQ31 NC NC DQ16 VSSQ VSS DQM3 A3 A2 DQM2 VDD A B C D E F G A4 A5 A6 A10 A0 A1 Top View H A7 A8 NC NC BA1 A11 CLK CKE A9 BA0 /CS /RAS DQM1 NC NC /CAS /WE DQM0 VDDQ DQ8 VSS VDD DQ7 VSSQ VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 DQ13 DQ15 VSS VDD DQ0 J K L M N P R DQ2 Ball DESCRIPTION PIN PIN NAME DESCRIPTION CLK Clock The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK. CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh CS Chip Select Enables or disables all inputs except CLK, CKE and DQM BA0, BA1 Bank Address Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity A0 ~ A11 Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 RAS, CAS, WE Row Address Strobe, Column Address Strobe, Write Enable RAS, CAS and WE define the operation Refer function truth table for details DQM0~3 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ31 Data Input/Output Multiplexed data input / output pin VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers NC No Connection No connection Rev. 0.9 / July 2004 4 HY57V283220(L)T(P) / HY5V22(L)F(P) FUNCTIONAL BLOCK DIAGRAM 1Mbit x 4banks x 32 I/O Synchronous DRAM Self Refresh Logic & Timer Refresh Counter 1M x32 Bank 3 CLK Row Active Column Active Memory Cell Array Column Pre Decoder DQ0 I/O Buffer & Logic WE DQM0 DQM1 DQM2 DQM3 1M x32 Bank 0 X decoder CAS 1M x32 Bank 1 Sense AMP & I/O Gate RAS State Machine CS 1M x32 Bank 2 X decoder X decoder X decoder CKE Row Pre Decoder Y decoder Bank Select A0 A1 DQ1 DQ30 DQ31 Column Add Counter Address Register Address buffers A11 BA0 BA1 Rev. 0.9 / July 2004 Burst Counter Mode Register CAS Latency Data Out Control Pipe Line Control 5 HY57V283220(L)T(P) / HY5V22(L)F(P) ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 °C Storage Temperature TSTG -55 ~ 125 °C Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 1 W Soldering Temperature Þ Time TSOLDER 260 ⋅ 10 °C ⋅ Sec Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITION (TA=0 to 70°C) Parameter Symbol Min Typ. Max Unit Note Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1 Input high voltage VIH 2.0 3.0 VDDQ + 0.3 V 1,2 Input low voltage VIL - 0.3 0 0.8 V 1,3 Note Note : 1.All voltages are referenced to VSS = 0V 2.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration with no input clamp diodes 3.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration with no input clamp diodes AC OPERATING CONDITION (TA=0 to 70°C, 3.0V ≤VDD ≤3.6V, VSS=0V - Note1) Parameter Symbol Value Unit VIH / VIL 2.4/0.4 V Vtrip 1.4 V Input rise / fall time tR / tF 1 ns Output timing measurement reference level Voutref 1.4 V CL 30 pF AC input high / low level voltage Input timing measurement reference level voltage Output load capacitance for access time measurement 1 Note : 1.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF) For details, refer to AC/DC output load circuit Rev. 0.9 / July 2004 6 HY57V283220(L)T(P) / HY5V22(L)F(P) CAPACITANCE ( HY57V283220T Series) (TA=25°C, f=1MHz, VDD=3.3V) Parameter Pin Input capacitance Data input / output capacitance Symbol Min Max Unit CLK CI1 2.5 4.0 pF A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM0~3 CI2 2.5 4.0 pF DQ0 ~ DQ31 CI/O 4.0 6.5 pF OUTPUT LOAD CIRCUIT Vtt=1.4V Vtt=1.4V RT=500 Ω Output Output RT=50 Ω Z0 = 50Ω 30pF 30pF DC Output Load Circuit AC Output Load Circuit DC CHARACTERISTICS I (DC operating conditions unless otherwise noted) Parameter Symbol Min. Max Unit Note Input leakage current ILI -1 1 uA 1 Output leakage current ILO -1 1 uA 2 Output high voltage VOH 2.4 - V IOH = -2mA Output low voltage VOL - 0.4 V IOL = +2mA Note : 1.VIN = 0 to 3.6V, All other pins are not under test = 0V 2.DOUT is disabled, VOUT=0 to 3.6V Rev. 0.9 / July 2004 7 HY57V283220(L)T(P) / HY5V22(L)F(P) DC CHARACTERISTICS II (DC operating conditions unless otherwise noted) Speed Parameter Operating Current Precharge Standby Current in power down mode Symbol -5 -55 -6 -7 -H -8 -P S 120 120 110 100 100 100 90 90 IDD1 Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mA IDD2P CKE ≤ VIL(max), tCK = 10ns 2 IDD2PS CKE ≤ VIL(max), tCK = ∞ 1 IDD2N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 10ns Input signals are changed one time during 2clks. All other pins ≥ VDD0.2V or ≤ 0.2V 14 IDD2NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 9 IDD3P CKE ≤ VIL(max), tCK = 10ns 7 IDD3PS CKE ≤ VIL(max), tCK = ∞ 6 Unit Note mA 1 mA Precharge Standby Current in non power down mode Active Standby Current in power down mode Test Condition mA mA IDD3N Active Standby Current in non power down mode IDD3NS CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 10ns Input signals are changed 17 one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V mA CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 13 ttCK ≥ tCK(min), IOL=0mA CL=3 230 220 200 180 180 150 130 130 All banks active CL=2 - - - - - - 130 130 170 160 150 140 140 140 140 140 Burst Mode Operating Current IDD4 Auto Refresh Current IDD5 tRC ≥ tRC(min), All banks active Self Refresh Current IDD6 CKE ≤ 0.2V mA 1 mA 2 2 3 mA 0.8 4 Note : 1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3.HY57V283220T(P)(HY5V22F(P))-5/55/6/7/H/8/P/S 4.HY57V283220LT(P)(HY5V22LF(P))-5/55/6/7/H/8/P/S Rev. 0.9 / July 2004 8 HY57V283220(L)T(P) / HY5V22(L)F(P) AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) -5 Parameter CAS Latency = 3 tCK3 Max 5 Min Max 5.5 1000 CAS Latency = 2 -6 -7 -H -8 -P -S Unit Note Min System clock cycle time -55 Symbol Min Max 6 1000 Max 7 1000 Max 7.5 1000 10 Min Max 8 1000 10 Min Max 10 1000 -10 Min Max 10 1000 10 ns 1000 10 Clock high pulse width tCHW 2 - 2.25 - 2.5 - 3 - 3 - 3 - 3 - 3 - ns 1 Clock low pulse width tCLW 2 - 2.25 - 2.5 - 3 - 3 - 3 - 3 - 3 - ns 1 CAS Latency = 3 tAC3 - 4.5 - 5 - 5.5 - 5.5 - 5.5 - 6 - 6 - 6 ns CAS Latency = 2 tAC2 - 6 - 6 - 6 - 6 - 6 - 6 - 6 - 6 ns Data-out hold time tOH 1.5 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - ns 3 Data-Input setup time tDS 1.5 - 1.5 - 1.5 - 1.75 - 1.75 - 2 - 2 - 2 - ns 1 Data-Input hold time tDH 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - ns 1 Address setup time tAS 1.5 - 1.5 - 1.5 - 1.75 - 1.75 - 2 - 2 - 2 - ns 1 Address hold time tAH 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - ns 1 CKE setup time tCKS 1.5 - 1.5 - 1.5 - 1.75 - 1.75 - 2 - 2 - 2 - ns 1 CKE hold time tCKH 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - ns 1 Command setup time tCS 1.5 - 1.5 - 1.5 - 1.75 - 1.75 - 2 - 2 - 2 - ns 1 Command hold time tCH 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - ns 1 CLK to data output in low Z-time tOLZ 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - ns CAS Latency = 3 tOHZ3 - 4.5 - 5 - 5.5 - 5.5 - 5.5 - 6 - 6 - 6 ns CAS Latency = 2 tOHZ2 - 6 - 6 - 6 - 6 - 6 - 6 - 6 - 6 ns CLK to data output in high Z-time 10 Min tCK2 Access time from clock 10 Min 12 ns 2 Note : 1.Assume tR / tF (input rise and fall time ) is 1ns 2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v 3.Data-out hold time to be measured under 30pF load condition, without Vt termination Rev. 0.9 / July 2004 9 HY57V283220(L)T(P) / HY5V22(L)F(P) AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) -5 Parameter -55 -6 -7 -H -8 -P -S Symbol Unit Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Operation tRC 55 - 55 - 60 - 63 - 63 - 64 - 70 - 70 - ns Auto Refresh tRRC 55 - 55 - 60 - 63 - 63 - 64 - 70 - 70 - ns RAS to CAS delay tRCD 15 - 16.5 - 18 - 20 - 20 - 20 - 20 - 20 - ns RAS active time tRAS 38.7 100 K 38.7 100 K 42 100 K 42 100 K 42 100 K 48 100 K 50 100 K 50 100 K ns RAS precharge time tRP 15 - 16.5 - 18 - 20 - 20 - 20 - 20 - 20 - ns RAS to RAS bank active delay tRRD 2 - 2 - 2 - 2 - 2 - 2 - 20 - 20 - CLK CAS to CAS delay tCCD 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK Write command to data-in delay tWTL 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - CLK Data-in to precharge command tDPL 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK Data-in to active command tDAL 4 - 4 - 4 - 4 - 4 - 4 - 4 - 4 - CLK DQM to data-out Hi-Z tDQZ 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK DQM to data-in mask tDQM 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - CLK MRS to new command tMRD 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK CAS Latency = 3 tPROZ3 3 - 3 - 3 - 3 - 3 - 3 - 3 - 3 - CLK CAS Latency = 2 tPROZ2 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK Power down exit time tPDE 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK Self refresh exit time tSRE 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK Refresh Time tREF - 64 - 64 - 64 - 64 - 64 - 64 - 64 - 64 ms Note RAS cycle time Precharge to data output Hi-Z 1 Note : 1. A new command can be given tRRC after self refresh exit Rev. 0.9 / July 2004 10 HY57V283220(L)T(P) / HY5V22(L)F(P) DEVICE OPERATING OPTION TABLE HY5xxxxxxxxx(P)-5 200MHz(5ns) CAS Latency tRCD tRAS tRC tRP tAC tOH 3CLKs 3CLKs 8CLKs 11CLKs 3CLKs 4.5ns 1.5ns 183MHz(5.5ns) 3CLKs 3CLKs 8CLKs 10CLKs 3CLKs 5ns 2ns 166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2ns tRCD tRAS tRC tRP tAC tOH 2ns HY5xxxxxxxxx(P)-55 CAS Latency 183MHz(5.5ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5ns 166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2ns 143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.5ns 2ns HY5xxxxxxxxx(P)-6 CAS Latency tRCD tRAS tRC tRP tAC tOH 166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2ns 143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.5ns 2ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2.5ns CAS Latency tRCD tRAS tRC tRP tAC tOH 143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.5ns 2ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2ns HY5xxxxxxxxx(P)-7 HY5xxxxxxxxx(P)-H CAS Latency tRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.5ns 2ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2ns CAS Latency tRCD tRAS tRC tRP tAC tOH 2ns HY5xxxxxxxxx(P)-8 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2ns 83MHz(12ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 2.5ns Rev. 0.9 / July 2004 11 HY57V283220(L)T(P) / HY5V22(L)F(P) HY5xxxxxxxxx(P)-P CAS Latency tRCD tRAS tRC tRP tAC tOH 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2ns 83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.5ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 2.5ns CAS Latency tRCD tRAS tRC tRP tAC tOH 100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2ns 83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.5ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 2.5ns HY5xxxxxxxxx(P)-S Rev. 0.9 / July 2004 12 HY57V283220(L)T(P) / HY5V22(L)F(P) COMMAND TRUTH TABLE Command A10/ AP CKEn-1 CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X OP code No Operation H X H X X X L H H H X X Bank Active H X L L H H X H X L H L H X CA H X L H L L X CA H X L L H L X X Burst Stop H X L H H L X X DQM H V X Auto Refresh H H L L L H X X Burst-Read-Single-WRITE H X L L L L X A9 Pin High (Other Pins OP code) Entry H L L L L H X Exit L H H X X X L H H H Entry H L H X X X L H H H H X X X L H H H H X X X L V V V Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Self Refresh1 X Precharge power down Clock Suspend Exit L H Entry H L Exit L H X ADDR RA BA Note V L H L H V V H X L V X 3 X X X X X X X Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Don¢t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation 3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1. Rev. 0.9 / July 2004 13 HY57V283220(L)T(P) / HY5V22(L)F(P) PACKAGE INFORMATION (HY57V283220T(P) Series) 400mil 86pin Thin Small Outline Package Unit : mm(inch) 11.938(0.4700) 11.735(0.4620) 22.327(0.8790) 22.149(0.8720) 10.262(0.4040) 10.058(0.3960) 0.150(0.0059) 0.050(0.0020) 0.50(0.0197) Rev. 0.9 / July 2004 0.21(0.008) 0.18(0.007) 1.194(0.0470) 0.991(0.0390) 5deg 0deg 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0047) 14 HY57V283220(L)T(P) / HY5V22(L)F(P) PACKAGE INFORMATION (HY5V22F(P) Series) 90Ball FBGA with 0.8mm of pin pitch (Ball-side view) 6.40 0.80(typ) pin#1 ID 0.80 typ 11.20 13.00 ± 0.10 5.60 ± 0.5 6.50 ± 0.5 3.20 ± 0.5 4.00 ± 0.5 8.00 1.20max Ball Size 0.45 ± 0.05mm 0.850+/-0.075 seating plane Rev. 0.9 / July 2004 15