X76F101SIG-3.0

This X76F101 device has been acquired by IC MICROSYSTEMS from Xicor, Inc. ICmic TM IC MICROSYSTEMS 1K X76F101 Secure SerialFlash DESCRIPTION 128 x 8 bit FEATURES •64-bit Password Security •One Array (112 Bytes) Two Passwords —Read Password —Write Password The X76F101 is a Password Access Security Supervisor, containing one 896-bit Secure Serial Flash array. Access to the memory array can be controlled by two 64-bit passwords. These passwords protect read and write •Programmable Passwords •32-bit Response to Reset (RST Input) •8 byte Sector Write mode operations of the memory array. The X76F101 features a serial interface and software protocol allowing operation on a popular two wire bus. The bus signals are a clock Input (SCL) and a bidirectional data input and output (SDA). Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X76F101 also features a synchronous response to reset providing an automatic output of a hard-wired 32-bit data stream conforming to the industry standard for memory cards. TM The X76F101 utilizes Xicor’s proprietary Direct Write •1MHz Clock Rate •2 wire Serial Interface •Low Power CMOS —3.0 to 5.5V operation —Standby current Less than 1µA —Active current less than 3 mA •High Reliability Endurance: —100,000 Write Cycles •Data Retention: 100 years •Available in: —8 lead PDIP, SOIC, MSOP and ISO Card —SmartCard Module cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. Functional Diagram 8K BYTE CHIP ENABLE DATA TRANSFER ARRAY ACCESS ENABLE CS SCL SDA SerialFlash ARRAY ARRAY 0 (PASSWORD PROTECTED) Interface Logic PASSWORD ARRAY AND PASSWORD 32 BYTE SerialFlash ARRAY 112 Byte ARRAY 1 (PASSWORD PROTECTED) VERIFICATION LOGIC RST RESET RESPONSE REGISTER RETRY COUNTER 7025 FM 01 ©Xicor, Inc. 1994, 1995, 1996 Patents Pending 7065 -1.1 4/17/98 T2/C0/D0 SH 1 Characteristics subject to change without notice X76F101 PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. To ensure the correct communication, RST must remain LOW under all conditions except when running a “Response to Reset sequence”. Data is transferred in 8-bit segments, with each transfer being followed by an ACK, generated by the receiving device. If the X76F101 is in a nonvolatile write cycle a “no ACK” (SDA=High) response will be issued in response to loading of the command byte. If a stop is issued prior to the nonvolatile write cycle the write operation will be terminated and the part will reset and enter into a standby mode. The basic sequence is illustrated in Figure 1. Serial Data (SDA) SDA is an open drain serial data input/output pin. During a read cycle, data is shifted out on this pin. During a write cycle, data is shifted in on this pin. In all other cases, this pin is in a high impedance state. Chip Select (CS) When CS is high, the X76F101 is deselected and the SDA pin is at high impedance and unless an internal write operation is underway, the X76F101 will be in standby mode. CS low enables the X76F101, placing it in the active mode. Reset (RST) RST is a device reset pin. When RST is pulsed high while CS is low the X76F101 will output 32 bits of fixed data which conforms to the standard for “synchronous response to reset”. CS must remain LOW and the part must not be in a write cycle for the response to reset to occur. See Figure 7. If at any time during the response to reset CS goes HIGH, the response to reset will be aborted and the part will return to the standby state. The response to reset is "mask programmable" only! PIN NAMES Symbol CS SDA SCL RST Vcc Vss NC Description Chip Select Input Serial Data Input/Output Serial Clock Input Reset Input Supply Voltage Ground No Connect DEVICE OPERATION The X76F101 memory array consists of fourteen 8-byte sectors. Read or write access to the array always begins at the first address of the sector. Read operations then can continue indefinitely. Write operations must total 8 PIN CONFIGURATION PDIP VCC NC NC Vss 1 2 3 4 SOIC VSS CS SDA NC 1 2 3 4 MSOP VSS NC CS SDA 1 2 3 4 8 7 6 5 VCC NC RST SCL 8 7 6 5 VCC RST SCL NC VCC RST SCL NC GND CS SDA NC 8 7 6 5 RST SCL SDA CS Smart Card bytes. There are two primary modes of operation for the X76F101; Protected READ and protected WRITE. Protected operations must be performed with one of two 8-byte passwords. The basic method of communication for the device is established by first enabling the device (CS LOW), generating a start condition, then transmitting a command, followed by the correct password. All parts will be shipped from the factory with all passwords equal to ‘0’. The user must perform ACK Polling to determine the validity of the password, before starting a data transfer (see Acknowledge Polling.) Only after the correct password is accepted and a ACK polling has been performed, can the data transfer occur. 2 X76F101 After each transaction is completed, the X76F101 will reset and enter into a standby mode. This will also be the A start may be issued to terminate the input of a control byte or the input data to be written. This will reset the device and leave it ready to begin a new read or write command. Because of the push/pull output, a start cannot be generated while the part is outputting data. Starts are inhibited while a write is in progress. Stop Condition response if an unsuccessful attempt is made to access a protected array. Figure 1. X76F101 Device Operation LOAD COMMAND/ADDRESS BYTE All communications must be terminated by a stop condition. The stop condition is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to reset the device during a command or data input sequence and will leave the device in the standby power mode. As with starts, stops are inhibited when outputting data and while a write is in progress. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. The X76F101 will respond with an acknowledge after recognition of a start condition and its slave address. If LOAD 8-BYTE PASSWORD VERIFY PASSWORD ACCEPTANCE BY USE OF ACK POLLING READ/WRITE DATA BYTES Device Protocol The X76F101 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data both the device and a write condition have been selected, the X76F101 will respond with an acknowledge after the receipt of each subsequent eight-bit word. onto the bus as a transmitter and the receiving device as a receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X76F101 will be considered a slave in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figure 2 and Figure 3. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X76F101 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. 3 X76F101 Figure 2. Data Validity SCL SDA Data Stable Data Change Figure 3. Definition of Start and Stop Conditions SCL SDA Start Condition Stop Condition Table 1. X76F101 Instruction Set Command after Start Command Description Sector Write Sector Read Change Write Password Change Read Password Password ACK Command Password used 1 0 0 S3 S2 S1 S00 1 0 0 S3 S2 S1 S0 1 11111100 11111110 01010101 Write Read Write Write None Illegal command codes will be disregarded. The part will respond with a “no-ACK” to the illegal byte and then return to the standby mode. All write/read operations require a password. PROGRAM OPERATIONS Sector Write The sector write mode requires issuing the 8-bit write command followed by the password and then the data issued which starts the nonvolatile write cycle. If more or less than 8 bytes are transferred, the data in the sector remains unchanged. ACK Polling Once a stop condition is issued to indicate the end of the host’s write sequence, the X76F101 initiates the internal nonvolatile write cycle. In order to take advantage of the typical 5ms write cycle, ACK polling can begin immediately. This involves issuing the start condition bytes transferred as illustrated in figure 4. The write command byte contains the address of the sector to be written. Data is written starting at the first address of a sector and eight bytes must be transferred. After the last byte to be transferred is acknowledged a stop condition is 4 X76F101 followed by the new command code of 8 bits (1st byte of the protocol.) If the X76F101 is still busy with the nonvolatile write operation, it will issue a “no-ACK” in response. If the nonvolatile write operation has Password ACK Polling Sequence PASSWORD LOAD COMPLETED completed, an “ACK” will be returned and the host can then proceed with the rest of the protocol. ENTER ACK POLLING Data ACK Polling Sequence WRITE SEQUENCE COMPLETED ISSUE START ENTER ACK POLLING ISSUE PASSWORD ACK COMMAND ISSUE START ACK RETURNED? NO ISSUE NEW COMMAND CODE YES PROCEED ACK RETURNED? NO YES PROCEED READ OPERATIONS Read operations are initiated in the same manner as write operations but with a different command code. After the password sequence, there is always a nonvolatile write cycle. This is done to discourage random guesses of the password if the device is being tampered with. In order to continue the transaction, the X76F101 requires the master to perform a password ACK polling sequence with the specific command code of 55h. As with regular Acknowledge polling the user can either time out for 10ms, and then issue the ACK polling once, or Sector Read W ith sector read, a sector address is supplied with the read command. Once the password has been acknowledged data may be read from the sector. An acknowledge must follow each 8-bit data transfer. A read operation always begins at the first byte in the sector, but may stop at any time. Random accesses to the array are not possible. Continuous reading from the array will return data from successive sectors. After reading the last sector in the array, the address is automatically set to the first sector in the array and data can continue to be continuously loop as described in the flow. If the password that was inserted was correct, then an “ACK” will be returned once the nonvolatile cycle in response to the password ACK polling sequence is over. If the password that was inserted was incorrect, then a “no ACK” will be returned even if the nonvolatile cycle is over. Therefore, the user cannot be certain that the password is incorrect until the 10ms write cycle time has read out. After the last bit has been read, a stop condition is generated without sending a preceding acknowledge. elapsed. 5 X76F101 Figure 4. Sector Write Sequence (Password Required) START Write Password Write Password Host Commands X76F101 Response WRITE COMMAND 7 0 W ait tWC OR SDA S ACK ACK ACK ACK STOP P Password ACK Command If ACK, Then Password Matches Host Commands START ACK Password ACK COMMAND S no-ACK ACK ACK X76F101 Responce ... ACK ACK ACK W ait tWC Data ACK Polling Figure 5. Acknowledge Polling SCL pwd. byte 8th clk. of 8th ‘ACK’ clk 8th clk ‘ACK’ clk SDA ‘ACK’ START condition 8th bit ACK or no ACK Figure 6. Sector Read Sequence (Password Required) Host Commands X76F101 Response START Read Password Read Password READ COMMAND 7 0 W ait tWC OR SDA S ACK ACK ACK ACK Data n STOP P Password ACK Command If ACK, Then Password Matches Host Commands START ACK Password ACK COMMAND S X76F101 Responce ... ACK Data 0 no-ACK 6 ACK X76F101 PASSWORDS Passwords are changed by sending the "change read password" or "change write password" commands in a normal sector write operation. A full eight bytes containing the new password must be sent, following This conforms to the ISO standard for “synchronous response to reset”. CS must remain LOW and the part must not be in a write cycle for the response to reset to occur. After initiating a nonvolatile write cycle the RST pin must not be pulsed until the nonvolatile write cycle is complete. If not, the ISO response will not be activated. Also, any attempt to pulse the RST pin in the middle of an ISO successful transmission of the current write password and a valid password ACK response. The user can use a repeated ACK Polling command to check that a new password has been written correctly. An ACK indicates that the new password is valid. There is no way to read any of the passwords. transaction will stop the transaction with the SDA pin in high impedance. The user will have to issue a stop condition and start the transaction again. If at any time during the Response to Reset CS goes HIGH, the response to reset will be aborted and the part will return to the standby state. A Response to Reset is not RESPONSE TO RESET (DEFAULT = 19 01 AA 55) The ISO Response to reset is controlled by the RST, CS and CLK pins. When RST is pulsed high, while CS is low, available during a nonvolatile write cycle. Continued clocks after the 32 bits, will output the 32 bit sequence again, starting at byte 0. the device will output 32 bits of data, one bit per clock. Figure 7. Response to RESET (RST) CS RST SCK SO LSB Byte 0 MSB LSB 1 MSB LSB 2 MSB LSB 3 MSB ABSOLUTE MAXIMUM RATINGS* Temperature under Bias .....................–65°C to +135°C Storage Temperature.......................... –65°C to +150°C Voltage on any Pin with Respect to V S ....................................... –1V to +7V S D.C. Output Current .................................................. 5mA Lead Temperature (Soldering, 10 seconds) .................................. 300°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7 X76F101 RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial Industrial 0° C –40° C +70° C +85° C Supply Voltage X76F101 X76F101 – 3 Limits 4.5V to 5.5V 3.0V to 5.5V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol ICC1 ICC2(3) ISB1(1) ISB2(1) ILI ILO VIL (2) VIH (2) VOL (Read) Parameter VCC Supply Current VCC Supply Current (Write) Limits Min. Max. 1 Units mA Test Conditions fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 KHz, SDA = Open RST = CS = V SS 3 1 1 10 10 VCC x 0.3 –0.5 VCC x 0.7VCC + 0.5 0.4 mA µA µA µA µA V V V fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 KHz, SDA = Open RST = CS = V SS VCC Supply Current (Standby) (Standby) VCC Supply Current Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage VIL = VCC x 0.1, VIH = VCC x 0.9 fSCL = 400 KHz, fSDA = 400 KHz VSDA = VSCC = VCC Other = GND or VCC–0.3V VIN = VSS to VCC VOUT = VSS to VCC IOL = 3mA CAPACITANCE TA = +25° f = 1MHz, VCC = 5V C, Symbol COUT (3) CIN (3) Test Output Capacitance (SDA) Input Capacitance (RST, SCL, CS) Max. 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V NOTES: (1) Must perform a stop command after a read command prior to measurement (2) VIL min. and VH max. are for reference only and are not tested. I (3) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT 5V 1.53KΟ OUTPUT 100pF OUTPUT 100pF 3V 1.3KΟ A.C. TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Level Output Load VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 100pF 8 X76F101 AC CHARACTERISTICS (TA = -40˚C to +85˚C, VCC = +3.0V to +5.5V, unless otherwise specified.) Symbol fSCL tAA (3) Parameter SCL Clock Frequency SCL LOW to SDA Data Out Valid Time the Bus Must Be Free Before a New Transmission Can Start Min 0 0.1 1.2 0.6 1.2 0.6 0.6 0 100 20+0.1XCb 20+0.1XCb (2) (2) Max 1 0.9 Units MHz ∝s ∝s ∝s ∝s ∝s ∝s ∝s ns tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH tNOL tRDV tCDV tDHZ(1) tSR(1) tRST tSU:RST tSU:CS tSU:CS Start Condition Hold Time Clock LOW Period Clock HIGH Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time RST to SCL Non-Overlap RST LOW to SDA Valid During Response to Reset CLK LOW to SDA Valid During Response to Reset Device Deselect to SDA high impedance Device Select to RST active RST High Time RST Setup Time CS Setup Time CS Hold Time 300 300 ns ns ∝s 0.6 0.1 ∝s ns 450 450 450 ns ns ns ns ∝s ns ns ns 500 0 0 0 0 1.5 500 200 100 Notes:1. These Specs are not defined in the ISO 7816-3 Standard, since CS is not defined. 2. Cb = total capacitance of one bus line in pF 3. tAA = 1.1µs Max below VCC = 3.0V. RESET AC SPECIFICATIONS Power Up Timing Symbol tPUR (1) (1) Parameter Time from Power Up to Read Time from Power Up to Write Min. Typ (2) Max. 1 5 Units mS mS tPUW Notes:1. 2. Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. Typical values are for TA = 25˚C and VCC = 5.0V 9 X76F101 Nonvolatile Write Cycle Timing Symbol tWC (1) Parameter W rite Cycle Time Min. Typ.(1) 5 Max. 10 Units mS Notes:1. tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. BUS TIMING t F t HIGH t LOW t R SCL t SU:STA t HD:STA t HD:DAT t SU:DAT t SU:STO SDA IN t AA t DH t BUF SDA OUT Write Cycle Timing SCL SDA 8th bit of last byte ACK tWC Stop Condition Start Condition CS Timing Diagram (Selecting/Deselecting the Part) SCL tSU:CS CS from tHD:CS master 10 X76F101 RST Timing Diagram – Response to a Synchronous Reset tSR CS RST tRST tNOL tNOL 1st clk tHIGH_RST 2nd clk 3rd clk CLK pulse tRDV I/O tSU:RST DATA BIT (1) pulse tLOW_RST pulse tCDV DATA BIT (2) CS RST CLK tDHZ I/O DATA BIT (N) DATA BIT (N+1) (N+2) GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS 100 80 60 40 20 R R Pull Up Resistance in KΟ RMAX MIN = -------------------------- 1.8KΟ = I OLMIN V CCMAX RMIN 20 Bus capacitance in pF MAX =C ---------------BUS t R 40 60 80 100 tR = maximum allowable SDA rise time 11 X76F101 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 0.430 (10.92) 0.360 (9.14) 0.260 (6.60) 0.240 (6.10) PIN 1 INDEX PIN 1 0.300 (7.62) REF. 0.060 (1.52) 0.020 (0.51) HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL SEATING PLANE 0.145 (3.68) 0.128 (3.25) 0.150 (3.81) 0.125 (3.18) 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.110 (2.79) 0.090 (2.29) 0.020 (0.51) 0.016 (0.41) .073 (1.84) MAX. 0.325 (8.25) 0.300 (7.62) TYP . 0.010 (0.25) 0° 15° NOTE: 1.ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 12 X76F101 PACKAGING INFORMATION 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.020 (.508) 0.012 (.305) PIN 1 INDEX PIN 1 ID PIN 1 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) .213 0.244 (6.20) .330 (5.41) .205 (8.38) .300 (5.21) (7.62) 0.014 (0.35) 0.019 (0.49) .050 (1.27) BSC 0.188 (4.78) 0.197 (5.00) .212 (5.38) .203 (5.16) .080 (2.03) .070 (1.78) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.050 (1.27) 0.004 (0.19) .013 0.010 (0.25) (.330) .004 (.102) 0 8 REF 0.050" TYPICAL .010 (.254) .007 (.178) .035 (.889) .020 (.508) 0.050" TYPICAL 0.010 (0.25) 0.020 (0.50) X 45° 0° – 8° 0.250" 0.016 (0.410) 0.037 (0.937) NOTE: 0.0075 (0.19) 0.010 (0.25) 1. ALL DIMENSIONS IN INCHES (IN P FOOTPRINT 7025 FM 24 0.030" TYPICAL 8 PLACES ARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 13 X76F101 8-LEAD MINIATURE SMALL OUTLINE GULL WING PACKAGE TYPE M 0.118 ± 0.002 (3.00 ± 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) TYP R 0.014 (0.36) 0.118 ± 0.002 (3.00 ± 0.05) 0.030 (0.76) 0.0216 (0.55) 0.036 (0.91) 0.032 (0.81) 7° TYP 0.0256" TYPICAL 0.040 ± 0.002 (1.02 ± 0.05) 0.008 (0.20) 0.004 (0.10) 0.025" TYPICAL 0.220" 0.007 (0.18) 0.005 (0.13) 0.150 (3.81) REF. 0.193 (4.90) REF. 0.020" TYPICAL FOOTPRINT 8 PLACES NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS) 3003 ILL 01 14 X76F101 8 PAD CHIP ON BOARD SMART CARD MODULE TYPE X SMART CARD TYPE Y 3° MAX. DRAFT ANGLE (ALL AROUND) 3.369 ± 0.002 (85.57 ± 0.05) 0.593 ± 0.002 (15.06 ± 0.05) R. 0.125 (3.18) (4x) 0.430 ± 0.002 (10.92 ± 0.05) A 0.010 0.25) 2.125 ± 0.00 (53.98 ± 0.05 A R. 0.030 (0.76) (4x) 15 X76F101 X76F041 8 PAD CHIP ON BOARD SMART CARD MODULE TYPE X 0.465 ± 0.002 (11.81 ± 0.05) 0.088 (2.24) MIN EPOXY FREE AREA (TYP.) 0.285 (7.24) MAX. SEE NOTE 7 SHT. 2 R. 0.078 (2.00) 0.069 (1.75) MIN EPOXY FREE AREA (TYP.) 0.270 (6.86) MAX. SEE NOTE 7 SHT. 2 0.420 ± 0.002 (10.67 ± 0.05) A A 0.008 ± 0.001 (0.20 ± 0.03) 0.210 ± 0.002 (5.33 ± 0.05) 0.233 ± 0.002 (5.92 ± 0.05) SECTION A-A FR4 TAPE DIE GLOB SIZE 0.0235 (0.60) MAX. 0.015 (0.38) MAX. 0.008 (0.20) MAX. SEE DETAIL SHEET 3 COPPER, NICKEL PLATED, GOLD FLASH 0.146 ± 0.002 (3.71 ± 0.05) 0.174 ± 0.002 (4.42 ± 0.05) R. 0.013 (0.33) (8x) Vcc 0.105 ± 0.002 (2.67 ± 0.05) TYP. Vss RST CS (8x) SCL SDA 0.105 ± 0.002 (8x) (2.67 ± 0.05) NC NC NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS) SC Type X ILL 1.0 16 X76F101 ORDERING INFORMATION X76F101 Device P T G -V VCC Limits Blank = 5V ±10% 3.0 = 3.0V to 5.5V G = RoHS Compliant Lead Free package Blank = Standard package. Non lead free Temperature Range Blank = Commercial = 0° to +70° C C I = Industrial= –40° to +85° C C Package S = 8-Lead SOIC M = 8- Lead MSOP P = 8-Lead PDIP H = Die in Waffle Packs W = Die in Wafer Form X = Smart Card Module Y = Smart Card Part Mark Convention 8-Lead MSOP EYWW XXX 8-Lead SOIC/PDIP X76F101 XG XX A = 8-Lead SOIC G = RoHS compliant Lead Free AAQ = 3.0 to 5.5V, 0 to +76° C AAR = 3.0 to 5.5V, -40 to +85° C AAS = 4.5 to 5.5V, 0 to +76° C AAT = 4.5 to 5.5V, -40 to +85° C D = 3.0 to 5.5V, 0 to +70°C E = 3.0 to 5.5V, -40 to +85°C Blank = 4.5 to 5.5V, 0 to +70° C I = 4.5 to 5.5V, -40 to +85°C LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 17