IC61SF51218D-7.5BI

IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D Document Title 8Mb SyncBurst Flow through SRAM Revision History Revision No 0A History Initial Draft Draft Date September 3,2002 Remark The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 1 IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D 256K x 32, 256K x 36, 512K x 18 8Mb SYNCBURST Flow throughSRAMs FEATURES • • • • • • • • • • • • • • Flowthrough Mode operation. User-selectable Output Drive Strength with XQ Mode. Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Pentium™ or linear burst sequence control using MODE input Common data inputs and data outputs JEDEC 100-Pin TQFP and 119-pin PBGA package Single +3.3V, +10%, –5% core power supply Power-down snooze mode 2.5V or 3.3V I/O Supply Snooze MODE for reduced-power standby T version (three chip selects) D version (two chip selects) DESCRIPTION ICSI's 8Mb SyncBurst Flowthrough SRAMs integrate a 512k x 18, 256k x 32, or 256k x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. Applications The ICSI SyncBurst Flowthrough SRAM family employs highspeed ,low-power CMOS designs that are fabricated using an advanced CMOS process to provide Level 2 Cache applications supporting Pentium and PowerPC microprocessors originally, the device now finds application ranging from DSP main store to networking chip set support. Controls All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. Byte Write and Global Write Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs.Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE).input combined with one or more individualbyte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. IOL/IOH Drive strength Options The XQ pin allows selection between high drive strength (XQ low) for multi-drop bus applications and normal drive strength (XQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details. Snooze Mode Low power (Snooze mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Snooze mode. FAST ACCESS TIME Symbol -6.5 Flow tKQ 6.5 Through tKC 7.5 2-1-1-1 ICC1 270 -7.5 7.5 8.5 260 -8.5 8.5 10 240 -9.5 9.5 11 230 Units ns ns mA ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D BLOCK DIAGRAM MODE Q0 A0' CLK CLK A0 BINARY COUNTER ADV ADSC ADSP Q1 A1' A1 256Kx32; 256Kx36; 512Kx18 MEMORY ARRAY 18/19 16/17 D Q 18/19 An-A0 ADDRESS REGISTER CLK 32, 36, or 18 32, 36, or 18 GW BWE BWd (x32/x36) DQd BYTE WRITE REGISTERS CLK D Q BWb (x32/x36) D DQc Q BYTE WRITE REGISTERS CLK BWa (x32/x36/x18) DQb BYTE WRITE REGISTERS CLK D Q BWa (x32/x36/x18) D DQa Q BYTE WRITE REGISTERS CLK (T, D)CE (T, D) CE2 (T) CE2 D Q 4 ENABLE REGISTER CLK INPUT REGISTERS CLK OUTPUT REGISTERS CLK OE 32, 36, or 18 DQa - DQd D Q ENABLE DELAY REGISTER CLK OE Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 3 IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D PIN CONFIGURATION 119-pin PBGA (Top View) 1 A VCCQ B NC C NC D DQc1 E DQc2 F VCCQ G DQc5 H DQc7 J VCCQ K DQd1 L DQd4 M VCCQ N DQd6 P DQd8 R NC T NC U VCCQ NC NC NC NC NC VCCQ MODE SA SA SA SA A1 A0 NC NC GND VCC NC NC A10 SA SA SA SA SA SA 100-Pin TQFP (D Version) 6 7 SA SA CE CE2 BWd BWc BWb BWa SA VCC GND CLK GW BWE OE ADSC ADSP ADV SA SA 2 3 4 5 SA CE2 SA NC DQc3 DQc4 DQc6 DQc8 VCC DQd2 DQd3 DQd5 DQd7 NC SA NC SA SA SA GND GND GND BWc GND NC GND BWd GND GND GND MODE SA ADSP ADSC VCC XQ CE OE ADV GW VCC CLK NC BWE A1 A0 VCC SA SA SA SA GND GND GND BWb GND NC GND BWa GND GND GND GND/NC SA SA SA SA NC DQb6 DQb5 DQb4 DQb2 VCC DQa7 DQa5 DQa4 DQa3 NC SA NC VCCQ NC NC DQb8 DQb7 VCCQ DQb3 DQb1 VCCQ DQa8 DQa6 VCCQ DQa2 DQa1 NC ZZ NC DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 GND/NC VCC XQ GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 NC Note:Ball R5 no connection is acceptable 256K x 32 Note:Pin 14 no connection is acceptable PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable Synchronous Global Write Enable Synchronous Chip Enable Output Enable DQa-DQd MODE XQ VCC GND VCCQ ZZ Synchronous Data Input/Output Burst Sequence Mode Selection Output Drive Control +3.3V Power Supply Ground Isolated Output Buffer Supply : +3.3V or 2.5V Snooze Enable A2-A17 CLK ADSP ADSC ADV BWa -BWd BWE GW CE , CE2 OE 4 Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D PIN CONFIGURATION 100-Pin TQFP (T Version) SA SA CE CE2 BWd BWc BWb BWa CE2 VCC GND CLK GW BWE OE ADSC ADSP ADV SA SA NC DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 GND/NC VCC XQ GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE SA SA SA SA A1 A0 NC NC GND VCC NC SA SA SA SA SA SA SA SA NC DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 NC Note:Pin 14 no connection is acceptable 256K x 32 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable Synchronous Global Write Enable Synchronous Chip Enable Output Enable DQa-DQd MODE XQ VCC GND VCCQ ZZ Synchronous Data Input/Output Burst Sequence Mode Selection Output Drive Control +3.3V Power Supply Ground Isolated Output Buffer Supply : +3.3V or 2.5V Snooze Enable A2-A17 CLK ADSP ADSC ADV BWa -BWd BWE GW CE,CE2,CE2 OE Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 5 IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D PIN CONFIGURATION 119-pin PBGA (Top View) 1 A VCCQ B NC C NC D DQc1 E DQc2 F VCCQ G DQc5 H DQc7 J VCCQ K DQd1 L DQd4 M VCCQ N DQd6 P DQd8 R NC T NC U VCCQ NC NC NC NC NC VCCQ MODE SA SA SA SA A1 A0 NC NC GND VCC NC NC SA SA SA SA SA SA SA 100-Pin TQFP (D Version) 6 7 SA SA CE CE2 BWd BWc BWb BWa A17 VCC GND CLK GW BWE OE ADSC ADSP ADV SA SA 2 3 4 5 SA CE2 SA DQPc DQc3 DQc4 DQc6 DQc8 VCC DQd2 DQd3 DQd5 DQd7 DQPd SA NC SA SA SA GND GND GND BWc GND NC GND BWd GND GND GND MODE SA ADSP ADSC VCC XQ CE OE ADV GW VCC CLK NC BWE A1 A0 VCC SA SA SA SA GND GND GND BWb GND NC GND BWa GND GND GND GND/NC SA SA SA SA DQPb DQb6 DQb5 DQb4 DQb2 VCC DQa7 DQa5 DQa4 DQa3 DQPa SA NC VCCQ NC NC DQb8 DQb7 VCCQ DQb3 DQb1 VCCQ DQa8 DQa6 VCCQ DQa2 DQa1 NC ZZ DQPc DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 GND/NC VCC XQ GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPb DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 DQPa Note:Ball R5 no connection is acceptable 256K x 36 Note:Pin 14 no connection is acceptable PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable Synchronous Global Write Enable Synchronous Chip Enable Output Enable DQa-DQd MODE XQ VCC GND VCCQ ZZ DQPa-DQPd Synchronous Data Input/Output Burst Sequence Mode Selection Output Drive Control +3.3V Power Supply Ground Isolated Output Buffer Supply : +3.3V or 2.5V Snooze Enable Parity Data I/O A2-A17 CLK ADSP ADSC ADV BWa -BWd BWE GW CE , CE2 OE 6 Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D PIN CONFIGURATION 100-Pin TQFP (T Version) SA SA CE CE2 BWd BWc BWb BWa CE2 VCC GND CLK GW BWE OE ADSC ADSP ADV SA SA DQPc DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 GND/NC VCC XQ GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE SA SA SA SA A1 A0 NC NC GND VCC NC SA SA SA SA SA SA SA SA DQPb DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 DQPa Note:Pin 14 no connection is acceptable 256K x 36 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable Synchronous Global Write Enable Synchronous Chip Enable Output Enable DQa-DQd MODE XQ VCC GND VCCQ ZZ DQPa-DQPd Synchronous Data Input/Output Burst Sequence Mode Selection Output Drive Control +3.3V Power Supply Ground Isolated Output Buffer Supply : +3.3V or 2.5V Snooze Enable Parity Data I/O A2-A17 CLK ADSP ADSC ADV BWa -BWd BWE GW CE,CE2,CE2 OE Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 7 IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D PIN CONFIGURATION 119-pin PBGA (Top View) 1 A VCCQ B NC C NC D DQc1 E NC F VCCQ G NC H DQc4 J VCCQ K Nc L DQd6 M VCCQ N DQd8 P NC R NC T NC U VCCQ NC NC NC NC NC VCCQ MODE SA SA SA SA A1 A0 NC NC GND VCC NC NC SA SA SA SA SA SA SA 100-Pin TQFP (D Version) 6 7 SA SA CE CE2 NC NC BWb BWa A18 VCC GND CLK GW BWE OE ADSC ADSP ADV SA SA 2 3 4 5 SA CE2 SA DQb2 NC DQc4 DQc3 NC VCC DQd5 NC DQd7 NC DQPd SA SA SA SA SA GND GND GND BWb GND NC GND GND GND GND GND MODE SA ADSP ADSC VCC XQ CE OE ADV GW VCC CLK NC BWE A1 A0 VCC NC SA SA SA GND GND GND GND GND NC GND BWa GND GND GND GND/NC SA SA SA SA DQPa NC DQb7 NC DQb5 VCC NC DQa3 NC DQa2 NC SA SA VCCQ NC NC NC DQb8 VCCQ DQb6 NC VCCQ DQa4 NC VCCQ NC DQa1 NC ZZ NC NC NC VCCQ GND NC NC DQb1 DQb2 GND VCCQ DQb3 DQb4 GND/NC VCC XQ GND DQb5 DQb6 VCCQ GND DQb7 DQb8 DQPb NC GND VCCQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SA NC NC VCCQ GND NC DQPa DQa8 DQa7 GND VCCQ DQa6 DQa5 GND NC VCC ZZ DQa4 DQa3 VCCQ GND DQa2 DQa1 NC NC GND VCCQ NC NC NC Note:Ball R5 no connection is acceptable 512K x18 Note:Pin 14 no connection is acceptable PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable Synchronous Global Write Enable Synchronous Chip Enable Output Enable DQa-DQb MODE XQ VCC GND VCCQ ZZ DQPa-DQPb Synchronous Data Input/Output Burst Sequence Mode Selection Output Drive Control +3.3V Power Supply Ground Isolated Output Buffer Supply : +3.3V or 2.5V Snooze Enable Parity Data I/O DQPa is parity for DQa1-8;DQPb is parity for DQb1-8 A2-A18 CLK ADSP ADSC ADV BWa -BWb BWE GW CE , CE2 OE 8 Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D PIN CONFIGURATION 100-Pin TQFP (T Version) SA SA CE CE2 NC NC BWb BWa CE2 VCC GND CLK GW BWE OE ADSC ADSP ADV SA SA NC NC NC VCCQ GND NC NC DQb1 DQb2 GND VCCQ DQb3 DQb4 GND/NC VCC XQ GND DQb5 DQb6 VCCQ GND DQb7 DQb8 DQPb NC GND VCCQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE SA SA SA SA A1 A0 NC NC GND VCC NC SA SA SA SA SA SA SA SA SA NC NC VCCQ GND NC DQPa DQa8 DQa7 GND VCCQ DQa6 DQa5 GND NC VCC ZZ DQa4 DQa3 VCCQ GND DQa2 DQa1 NC NC GND VCCQ NC NC NC Note:Pin 14 no connection is acceptable 512K x18 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable Synchronous Global Write Enable Synchronous Chip Enable Output Enable DQa-DQb MODE XQ VCC GND VCCQ ZZ DQPa-DQPb Synchronous Data Input/Output Burst Sequence Mode Selection Output Drive Control +3.3V Power Supply Ground Isolated Output Buffer Supply : +3.3V or 2.5V Snooze Enable Parity Data I/O DQPa is parity for DQa1-8;DQPb is parity for DQb1-8 A2-A18 CLK ADSP ADSC ADV BWa -BWb BWE GW CE,CE2,CE2 OE Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 9 IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D Mode Pin Functions Mode Name Burst Order Control Power Down Control Output Drive Control Pin Name MODE ZZ XQ State L H or NC L or NC H L H Function Linear Burst Interleaved Burst Active Standby High Drive (Low Impedance) Low Drive (High Impedance) Note: There are pull-up devices on the MODE, XQ, SCD, and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above table. TRUTH TABLE Operation Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None None None External External External Next Next Next Next Next Next Current Current Current Current Current Current CE H L L L L L L L X X H H X H X X H H X H CE2 X X L X L H H H X X X X X X X X X X X X CE2 X H X H X L L L X X X X X X X X X X X X ADSP X L L H H L H H H H X X H X H H X X H X ADSC L X X L L X L L H H H H H H H H H H H H ADV X X X X X X X X L L L L L L H H H H H H WRITE X X X X X X Read Write Read Read Read Read Write Write Read Read Read Read Write Write OE X X X X X X X X L H L H X X L H L H X X DQ High-Z High-Z High-Z High-Z High-Z Q Q D Q High-Z Q High-Z D D Q High-Z Q High-Z D D PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes 10 GW H H H H L BWb BWE BWa BWb BWc BWd H X X X X L H H H H L L H H H L L L L L X X X X X Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect) External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = GND) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS Symbol TBIAS TSTG PD IOUT VIN, VOUT VIN VCC (1) Parameter Temperature Under Bias Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs Voltage on Vcc Supply Relatiive to GND Value –40 to +85 –55 to +150 1.6 100 –0.5 to VCCQ + 0.5 –0.5 to VCC + 0.5 –0.5 to 4.6 Unit °C °C W mA V V V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 11 IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C V CC 3.3V, +10%, –5% 3.3V, +10%, –5% VCCQ 2.375–3.6V 2.375–3.6V DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Output HIGH Voltage VOH VOL VIH VIL ILI ILO Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Test Conditions IOH = –2.0 mA, VCCQ = 2.5V IOH = –4.0 mA, VCCQ = 3.3V IOL = 2.0 mA, VCCQ = 2.5V IOL = 8.0 mA, VCCQ = 3.3V VCCQ = 2.5V VCCQ = 3.3V VCCQ = 2.5V VCCQ = 3.3V GND ≤ VIN ≤ VCC (1) GND ≤ VOUT ≤ VCCQ, OE = VIH Min. Max. 1.7 — 2.4 — — 0.7 — 0.4 1.7 VCCQ+ 0.3 2.0 VCCQ + 0.3 –0.3 0.7 –0.3 0.8 –2 2 –2 2 Unit V V V V V V V V µA µA Notes: 1. The MODE, ZZ, XQ, pin14 pin has an internal pullup. and input leakage = ±10 µA . POWER SUPPLY CHARACTERISTICS (Over Operating Range) Parameter AC Operating Supply Current Test Conditions Symbol Device Selected, ICC1 All Inputs ≤ VIL or ≥VIH OE = VIH, VCC = Max f = 1/tKC Clock Running Device Deselected, ICC2 VCC = Max., All Inputs ≤ VIL or ≥VIH f = 1/tKC COMS Standby Device Deselected, ISB VCC = Max., All Inputs ≤ 0.2V or ≥VCC -0.2V; f = 0 Power Down Mode VCC = Max Izz ZZ ≥VCC - 0.2V f = 0, All input ≤ 0.2V or ≥VCC - 0.2V -6.5 Max. 300 320 -7.5 Max. 290 310 -8.5 Max. 280 300 -9.5 Max. 370 290 Unit mA mA Com. Ind. Com. Ind. 110 120 100 110 90 100 90 100 mA mA Com. Ind. 90 100 90 100 90 100 90 100 mA mA Com. Ind. 80 90 80 90 80 90 80 90 mA mA 12 Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D CAPACITANCE (1,2) Symbol CIN COUT Parameter Conditions Input Capacitance Input/Output Capacitance Max. VIN = 0V VOUT = 0V Unit 6 8 pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V for 3.3V I/O VCCQ/2V for 2.5V I/O See Figures 1 and 2 AC TEST LOADS ZO = 50Ω 3.3V for 3.3V I/O /2.5V for 2.5v I/O 317Ω /1667Ω Output Buffer 50Ω OUTPUT 5 pF Including jig and scope 351Ω /1538Ω 1.5V for 3,3V I/O VCCQ/2V for 2.5V I/O Figure 1 Figure 2 Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 13 IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D READ/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol tKC tKQ tKQX(1) tKQLZ(1,2) tKH tKL tKQHZ(1,2) tOEQ tOELZ(1,2) tOEHZ(1,2) tAS tSS tWS tCES tAVS tDS tDH tAH tSH tWH tCEH tAVH tZZS tZZREC Parameter Cycle Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High Pulse Width Clock Low Pulse Width Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Enable to Output High-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Advance Setup Time Data Setup time Data Hold time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time ZZ Setup Time ZZ Recovery Time -6.5 Min. Max. 7.5 — — 6.5 2.5 — 0 — 1.6 — 1.6 — — 3.1 — 3.1 0 — — 3.0 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 0.5 0.5 0.5 0.5 0.5 2 2 — — — — — — — (Over Operating Range) -7.5 -8.5 -9.5 Min. Max. Min. Max. Min. Max. Unit 8.5 — 10 — 11 — ns — 7.5 — 8.5 — 9.5 ns 2.5 — 3.0 — 3.0 — ns 0 — 0 — 0 — ns 2 — 2.3 — 2.8 — ns 2 — 2.3 — 2.8 — ns — 3.1 — 3.5 — 4 ns — 3.1 — 3.5 — 4 ns 0 — 0 — 0 — ns — 3.0 — 3.5 — 4 ns 1.5 — 1.5 — 1.5 — ns 1.5 — 1.5 — 1.5 — ns 1.5 — 1.5 — 1.5 — ns 1.5 — 1.5 — 1.5 — ns 1.5 — 1.5 — 1.5 — ns 1.5 — 1.5 — 1.5 — ns 0.5 — 0.5 — 0.5 — ns 0.5 — 0.5 — 0.5 — ns 0.5 — 0.5 — 0.5 — ns 0.5 — 0.5 — 0.5 — ns 0.5 — 0.5 — 0.5 — ns 0.5 — 0.5 — 0.5 — ns 2 — 2 — 2 — cyc 2 — 2 — 2 — cyc Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 14 Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D READ/WRITE CYCLE TIMING: FLOW THROUGH tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS tSH ADSC ADV tAS tAH Addresses RD1 tWS tWH WR1 RD2 RD3 GW tWS tWH BWE tWS tWH BW4-BW1 tCES tCEH WR1 CE Masks ADSP CE tCES tCEH CE2 and CE2 only sampled with ADSP or ADSC CE2 tCES tCEH Unselected with CE2 CE2 tOEQ tOEHZ OE tOELZ tOEQX tKQX DATAOUT High-Z tKQLZ tKQ 1a tKQX tKQHZ 2a 2b 2c 2d tKQHZ DATAIN High-Z tDS 1a tDH Single Read Single Write Burst Read Unselected Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 15 IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D SNOOZE AND RECOVERY CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP ADSC ADV tAS tAH Address RD1 RD2 GW BWE BW4-BW1 tCES tCEH CE tCES tCEH CE2 tCES tCEH CE2 tOEQ tOEHZ OE tOELZ tOEQX DATAOUT High-Z tKQLZ tKQ 1a tKQX tKQHZ tZZS tZZREC DATAIN ZZ High-Z Single Read Snooze with Data Retention Read 16 Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed -6.5 Order Part Number IC61SF25632T-6.5TQ IC61SF25632D-6.5TQ IC61SF25632D-6.5B IC61SF25632T-7.5TQ IC61SF25632D-7.5TQ IC61SF25632D-7.5B IC61SF25632T-8.5TQ IC61SF25632D-8.5TQ IC61SF25632D-8.5B IC61SF25632T-9.5TQ IC61SF25632D-9.5TQ IC61SF25632D-9.5B Package 14*20*1.4mm LQFP 14*20*1.4mm LQFP 14*22mm PBGA 14*20*1.4mm LQFP 14*20*1.4mm LQFP 14*22mm PBGA 14*20*1.4mm TQFP 14*20*1.4mm TQFP 14*22mm PBGA 14*20*1.4mm TQFP 14*20*1.4mm TQFP 14*22mm PBGA -7.5 -8.5 -9.5 Speed -6.5 -7.5 -8.5 -9.5 Order Part Number IC61SF25636T-6.5TQ IC61SF25636D-6.5Q IC61SF25636D-6.5B IC61SF25636T-7.5TQ IC61SF25636D-7.5TQ IC61SF25636D-7.5B IC61SF25636T-8.5TQ IC61SF25636D-8.5TQ IC61SF25636D-8.5B IC61SF25636T-9.5TQ IC61SF25636D-9.5TQ IC61SF25636D-9.5B Package 14*20*1.4mm LQFP 14*20*1.4mm LQFP 14*22mm PBGA 14*20*1.4mm LQFP 14*20*1.4mm LQFP 14*22mm PBGA 14*20*1.4mm TQFP 14*20*1.4mm TQFP 14*22mm PBGA 14*20*1.4mm TQFP 14*20*1.4mm TQFP 14*22mm PBGA Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 17 IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D Speed -6.5 Order Part Number IC61SF51218T-6.5TQ IC61SF51218D-6.5TQ IC61SF51218D-6.5B IC61SF51218T-7.5TQ IC61SF51218D-7.5TQ IC61SF51218D-7.5B IC61SF51218T-8.5TQ IC61SF51218D-8.5TQ IC61SF51218D-8.5B IC61SF51218T-9.5TQ IC61SF51218D-9.5TQ IC61SF51218D-9.5B Package 14*20*1.4mm LQFP 14*20*1.4mm LQFP 14*22mm PBGA 14*20*1.4mm LQFP 14*20*1.4mm LQFP 14*22mm PBGA 14*20*1.4mm TQFP 14*20*1.4mm TQFP 14*22mm PBGA 14*20*1.4mm TQFP 14*20*1.4mm TQFP 14*22mm PBGA -7.5 -8.5 -9.5 Industrial Range: -40°C to 85°C Speed -6.5 Order Part Number IC61SF25632T-6.5TQI IC61SF25632D-6.5TQI IC61SF25632D-6.5BI IC61SF25632T-7.5TQI IC61SF25632D-7.5TQI IC61SF25632D-7.5BI IC61SF25632T-8.5TQI IC61SF25632D-8.5TQI IC61SF25632D-8.5BI IC61SF25632T-9.5TQI IC61SF25632D-9.5TQI IC61SF25632D-9.5BI Package 14*20*1.4mm LQFP 14*20*1.4mm LQFP 14*22mm PBGA 14*20*1.4mm LQFP 14*20*1.4mm LQFP 14*22mm PBGA 14*20*1.4mm TQFP 14*20*1.4mm TQFP 14*22mm PBGA 14*20*1.4mm TQFP 14*20*1.4mm TQFP 14*22mm PBGA -7.5 -8.5 -9.5 18 Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D Speed -6.5 -7.5 -8.5 -9.5 Order Part Number IC61SF25636T-6.5TQI IC61SF25636D-6.5QI IC61SF25636D-6.5BI IC61SF25636T-7.5TQI IC61SF25636D-7.5TQI IC61SF25636D-7.5BI IC61SF25636T-8.5TQI IC61SF25636D-8.5TQI IC61SF25636D-8.5BI IC61SF25636T-9.5TQI IC61SF25636D-9.5TQI IC61SF25636D-9.5BI Package 14*20*1.4mm LQFP 14*20*1.4mm LQFP 14*22mm PBGA 14*20*1.4mm LQFP 14*20*1.4mm LQFP 14*22mm PBGA 14*20*1.4mm TQFP 14*20*1.4mm TQFP 14*22mm PBGA 14*20*1.4mm TQFP 14*20*1.4mm TQFP 14*22mm PBGA Speed -6.5 -7.5 -8.5 -9.5 Order Part Number IC61SF51218T-6.5TQI IC61SF51218D-6.5TQI IC61SF51218D-6.5BI IC61SF51218T-7.5TQI IC61SF51218D-7.5TQI IC61SF51218D-7.5BI IC61SF51218T-8.5TQI IC61SF51218D-8.5TQI IC61SF51218D-8.5BI IC61SF51218T-9.5TQI IC61SF51218D-9.5TQI IC61SF51218D-9.5BI Package 14*20*1.4mm LQFP 14*20*1.4mm LQFP 14*22mm PBGA 14*20*1.4mm LQFP 14*20*1.4mm LQFP 14*22mm PBGA 14*20*1.4mm TQFP 14*20*1.4mm TQFP 14*22mm PBGA 14*20*1.4mm TQFP 14*20*1.4mm TQFP 14*22mm PBGA Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 19