IC61SF6432-10PQ

I C61SF6432 Document Title 64K x 32 Flow Through Sync. SRAM Revision History Revision No 0A History Initial Draft Draft Date Remark September 13,2001 The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. SSR017-0A 09/13/2001 1 I C61SF6432 64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • • • • • • • • • • • • Fast access time: 9 ns, 10 ns Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Pentium™ or linear burst sequence control using MODE input Three chip enables for simple depth expansion and address pipelining Common data inputs and data outputs Power-down control by ZZ input JEDEC 100-Pin LQFP and PQFP package Single +3.3V power supply Two Clock enables and one Clock disable to eliminate multiple bank bus contention. Control pins mode upon power-up: – FT in pipeline mode – MODE in interleave burst mode – ZZ in normal operation mode These control pins can be connected to GNDQ or VCCQ to alter their power-up state Industrial temperature available DESCRIPTION The ICSI IC61SF6432 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium™, 680X0™, and PowerPC™ microprocessors. It is organized as 65,536 words by 32 bits, fabricated with ICSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3 controls DQ17-DQ24, BW4 controls DQ25-DQ32, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IC61SF6432 and controlled by the ADV (burst address advance) input pin. Asynchronous signals include output enable (OE), sleep mode input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH input on the ZZ pin puts the SRAM in the power-down state. When ZZ is pulled LOW (or no connect), the SRAM normally operates after three cycles of the wake-up period. A LOW input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ (or no connect) on MODE pin selects INTERLEAVED Burst. • ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. SSR017-0A 09/13/2001 I C61SF6432 BLOCK DIAGRAM MODE Q0 A0’ CLK CLK A0 BINARY COUNTER ADV ADSC ADSP CE CLR Q1 A1’ A1 64K x 32 MEMORY ARRAY 14 16 A15-A0 16 D Q ADDRESS REGISTER CE CLK 32 32 GW BWE BW4 D Q DQ32-DQ25 BYTE WRITE REGISTERS CLK D BW3 Q DQ24-DQ17 BYTE WRITE REGISTERS CLK D BW2 Q DQ16-DQ9 BYTE WRITE REGISTERS CLK D BW1 Q DQ8-DQ1 BYTE WRITE REGISTERS CLK CE1 CE2 CE3 D Q 4 ENABLE REGISTER CE CLK INPUT REGISTERS CLK OE 32 DATA[32:1] D Q ENABLE DELAY REGISTER CLK OE Integrated Circuit Solution Inc. SSR017-0A 09/13/2001 3 I C61SF6432 PIN CONFIGURATION 100-Pin LQFP and PQFP (Top View) A6 A7 CE1 CE2 BW4 BW3 BW2 BW1 CE3 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9 NC DQ17 DQ18 VCCQ GNDQ DQ19 DQ20 DQ21 DQ22 GNDQ VCCQ DQ23 DQ24 GNDQ VCC NC GND DQ25 DQ26 VCCQ GNDQ DQ27 DQ28 DQ29 DQ30 GNDQ VCCQ DQ31 DQ32 NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 NC NC DQ16 DQ15 VCCQ GNDQ DQ14 DQ13 DQ12 DQ11 GNDQ VCCQ DQ10 DQ9 GND NC VCC ZZ DQ8 DQ7 VCCQ GNDQ DQ6 DQ5 DQ4 DQ3 GNDQ VCCQ DQ2 DQ1 NC PIN DESCRIPTIONS A0-A15 CLK ADSP ADSC ADV BW1-BW4 BWE GW CE1, CE2, CE3 OE Address Inputs Clock Processor Address Status Controller Address Status Burst Address Advance Synchronous Byte Write Enable Byte Write Enable Global Write Enable Synchronous Chip Enable Output Enable GNDQ NC DQ1-DQ32 ZZ MODE VCC GND VCCQ Data Input/Output Sleep Mode Burst Sequence Mode +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V Isolated Output Buffer Ground No Connect 4 Integrated Circuit Solution Inc. SSR017-0A 09/13/2001 I C61SF6432 TRUTH TABLE OPERATION Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst ADDRESS USED None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE1 H L L L L L L L L L X X H H X H X X H H X H CE2 X L X L X H H H H H X X X X X X X X X X X X CE3 X X H X H L L L L L X X X X X X X X X X X X ADSP ADSC X L L H H L L H H H H H X X H X H H X X H X L X X L L X X L L L H H H H H H H H H H H H ADV WRITE X X X X X X X X X X L L L L L L H H H H H H X X X X X X X L H H H H H H L L H H H H L L OE X X X X X L H X L H L H L H X X L H L H X X DQ High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D Notes: 1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK). 2. Wait states are inserted by suspending burst. 3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is LOW. WRITE=H means all byte write enable signals are HIGH. 4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH throughout the input data hold time. 5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock. PARTIAL TRUTH TABLE FUNCTION READ READ WRITE Byte 1 WRITE All Bytes WRITE All Bytes GW H H H X L BWE H X L L X BW1 X H L L X BW2 X H H L X BW3 BW4 X H H L X X H H L X Integrated Circuit Solution Inc. SSR017-0A 09/13/2001 5 I C61SF6432 INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect) External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = GNDQ) 0,0 A1’, A0’ = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol TBIAS TSTG PD IOUT VIN, VOUT VIN Parameter Temperature Under Bias Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs Value –10 to +85 –55 to +150 1.8 100 –0.5 to VCCQ + 0.3 –0.5 to 5.5 Unit °C °C W mA V V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. 6 Integrated Circuit Solution Inc. SSR017-0A 09/13/2001 I C61SF6432 OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V +10%, –5% 3.3V +10%, –5% DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current GND ≤ VIN ≤ VCCQ(2) GND ≤ VOUT ≤ VCCQ, OE = VIH Com. Ind. Com. Ind. Test Conditions IOH = –5.0 mA IOL = 5.0 mA Min. 2.4 — 2.0 –0.3 –5 –10 –5 –10 Max. — 0.4 VCCQ + 0.3 0.8 5 10 5 10 Unit V V V V µA µA POWER SUPPLY CHARACTERISTICS (Over Operating Range) Symbol Parameter ICC AC Operating Supply Current Standby Current Test Conditions Device Selected, Com. All Inputs = VIL or VIH Ind. OE = VIH, Cycle Time ≥ tKC min. Device Deselected, Com. VCC = Max., Ind. All Inputs = VIH or VIL CLK Cycle Time ≥ tKC min. ZZ = VCCQ, Com. CLK Running Ind. All Inputs ≤ GND + 0.2V or ≥ VCC – 0.2V -9 Min. Typ. Max. — — — — 300 — 60 — — — — — -10 Min. Typ. Max. — — — — 290 300 60 70 — — — — Unit mA ISB mA IZZ Power-Down Mode Current — — 10 — — — — — 10 20 — — mA Note: 1. MODE pin has an internal pull-up. ZZ pin has an internal pull-down. These pins may be a No Connect, tied to GND, or tied to VCCQ. 2. MODE pin should be tied to Vcc or GND. They exhibit ±30 µA maximum leakage current when tied to ≤ GND + 0.2V or ≥ Vcc – 0.2V. Integrated Circuit Solution Inc. SSR017-0A 09/13/2001 7 I C61SF6432 CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 AC TEST LOADS 3.3V 317 Ω ZO = 50Ω OUTPUT Output Buffer 30 pF 50Ω 5 pF Including jig and scope 351 Ω 1.5V Figure 1 Figure 2 8 Integrated Circuit Solution Inc. SSR017-0A 09/13/2001 I C61SF6432 READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC tKH tKL tKQ tKQX (2) (2,3) Parameter Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Configuration Setup (1) -9 Min. Max. -10 Min. Max. 15 6 6 — 2 0 2 2.5 2.5 2.5 2.5 2.5 1 0.5 0.5 0.5 0.5 80 — — — 10 — — 6 — — — — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 6 6 — 2 0 2 2.5 2.5 2.5 2.5 2.5 1 0.5 0.5 0.5 0.5 66.7 — — — 9 — — 6 — — — — — — — — — — — tKQLZ tAS tSS tWS tCES tAVS tAH tSH tWH tCEH tAVH tCFG tKQHZ(2,3) Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. Integrated Circuit Solution Inc. SSR017-0A 09/13/2001 9 I C61SF6432 READ CYCLE TIMING: FLOW-THROUGH tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS tSH ADSC initiate read ADSC tAVS tAVH Suspend Burst ADV tAS tAH A15-A0 RD1 tWS tWH RD2 RD3 GW tWS tWH BWE BW4-BW1 tCES tCEH CE Masks ADSP CE tCES tCEH CE2 and CE2 only sampled with ADSP or ADSC Unselected with CE2 CE2 tCES tCEH CE2 OE tKQX DATAOUT High-Z tKQLZ tKQ 1a 2a 2b 2c 2d 3a tKQHZ DATAIN High-Z Single Read Flow-through Burst Read Unselected 10 Integrated Circuit Solution Inc. SSR017-0A 09/13/2001 I C61SF6432 WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC tKH tKL tAS tSS tWS tDS tCES tAVS tAH tSH tDH tWH tCEH tAVH tCFG Parameter Cycle Time Clock High Time Clock Low Time Address Setup Time Address Status Setup Time Write Setup Time Data In Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Configuration Setup(1) -9 Min. Max. 13 6 6 2.5 2.5 2.5 2.5 2.5 2.5 1 0.5 0.5 0.5 0.5 0.5 52 — — — — — — — — — — — — — — — — -10 Min. Max. 15 6 6 2.5 2.5 2.5 2.5 2.5 2.5 1 0.5 0.5 0.5 0.5 0.5 60 — — — — — — — — — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Configuration signal MODE is static and must not change during normal operation. Integrated Circuit Solution Inc. SSR017-0A 09/13/2001 11 I C61SF6432 WRITE CYCLE TIMING: PIPELINE tKC CLK tSS tSH tKH tKL ADSP is blocked by CE1 inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS ADV tAS tAH tAVH A15-A0 WR1 tWS tWH WR2 WR3 GW tWS tWH BWE tWS tWH tWS tWH BW4-BW1 tCES tCEH WR1 WR2 CE1 Masks ADSP WR3 CE1 tCES tCEH CE2 and CE3 only sampled with ADSP or ADSC Unselected with CE2 CE2 tCES tCEH CE3 OE DATAOUT High-Z tDS tDH DATAIN High-Z 1a BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d 3a Single Write Burst Write Write Unselected 12 Integrated Circuit Solution Inc. SSR017-0A 09/13/2001 I C61SF6432 READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC tKH tKL tKQ tKQX (2) (2,3) Parameter Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Disable to Output Invalid Output Disable to Output High-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time -9 Min. Max. 13 6 6 — 2 0 2 0 — 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 — — — 9 — — 6 — 6 — — — — — — — — -10 Min. Max. 15 6 6 — 2 0 2 0 — 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 — — — 10 — — 6 — 6 — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tKQLZ tKQHZ(2,3) tOEQX(2) tOEHZ tAS tSS tWS tCES tAH tSH tWH tCEH (2,3) Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. Integrated Circuit Solution Inc. SSR017-0A 09/13/2001 13 I C61SF6432 READ/WRITE CYCLE TIMING: FLOW-THROUGH tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS tSH ADSC ADV tAS tAH A15-A0 RD1 tWS tWH WR1 RD2 RD3 GW tWS tWH BWE tWS tWH BW4-BW1 tCES tCEH WR1 CE Masks ADSP CE tCES tCEH CE2 and CE2 only sampled with ADSP or ADSC CE2 tCES tCEH Unselected with CE2 CE2 tOEHZ OE tOEQX tKQX DATAOUT High-Z tKQLZ tKQ 1a tKQX tKQHZ 2a 2b 2c 2d tKQHZ DATAIN High-Z tDS 1a tDH Single Read Flow-through Single Write Burst Read Unselected 14 Integrated Circuit Solution Inc. SSR017-0A 09/13/2001 I C61SF6432 SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC tKH tKL tKQ tKQX (4) (4,5) Parameter Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Chip Enable Setup Time Address Hold Time Address Status Hold Time Chip Enable Hold Time ZZ Standby (1) -9 Min. Max. 13 6 6 — 2 0 2 — 0 0 — 2.5 2.5 2.5 0.5 0.5 0.5 2 2 52 — — — 9 — — 6 6 — — 6 — — — — — — — — — -10 Min. Max. 15 6 6 — 2 0 2 — 0 0 — 2.5 2.5 2.5 0.5 0.5 0.5 2 2 60 — — — 10 — — 6 6 — — 6 — — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc ns tKQLZ tOEQ tKQHZ(4,5) tOEQX tOELZ tAS tSS tCES tAH tSH tCEH tZZS tZZREC tCFG (4) (4,5) tOEHZ(4,5) ZZ Recovery(2) Configuration Setup(3) Notes: 1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data retention is guaranteed when ZZ is asserted and clock remains active. 2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state. 3. Configuration signal MODE is static and must not change during normal operation. 4. Guaranteed but not 100% tested. This parameter is periodically sampled. 5. Tested with load in Figure 2. Integrated Circuit Solution Inc. SSR017-0A 09/13/2001 15 I C61SF6432 SNOOZE AND RECOVERY CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP ADSC ADV tAS tAH A15-A0 RD1 RD2 GW BWE BW4-BW1 tCES tCEH CE1 tCES tCEH CE2 tCES tCEH CE3 tOEQ tOEHZ OE tOELZ tOEQX DATAOUT High-Z tKQLZ tKQ 1a tKQX tKQHZ DATAIN High-Z tZZS tZZREC ZZ Single Read Snooze with Data Retention Read 16 Integrated Circuit Solution Inc. SSR017-0A 09/13/2001 I C61SF6432 ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 9 9 10 10 Order Part Number IC61SF6432-9TQ IC61SF6432-9PQ IC61SF6432-10TQ IC61SF6432-10PQ Package 14*20*1.4mm LQFP 14*20*2.7mm PQFP 14*20*1.4mm LQFP 14*20*2.7mm PQFP ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) 10 10 Order Part Number IC61SF6432-10TQI IC61SF6432-10PQI Package 14*20*1.4mm LQFP 14*20*2.7mm PQFP Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw Integrated Circuit Solution Inc. SSR017-0A 09/13/2001 17