IC62C1024

1+$ + " 1+$ + " .EATURES 128K x 8 HIGH-SPEED CMOS STATIC RAM • High-speed access time: 35, 45, 55, 70 ns • Low active power: 450 mW (typical) • Low standby power: 500 µW (typical) CMOS standby • Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications • .ully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single 5V (±10%) power supply DESCRIPTION The 1+51 IC62C1024 is a low power,131,072-word by 8-bit CMOS static RAM. It is fabricated using 1 +51 's highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IC62C1024 is available in 32-pin 600mil DIP, 450mil SOP and 8*20mm TSOP-1 packages. .UNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 512 x 2048 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE1 CE2 OE WE CONTROL CIRCUIT ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. ALSR005-0A 1 1+$ + " PIN CON.IGURATION 32-Pin SOP and DIP NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 PIN CON.IGURATION 32-Pin 8x20mm TSOP-1 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 PIN DESCRIPTIONS A0-A16 CE1 CE2 OE WE I/O0-I/O7 Vcc GND Address Inputs Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Write Enable Input Input/Output Power Ground OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 5V ± 10% 5V ± 10% TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X X H H L CE1 H X L L L CE2 X L H H H OE X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN Vcc Current ISB, ISB ISB, ISB ICC ICC ICC 2 Integrated Circuit Solution Inc. ALSR005-0A 1+$ + " ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +7.0 –10 to +85 –65 to +150 1.5 20 Unit V °C °C W mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit p. p. Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions VCC = Min., IOH = –1.0 mA VCC = Min., IOL = 2.1 mA Min. 2.4 — 2.2 –0.3 –5 –10 –5 –10 Max. — 0.4 VCC + 0.5 0.8 5 10 5 10 Unit V V V V µA µA GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC Com. Ind. Com. Ind. Notes: 1. VIL = –3.0V for pulse width less than 10 ns. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC ISB Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., CE = VIL IOUT = 0 mA, f = fMAX Com. Ind. -35 ns Min. Max. — — — — — — 150 160 40 60 30 40 -45 ns Min. Max. — — — — — — 135 145 40 60 30 40 -55 ns Min. Max. — — — — — — 120 130 40 60 30 40 -70 ns Min. Max. — — — — — — 90 100 40 60 30 40 Unit mA mA VCC = Max., Com. VIN = VIH or VIL, CE1 ≥ VIH, Ind. or CE2 ≤ VIL, f = 0 VCC = Max., Com. CE1 ≥ VCC – 0.2V, Ind. CE2 ≤ 0.2V, VIN > VCC – 0.2V, or VIN ≤ 0.2V, f = 0 ISB mA Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Integrated Circuit Solution Inc. ALSR005-0A 3 1+$ + " READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE1 Access Time CE2 Access Time OE Access Time Min. 35 — 3 — — — 0 0 3 3 0 -35 Max. — 35 — 35 35 10 — 10 — — 10 -45 Min. Max. 45 — 3 — — — 0 0 5 5 0 — 45 — 45 45 20 — 15 — — 15 Min. 55 — 3 — — — 0 0 7 7 0 -55 Max. — 55 — 55 55 25 — 20 — — 20 Min. 70 — 3 — — — 0 0 10 10 0 -70 Max. — 70 — 70 70 35 — 25 — — 25 Unit ns ns ns ns ns ns ns ns ns ns ns tRC tAA tOHA tACE tACE tDOE tLZOE  OE to Low-Z Output tHZOE  OE to High-Z Output tLZCE tLZCE   CE1 to Low-Z Output CE2 to Low-Z Output tHZCE  CE1 or CE2 to High-Z Output Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in .igure 1a. 2. Tested with the load in .igure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and .all Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 5 ns 1.5V See .igures 1a and 1b AC TEST LOADS 480 Ω 5V 5V 480 Ω OUTPUT 100 pF Including jig and scope 255 Ω OUTPUT 5 pF Including jig and scope 255 Ω .igure 1a. 4 .igure 1b. Integrated Circuit Solution Inc. ALSR005-0A 1+$ + " AC WAVE.ORMS READ CYCLE NO. 1(1,2) t RC ADDRESS t AA t OHA DOUT PREVIOUS DATA VALID t OHA DATA VALID READ CYCLE NO. 2(1,3) t RC ADDRESS t AA OE t OHA t DOE CE t HZOE t LZOE t ACE t LZCE t HZCE DATA VALID DOUT HIGH-Z Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. Integrated Circuit Solution Inc. ALSR005-0A 5 1+$ + " WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power) Symbol Parameter Write Cycle Time CE1 to Write End CE2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time " Min. 35 25 25 25 0 0 25 20 0 — 3 -35 Max. — — — — — — — — — 10 — Min. 45 35 35 35 0 0 35 25 0 — 5 -45 Max. — — — — — — — — — 15 — Min. 55 50 50 45 0 0 40 25 0 — 5 -55 Max. — — — — — — — — — 20 — Min. 70 60 60 60 0 0 50 30 0 — 5 -70 Max. — — — — — — — — — 25 — Unit ns ns ns ns ns ns ns ns ns ns ns tWC tSCE tSCE tAW tHA tSA tPWE tSD tHD tLZWE  WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low-Z Output tHZWE  WE LOW to High-Z Output Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in .igure 1a. 2. Tested with the load in .igure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. AC WAVE.ORMS WRITE CYCLE NO. 1 (9- Controlled)(1,2) t WC ADDRESS VALID ADDRESS t SA CE t SCE t HA WE t AW t PWE1 t PWE2 t HZWE t LZWE HIGH-Z DOUT DATA UNDEFINED t SD DIN t HD DATAIN VALID 6 Integrated Circuit Solution Inc. ALSR005-0A 1+$ + " WRITE CYCLE NO. 2 (+-, CE2 Controlled)(1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA DOUT DATA UNDEFINED t HZWE HIGH-Z t LZWE t SD DIN t HD DATAIN VALID Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE = VIH. Integrated Circuit Solution Inc. ALSR005-0A 7 1+$ + " ORDERING IN.ORMATION Commercial Range: 0°C to +70°C Speed (ns) 35 35 35 45 45 45 55 55 55 70 70 70 Order Part No. IC62C1024-35W IC62C1024-35Q IC62C1024-35T IC62C1024-45W IC62C1024-45Q IC62C1024-45T IC62C1024-55W IC62C1024-55Q IC62C1024-55T IC62C1024-70W IC62C1024-70Q IC62C1024-70T Package 600mil DIP 450mil SOP 8*20mm TSOP-1 600mil DIP 450mil SOP 8*20mm TSOP-1 600mil DIP 450mil SOP 8*20mm TSOP-1 6600mil DIP 450mil SOP 8*20mm TSOP-1 ORDERING IN.ORMATION Industrial Range: –40°C to +85°C Speed (ns) 35 35 35 45 45 45 55 55 55 70 70 70 Order Part No. IC62C1024-35WI IC62C1024-35QI IC62C1024-35TI IC62C1024-45WI IC62C1024-45QI IC62C1024-45TI IC62C1024-55WI IC62C1024-55QI IC62C1024-55TI IC62C1024-70WI IC62C1024-70QI IC62C1024-70TI Package 600mil DIP 450mil SOP 8*20mm TSOP-1 600mil DIP 450mil SOP 8*20mm TSOP-1 600mil DIP 450mil SOP 8*20mm TSOP-1 600mil DIP 450mil SOP 8*20mm TSOP-1 HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 .ax: 886-3-5783000 Integrated Circuit Solution Inc. BRANCH O..ICE: 7., NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 .AX: 886-2-26962252 http://www.icsi.com.tw 8 Integrated Circuit Solution Inc. ALSR005-0A