IC62C256-70UI

1+$ + #$ .EATURES 32K x 8 LOW POWER CMOS STATIC RAM • Access time: 45, 70 ns • Low active power: 200 mW (typical) • Low standby power — 250 µW (typical) CMOS standby — 28 mW (typical) TTL standby • .ully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single 5V power supply DESCRIPTION The 1+51 IC62C256 is a low power, 32,768 word by 8-bit CMOS static RAM. It is fabricated using 1 +51 's highperformance, low power CMOS technology. When CS is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 µW (typical) at CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Select (CS) input and an active LOW Output Enable (OE) input. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IC62C256 is pin compatible with other 32K x 8 SRAMs in 330mil SOP or 8*13.4mm TSOP-1 package. .UNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32K X 8 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CS OE WE CONTROL CIRCUIT ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001 1 1+$ + #$ PIN CON.IGURATION 28-Pin SOP A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 PIN CON.IGURATION 8x13.4mm TSOP-1 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 PIN DESCRIPTIONS A0-A14 CS OE WE I/O0-I/O7 Vcc GND Address Inputs Chip Select Input Output Enable Input Write Enable Input Input/Output Power Ground TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X H H L CS H L L L OE X H L X I/O Operation High-Z High-Z DOUT DIN Vcc Current ISB, ISB ICC, ICC ICC, ICC ICC, ICC ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +7.0 –55 to +125 –65 to +150 Unit V °C °C W mA 0.5 20 Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001 1+$ + #$ OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 5V ± 10% 5V ± 10% DC ELECTRICAL CHARACTERISTICS Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage  Input Leakage Output Leakage Test Conditions VCC = Min., IOH = –1.0 mA VCC = Min., IOL = 2.1 mA Min. 2.4 — 2.2 –0.3 –2 –10 –2 –10 Max. — 0.4 VCC + 0.5 0.8 2 10 2 10 Unit V V V V µA µA GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC, Outputs Disabled Com. Ind. Com. Ind. Note: 1. VIH=VCC +3.0V for pulse width less than 10ns. 2. VIL = –3.0V for pulse width less than 10 ns. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC ICC ISB Parameter Vcc Operating Supply Current Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., CS = VIL IOUT = 0 mA, f = 0 VCC = Max., CS = VIL IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL CS ≥ VIH, f = 0 VCC = Max., CS ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V, f = 0 -45 ns Min. Max. — 60 — 70 — 70 — 80 — 5 — 10 — — 0.5 1.0 -70 ns Min. Max. — 60 — 70 — 65 — 75 — 5 — 10 — — 0.5 1.0 Unit mA mA mA Com. Ind. Com. Ind. Com. Ind. Com. Ind. ISB mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 10 Unit p. p. Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V. Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001 3 1+$ + #$ READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CS Access Time OE Access Time  Min. 45 — 2 — — 0 0 3 0 0 — -45 ns Max. — 45 — 45 25 — 20 — 20 — 30 -70 ns Min. Max. 70 — 2 — — 0 0 3 0 0 — — 70 — 70 35 — 25 — 25 — 50 Unit ns ns ns ns ns ns ns ns ns ns ns tRC tAA tOHA tACS tDOE tHZOE tLZCS tPU! tPD ! tLZOE  OE to Low-Z Output OE to High-Z Output CS to Low-Z Output CS to High-Z Output CS to Power-Up CS to Power-Down   tHZCS Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in .igure 1. 2. Tested with the load in .igure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and .all Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See .igures 1 and 2 AC TEST LOADS 480 Ω 5V 5V 480 Ω OUTPUT 100 pF Including jig and scope 255 Ω OUTPUT 5 pF Including jig and scope 255 Ω .igure 1. .igure 2. 4 Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001 1+$ + #$ AC WAVE.ORMS READ CYCLE NO. 1(1,2) t RC ADDRESS t AA t OHA DOUT PREVIOUS DATA VALID t OHA DATA VALID READ CYCLE NO. 2(1,3) t RC ADDRESS t AA OE t OHA t DOE CS t HZOE t LZOE t ACS t LZCS t HZCS DATA VALID DOUT HIGH-Z Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS = VIL. 3. Address is valid prior to or coincident with CS LOW transitions. Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001 5 1+$ + #$ WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter Write Cycle Time CS to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time " -45 ns Min. Max. 45 35 25 1 0 25 20 0 — — — — — — — — Min. 70 60 60 1 0 55 30 0 -70ns Max. — — — — — — — — Unit ns ns ns ns ns ns ns ns tWC tSCS tAW tHA tSA tPWE tSD tHD WE Pulse Width Data Setup to Write End Data Hold from Write End Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in .igure 1. 2. Tested with the load in .igure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CS LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 4. Tested with OE HIGH. AC WAVE.ORMS WRITE CYCLE NO. 1(CS Controlled, OE is HIGH or LOW) (1 ) t WC ADDRESS VALID ADDRESS t SA CS t SCS t HA WE t AW t PWE1 t PWE2 t HZWE t LZWE HIGH-Z DOUT DATA UNDEFINED t SD DIN t HD DATAIN VALID 6 Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001 1+$ + #$ AC WAVE.ORMS WRITE CYCLE NO. 2(OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CS LOW t AW t PWE1 WE t SA DOUT DATA UNDEFINED t HZWE HIGH-Z t LZWE t SD DIN t HD DATAIN VALID WRITE CYCLE NO. 3(OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE CS LOW t HA LOW t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE HIGH-Z t LZWE t SD DIN t HD DATAIN VALID Notes: 1. The internal write time is defined by the overlap of Cs LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. I/O will assume the High-Z state if OE ≥ VIH. Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001 7 1+$ + #$ DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Vcc for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform Vcc =2.0V, CE ≥ Vcc – 0.2V See Data Retention Waveform See Data Retention Waveform Com. Ind. Min. 2.0 — — 0 Max. 5.5 250 500 — — Unit V µA ns ns VDR IDR tSDR tRDR 5 DATA RETENTION WAVE.ORM tSDR VCC 5.0V (CE Controlled) Data Retention Mode tRDR 3.0V VDR CE ≥ VCC - 0.2V CE GND 8 Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001 1+$ + #$ ORDERING IN.ORMATION Commerical Range: 0°C to +70°C Speed (ns) 45 70 Order Part No. IC62C256-45T IC62C256-45U IC62C256-70T IC62C256-70U Package 8*13.4mm TSOP-1 330mil SOP 8*13.4mm TSOP-1 330mil SOP ORDERING IN.ORMATION Industrial Range: –40°C to +85°C Speed (ns) 45 70 Order Part No. IC62C256-45TI IC62C256-45UI IC62C256-70TI IC62C256-70UI Package 8*13.4mm TSOP-1 330mil SOP 8*13.4mm TSOP-1 330mil SOP Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001 9 1+$ + #$ HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 .ax: 886-3-5783000 Integrated Circuit Solution Inc. BRANCH O..ICE: 7., NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 .AX: 886-2-26962252 http://www.icsi.com.tw 10 Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001