IC62LV12816DL-55B

IC62LV12816DL IC62LV12816DLL Document Title 128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM Revision History Revision No 0A History Initial Draft Draft Date June 7,2002 Remark Preliminary The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. LPSR025-0A 6/7/2002 1 IC62LV12816DL IC62LV12816DLL 128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES • High-speed access times: 55, 70, 100 ns • CMOS low power operation --60mW (typical)* operating --3µW (typical)* CMOS standby • TTL compatible interface levels • Single 2.7V-3.6V Vcc power supply • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial temperature available • Available in the 44-pin TSOP-2 and 48-pin 6x8mm TF-BGA • CE2 pin only for 48-pin TF-BGA. * Typical values are measured at VCC=3.0V, TA=25°C Preliminary DESCRIPTION The ICSI IC62LV12816DL and IC62LV12816DLL are lowpower,2,097,152 bit static RAMs organized as 131,072 words by 16 bits. They are fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE1 is HIGH or when CE2 is low (deselected) or both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using Chip Enable Output and Enable inputs, CE1, CE2 and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IC62LV12816DL and IC62LV12816DLL are packaged in the JEDEC standare 44-pin TSOP-2 and 48-pin 6*8mm TFBGA. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 16 MEMORY ARRAY VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CE1, CE2 OE WE UB LB CONTROL CIRCUIT ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. LPSR025-0A 6/7/2002 IC62LV12816DL IC62LV12816DLL PIN CONFIGURATIONS 44-Pin TSOP-2 A4 A3 A2 A1 A0 CE1 I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC 48-Pin TF-BGA (TOP View) 1 A B C D E F G H LB I/O8 I/O9 GND Vcc I/O14 I/O15 NC 2 OE UB I/O10 I/O11 I/O12 I/O13 NC A8 3 A0 A3 A5 NC NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11 6 CE2 I/O0 I/O2 Vcc GND I/O6 I/O7 NC PIN DESCRIPTIONS A0-A16 I/O0-I/O15 CE1 CE2 OE WE Address Inputs Data Input/Output Chip Enable1 Input Chip Enable2 Input, BGA only Output Enable Input Write Enable Input LB UB NC Vcc GND Lower-byte Control (l/O0-I/O7) Upper-byte Control (l/O8-I/O15) No Connection Power Ground TRUTH TABLE Mode Not Selected WE CE1 H X L L L L L L L L L CE2 X L H H H H H H H H H OE X X X H H L L L X X X LB X X H L X L H L L H L UB X X H X L H L L H L L I/O0/-I/O7 High-Z High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN I/O PIN I/O8-I/O15 High-Z High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Vcc Current Standby Standby Standby Active Active Active Active Active Active Active Active X X X Output Disabled H H Read H H H Write L L L Integrated Circuit Solution Inc. LPSR025-0A 6/7/2002 3 IC62LV12816DL IC62LV12816DLL OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 2.7V- 3.6V 2.7V - 3.6V ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS VCC TSTG PT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Vcc related to GND Storage Temperature Power Dissipation Value –0.5 to Vcc + 0.5 –40 to +85 –0.3 to +4.0 –65 to +150 1.0 Unit V °C V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH(1) VIL(2) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions IOH = –1 mA IOL = 2.1 mA Min. 2.0 — 2.2 –0.2 –1 –1 Max. — 0.4 VCC + 0.2 0.4 1 1 Unit V V V V µA µA GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC, OUTPUTS DISABLED Notes: 1. VIH(max.) = Vcc + 0.2V for pulse width less than 10ns. 2. VIL(min.) = –2.0V for pulse width less than 10 ns. CAPACITANCE(1) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 4 Integrated Circuit Solution Inc. LPSR025-0A 6/7/2002 IC62LV12816DL IC62LV12816DLL AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0.4V to 2.2V 5 ns 1.3V See Figures 1 and 2 AC TEST LOADS 1 TTL OUTPUT 100 pF Including jig and scope OUTPUT 5 pF Including jig and scope 1 TTL Figure 1 Figure 2 IC62LV12816DL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC ISB1 Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = 3.0V., IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL, f = 0 CE1 = VIH, CE2 = VIL Com. Ind. Com. Ind. -55 Min. Max. — — — — — — 40 45 0.5 1.0 35 50 -70 Min. Max. — — — — — — 30 35 0.5 1.0 35 50 -100 Min. Max. — — — — — — 20 25 0.5 1.0 35 50 Unit mA mA ISB2 VCC = Max., Com. CE1 ≥ VCC – 0.2V, Ind. or CE2 ≤ 0.2V other input = 0-VCC, f = 0 µA OR ULB Control VCC = Max., CE1 = VIL, CE2 = VIH VIN ≤ 0.2V, f = 0, UB / LB = VCC – 0.2V Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Integrated Circuit Solution Inc. LPSR025-0A 6/7/2002 5 IC62LV12816DL IC62LV12816DLL IC62LV12816DLL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC ISB1 Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) OR ULB Control VCC = Max., CE1 = VIL, CE2 = VIH VIN ≤ 0.2V, f = 0, UB / LB = VCC – 0.2V Test Conditions VCC = Max IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL, CE1 = VIH, CE2 = VIL Com. Ind. Com. Ind. -55 Min. Max. — — — — — — 40 45 0.5 1.0 10 15 -70 Min. Max. — — — — — — 30 35 0.5 1.0 10 15 -100 Min. Max. — — — — — — 20 25 0.5 1.0 10 15 Unit mA mA ISB2 VCC = Max., f = 0 Com. CE1 ≥ VCC – 0.2V, Ind. or CE2 ≤ 0.2V other input = 0-VCC, f = 0 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -55 Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time (2) -70 Max. — 55 — 55 30 20 — 20 — 55 25 — Min. 70 — 10 — — — 5 0 10 — 0 0 Max. — 70 — 70 35 25 — 25 — 70 25 — Min. 55 — 10 — — — 5 0 10 — 0 0 -100 Min. Max. 100 — 15 — — — 5 0 10 — 0 0 — 100 — 100 50 30 — 30 — 100 35 — Unit ns ns ns ns ns ns ns ns ns ns ns ns tRC tAA tOHA tACE tDOE tHZOE tLZOE (2) OE to High-Z Output OE to Low-Z Output tHZCE(2) CE to High-Z Output tLZCE(2) CE to Low-Z Output tBA tHZB tLZB LB, UB Access Time LB, UB o High-Z Output LB. UB to Low-Z Output Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 6 Integrated Circuit Solution Inc. LPSR025-0A 6/7/2002 IC62LV12816DL IC62LV12816DLL AC TEST LOADS READ CYCLE NO.1(1,2) (Address Controlled) (CE1 = OE = VIL, CE2 = VIH, UB or LB = VIL) tRC ADDRESS tAA tOHA tOHA DATA VALID DOUT PREVIOUS DATA VALID AC WAVEFORMS READ CYCLE NO. 2(1,3) (OE, Controlled) tRC ADDRESS tAA tOHA OE tDOE tHZOE CE1 tLZOE CE2 tACE tLZCE tHZCE LB, UB tBA tHZB DATA VALID DOUT HIGH-Z tLZB Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1, UB, or LB = VIL, CE2 = VIH 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. Integrated Circuit Solution Inc. LPSR025-0A 6/7/2002 7 IC62LV12816DL IC62LV12816DLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) -55 Symbol Parameter Write Cycle Time CE1 Low and CE2 HIGH to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width Data Setup to Write End Data Hold from Write End (3) -70 Max. — — — — — — — — — 30 — Min. 70 65 65 0 0 60 40 30 0 — 5 Max. — — — — — — — — — 30 — Min. 55 50 50 0 0 45 45 25 0 — 5 -100 Min. Max 100 80 80 0 0 80 80 40 0 — 5 — — — — — — — — — 40 — Unit ns ns ns ns ns ns ns ns ns ns ns tWC tSCE tAW tHA tSA tPWB tPWE tSD tHD tHZWE WE LOW to High-Z Output tLZWE(3) WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE1 LOW, and UB or LB, WE LOW, and CE2 HIGH. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE1 or CE2, Controlled, OE = HIGH or LOW) t WC ADDRESS VALID ADDRESS t SA CE1 t SCE t HA CE2 t AW t PWE WE t PBW UB, LB t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID Notes: 1. WRITE is an internally generated signal asserted during an overlap of the WE, CE1 = VIL, CE2 = VIH and at least one of the LB and UB inputs being in the LOW state. 8 Integrated Circuit Solution Inc. LPSR025-0A 6/7/2002 IC62LV12816DL IC62LV12816DLL WRITE CYCLE NO. 2 (WE Controlled; OE is HIGH During Write Cycle) t WC ADDRESS VALID ADDRESS t HA OE t SCE CE1 CE2 WE t AW t PWE t SA t PBW UB, LB t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID WRITE CYCLE NO. 3 (WE Controlled; OE is LOW During Write Cycle) t WC ADDRESS VALID ADDRESS OE CE1 LOW t HA t SCE CE2 t AW t PWE WE t SA UB, LB t PBW t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID Integrated Circuit Solution Inc. LPSR025-0A 6/7/2002 9 IC62LV12816DL IC62LV12816DLL WRITE CYCLE NO. 4 (UB / LB Controlled) t WC ADDRESS ADDRESS 1 t WC ADDRESS 2 OE t SA CE1 CE2 WE t HA t SA t PBW t PBW WORD 2 t HA UB, LB WORD 1 t HZWE DOUT HIGH-Z t LZWE t HD DATAIN VALID DATA UNDEFINED t SD DIN t SD DATAIN VALID t HD DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Vcc for Data Retention Data Retention Current Test Condition See Data Retention Waveform VCC = 1.5V, CE1 ≥ VCC – 0.2V (1) Min. 1.5 Com. (-L) Com. (-LL) Ind. (-L) Ind. (-LL) — — — — 0 Max. 3.6 20 5 25 8 — — Unit V µA VDR IDR tSDR tRDR Data Retention Setup Time Recovery Time See Data Retention Waveform See Data Retention Waveform ns ns tRC Notes: 1. 1) CE1 ≥ VCC -0.2V, CE2 ≥ VCC -0.2V, (CE1 controlled) or 2) 0V ≤ CE2 ≤ 0.2V (CE2 controlled) or 3) LB = UB ≥ VCC -0.2V, CE2 ≥ VCC -0.2V (LB/UB controlled) 10 Integrated Circuit Solution Inc. LPSR025-0A 6/7/2002 IC62LV12816DL IC62LV12816DLL DATA RETENTION WAVEFORM (CE1 Controlled) tSDR VCC 2.7V Data Retention Mode tRDR 2.2V VDR CE1 ≥ VCC - 0.2V CE1 GND Integrated Circuit Solution Inc. LPSR025-0A 6/7/2002 11 IC62LV12816DL IC62LV12816DLL ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part No. 55 70 100 IC62LV12816DL-55T IC62LV12816DL-55B IC62LV12816DL-70T IC62LV12816DL-70B IC62LV12816DL-100T IC62LV12816DL-100B Package TSOP-2 6*8mm TF-BGA TSOP-2 6*8mm TF-BGA TSOP-2 6*8mm TF-BGA Industrial Range: -40°C to +85°C Speed (ns) Order Part No. 55 70 100 IC62LV12816DL-55TI IC62LV12816DL-55BI IC62LV12816DL-70TI IC62LV12816DL-70BI IC62LV12816DL-100TI IC62LV12816DL-100BI Package TSOP-2 6*8mm TF-BGA TSOP-2 6*8mm TF-BGA TSOP-2 6*8mm TF-BGA ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part No. 55 70 100 IC62LV12816DLL-55T IC62LV12816DLL-55B IC62LV12816DLL-70T IC62LV12816DLL-70B IC62LV12816DLL-100T IC62LV12816DLL-100B Package TSOP-2 6*8mm TF-BGA TSOP-2 6*8mm TF-BGA TSOP-2 6*8mm TF-BGA Industrial Range: -40°C to +85°C Speed (ns) Order Part No. 55 70 100 IC62LV12816DLL-55TI IC62LV12816DLL-55BI IC62LV12816DLL-70TI IC62LV12816DLL-70BI IC62LV12816DLL-100TI IC62LV12816DLL-100BI Package TSOP-2 6*8mm TF-BGA TSOP-2 6*8mm TF-BGA TSOP-2 6*8mm TF-BGA Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 12 Integrated Circuit Solution Inc. LPSR025-0A 6/7/2002