IC62LV256L-20TI

IC62LV256L Document Title 32K x 8 Low Power SRAM with 3.3V Revision History Revision No 0A History Initial Draft Draft Date October 5,2001 Remark The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. ALSR008-0A 10/5/2001 1 IC62LV256L 32K x 8 LOW VOLTAGE CMOS STATIC RAM FEATURES • High-speed access time: 15, 20, 25 ns • Automatic power-down when chip is deselected • CMOS low power operation — 255 mW (max.) operating — 0.18 mW (max.) CMOS standby • TTL compatible interface levels • Single 3.3V power supply • Fully static operation: no clock or refresh required • Three-state outputs DESCRIPTION The ICSI IC62LV256L is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 15 ns maximum. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 50 µW (typical) with CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory. The IC62LV256L is available in the JEDEC standard 28-pin 300mil SOJ and the 8*13.4mm TSOP-1 package. FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 256 X 1024 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE OE WE CONTROL CIRCUIT ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. ALSR008-0A 10/5/2001 IC62LV256L PIN CONFIGURATION 28-Pin SOJ A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 PIN CONFIGURATION 8x13.4mm TSOP-1 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 PIN DESCRIPTIONS A0-A14 CE OE WE I/O0-I/O7 Vcc GND Address Inputs Chip Enable Input Output Enable Input Write Enable Input Input/Output Power Ground TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X H H L CE H L L L OE X H L X I/O Operation High-Z High-Z DOUT DIN Vcc Current ISB1, ISB2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +4.6 –55 to +125 –65 to +150 0.5 20 Unit V °C °C W mA Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Integrated Circuit Solution Inc. ALSR008-0A 10/5/2001 3 IC62LV256L OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V +10% 3.3V ± 10% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC, Outputs Disabled Com. Ind. Com. Ind. Test Conditions VCC = Min., IOH = –2.0 mA VCC = Min., IOL = 4.0 mA Min. 2.4 — 2.2 –0.3 –2 –5 –2 –5 Max. — 0.4 VCC + 0.3 0.8 2 5 2 5 Unit V V V V µA µA Notes: 1. VIL = –3.0V for pulse width less than 10 ns. 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC1 ICC2 ISB1 Vcc Operating Supply Current Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., CE = VIL IOUT = 0 mA, f = 0 VCC = Max., CE = VIL IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 VCC = Max., CE ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Com. Ind. Com. Ind. Com. Ind. -15 ns Min. Max. — — — — — — — — 50 60 70 70 3 5 50 100 -20 ns Min. Max. — — — — — — — — 50 60 60 60 3 5 50 100 -25 ns Min. Max. — — — — — — 50 60 50 50 3 5 Unit mA mA mA ISB2 — 50 — 100 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 5 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V. 4 Integrated Circuit Solution Inc. ALSR008-0A 10/5/2001 IC62LV256L READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time (2) (2) -15 ns Min. Max. 15 — 2 — — 0 — 3 — 0 — — 15 — 15 7 — 8 — 6 — 15 -20 ns Min. Max. 20 — 2 — — 0 — 3 — 0 — — 20 — 20 8 — 9 — 9 — 18 -25 ns Min. Max. 25 — 2 — — 0 — 3 — 0 — — 25 — 25 9 — 10 — 10 — 20 Unit ns ns ns ns ns ns ns ns ns ns ns tRC tAA tOHA tACE tDOE tLZOE tLZCE tPU tPD (3) (3) OE to Low-Z Output OE to High-Z Output CE to Low-Z Output CE to High-Z Output CE to Power-Up CE to Power-Down tHZOE (2) tHZCE(2) Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 635 Ω 3.3V 3.3V 635 Ω OUTPUT 30 pF Including jig and scope 702 Ω OUTPUT 5 pF Including jig and scope 702 Ω Figure 1. Figure 2. Integrated Circuit Solution Inc. ALSR008-0A 10/5/2001 5 IC62LV256L AC WAVEFORMS READ CYCLE NO. 1(1,2) tRC ADDRESS tAA tOHA tOHA DATA VALID DOUT READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tDOE tHZOE CE tACE tLZCE tLZOE tHZCE DATA VALID DOUT HIGH-Z tPU tPD 50% 50% ICC SUPPLY CURRENT ISB Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. 6 Integrated Circuit Solution Inc. ALSR008-0A 10/5/2001 IC62LV256L WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time (4) -15 ns Min. Max. 15 10 10 0 0 10 8 0 — 0 — — — — — — — — 7 — -20 ns Min. Max. 20 13 15 0 0 13 10 0 — 0 — — — — — — — — 8 — -25 ns Min. Max. 25 15 20 0 0 15 12 0 — 0 — — — — — — — — 10 — Unit ns ns ns ns ns ns ns ns ns ns tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE(2) tLZWE (2) WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2) tWC ADDRESS tSCE tHA CE tAW WE tSA tHZWE tPWE tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Integrated Circuit Solution Inc. ALSR008-0A 10/5/2001 7 IC62LV256L WRITE CYCLE NO. 2 (CE Controlled)(1,2) tWC ADDRESS tSA tSCE tHA CE tAW tPWE WE tHZWE tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE ≥ VIH. ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 15 20 25 Order Part No. IC62LV256L-15T IC62LV256L-15J IC62LV256L-20T IC62LV256L-20J IC62LV256L-25T IC62LV256L-25J Package 8*13.4mm TSOP-1 300mil SOJ 8*13.4mm TSOP-1 300mil SOJ 8*13.4mm TSOP-1 300mil SOJ ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) 15 20 25 Order Part No. IC62LV256L-15TI IC62LV256L-15JI IC62LV256L-20TI IC62LV256L-20JI IC62LV256L-25TI IC62LV256L-25JI Package 8*13.4mm TSOP-1 300mil SOJ 8*13.4mm TSOP-1 300mil SOJ 8*13.4mm TSOP-1 300mil SOJ 8 Integrated Circuit Solution Inc. ALSR008-0A 10/5/2001 IC62LV256L Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw Integrated Circuit Solution Inc. ALSR008-0A 10/5/2001 9