IC62LV5128L-100BI

IC62LV5128L IC62LV5128LL Document Title 512Kx8 bit Low Voltage and Ultra Low Power CMOS Static RAM Revision History Revision No 0A 0B History Initial Draft Draft Date May 1,2001 Remark Preliminary 1. Change for tPWE: 45 to 40 ns for 55 ns product August 31,2001 : 60 to 40 ns for 70 ns product 2. Change for VCC: 2.2-3.6V to 2.7-3.6V 3.1 Change for ICC test conditiomn: VCC=Max. to 3V 3.2 Change for ICC: 30 to 25mA for 55 ns product 25 to 20mA for 70 ns porduct 20 to 15 mA for 100 ns product 4.1 Change for VDR Min. : 1.2 to 1.5V 4.2 Change for IDR test condition: VCC=1.2 to 1.5V and IDR 5. Change for tHZCE 25 to 20 ns for 55 ns product 6. Change for tHZWE 33 to 30 ns for 70 ns product The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. LPSR012-0B 08/31/2001 1 IC62LV5128L IC62LV5128LL 512K x 8 LOW POWER and LOW VCC CMOS STATIC RAM FEATURES • Access times of 55, 70, 100 ns • CMOS Low power operation: — 60 mW (typical) operation — 3 µW (typical) standby • Low data retention voltage: 1.5V (min.) • Output Enable (OE) and Chip Enable (CE) inputs for ease in applications • TTL compatible inputs and outputs • Fully static operation: — No clock or refresh reguired • Single 2.7V-3.6V power supply • Available in the 32-pin 8*20mm TSOP-1, 32-pin 8*13.4mm TSOP-1 and 48-pin 6*8mm TF-BGA DESCRIPTION The ICSI IC62LV5128L and IC62LV5128LL is a low voltage, ICSI's low voltage, six transistor (6T), CMOS technology. The device is targeted to satisfy the demands of the state-of-the-art technologies such as cell phones and pagers. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Additionally, easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable ( WE) controls both writing and reading of the memory. The IC62LV5128L and IC62LV5128LL are available in 32-pin 8*20mm TSOP-1, 8*13.4mm TSOP-1 and 48-pin 6*8mm TFBGA. 524,288 words by 8 bits, CMOS SRAM. It is fabricated using FUNCTIONAL BLOCK DIAGRAM A0-A18 DECODER 512K x 8 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE OE WE CONTROL CIRCUIT ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. LPSR012-0B 08/31/2001 IC62LV5128L IC62LV5128LL PIN CONFIGURATIONS 32-Pin 8*20mm TSOP-1, 8*13.4mm STSOP-1 A11 A9 A8 A13 WE A17 A15 Vcc A18 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 48-Pin 6*8mm TF-BGA 1 A B C D E F G H A0 I/O4 I/O5 GND Vcc I/O6 I/O7 A9 2 A1 A2 3 NC WE NC 4 A3 A4 A5 5 A6 A7 6 A8 I/O0 I/O1 Vcc GND A18 OE A10 CE A11 A17 A16 A12 A15 A13 I/O2 I/O3 A14 PIN DESCRIPTIONS A0-A18 CE OE WE I/O0-I/O7 NC Vcc GND Address Inputs Chip Enable Input Output Enable Input Write Enable Input Data Input/Output No Connection Power Ground TRUTH TABLE Mode Not Selected Output Disabled Read Write WE X H H L CE H L L L OE X H L X I/O Operation High-Z High-Z DOUT DIN Vcc Current ISB1, ISB2 ICC ICC ICC OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 2.7V - 3.6V 2.7V - 3.6V Integrated Circuit Solution Inc. LPSR012-0B 08/31/2001 3 IC62LV5128L IC62LV5128LL ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VCC TBIAS TSTG PT Parameter Terminal Voltage with Respect to GND Vcc related to GND Temperature Under Bias Storage Temperature Power Dissipation Value –0.5 to Vcc + 0.5 –0.3 to +4.0 –40 to +85 –65 to +150 1 Unit V V °C °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1)(2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25oC, f = 1 MHz, VCC = 3.0 V DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage(1) Input LOW Voltage(2) Input Leakage Output Leakage Test Conditions VCC = Min., IOH = –1.0 mA VCC = Min., IOL = 2.1 mA Min. 2.0 — 2.2 –0.2 –1 –1 Max. — 0.4 VCC + 0.3 0.4 1 1 Unit V V V V µA µA GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC Notes: 1. VIH(max) =VCC +2.0V for pulse width less than 10ns. 2. VIL(min) = –2.0V for pulse width less than 10 ns. 4 Integrated Circuit Solution Inc. LPSR012-0B 08/31/2001 IC62LV5128L IC62LV5128LL IC62LV5128L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC ISB1 Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = 3V, CE = VIL IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL, CE ≥ VIH VCC = Max., f = 0 CE ≥ VCC – 0.2V, Com. Ind. Com. Ind. Com. Ind. -55 Min. Max. — — — — — — 25 25 0.2 0.3 35 50 -70 Min. Max. — — — — — — 20 20 0.2 0.3 35 50 -100 Min. Max. — — — — — — 15 15 0.2 0.3 35 50 Unit mA mA ISB2 µA VIN ≥ VCC – 0.2V or VIN ≤ 0.2V Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. IC62LV5128LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC ISB1 Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = 3V, CE = VIL IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL, CE ≥ VIH VCC = Max., f = 0 CE ≥ VCC – 0.2V, Com. Ind. Com. Ind. Com. Ind. -55 Min. Max. — — — — — — 25 25 0.2 0.3 15 20 -70 Min. Max. — — — — — — 20 20 0.2 0.3 15 20 -100 Min. Max. — — — — — — 15 15 0.3 0.3 15 20 Unit mA mA ISB2 µA VIN ≥ VCC – 0.2V or VIN ≤ 0.2V Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Integrated Circuit Solution Inc. LPSR012-0B 08/31/2001 5 IC62LV5128L IC62LV5128LL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -55 Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time (2) Min. 55 — 10 — — — 5 10 0 Max. — 55 — 55 30 20 — — 20 -70 Min. Max. 70 — 10 — — 0 5 10 0 — 70 — 70 35 25 — — 25 -100 Min. Max. 100 — 15 — — 0 5 10 0 — 100 — 100 50 30 — — 30 Unit ns ns ns ns ns ns ns ns ns tRC tAA tOHA tACE tDOE tHZOE tLZOE(2) tLZCE(2) tHZCE (2) OE to High-Z Output OE to Low-Z Output CE to Low-Z Output CE to High-Z Output Notes: 1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input Reference Level Output Reference Level Output Load Unit 0.4V to 2.2V 5 ns 1.3V 1.5V See Figures 1 and 2 AC TEST LOADS 1 TTL OUTPUT 100 pF Including jig and scope OUTPUT 5 pF Including jig and scope 1 TTL Figure 1 Figure 2 6 Integrated Circuit Solution Inc. LPSR012-0B 08/31/2001 IC62LV5128L IC62LV5128LL AC TEST LOADS READ CYCLE NO.1(1,2) t RC ADDRESS t AA t OHA DOUT PREVIOUS DATA VALID t OHA DATA VALID AC WAVEFORMS READ CYCLE NO. 2(1,3) t RC ADDRESS t AA OE t OHA t DOE CE t HZOE t LZOE t ACE t LZCE t HZCE DATA VALID DOUT HIGH-Z Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Circuit Solution Inc. LPSR012-0B 08/31/2001 7 IC62LV5128L IC62LV5128LL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power) -55 Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output (3) -70 Max. — — — — — — — — 30 — Min. 70 65 65 0 0 40 30 0 — 5 Max. — — — — — — — — 30 — Min. 55 50 50 0 0 40 25 0 — 5 -100 Min. Max 100 80 80 0 0 80 40 0 — 5 — — — — — — — — 40 — Unit ns ns ns ns ns ns ns ns ns ns tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE(3) tLZWE Notes: 1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled) tWC ADDRESS tSCE tHA CE tAW WE tSA tHZWE tPWE tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID 8 Integrated Circuit Solution Inc. LPSR012-0B 08/31/2001 IC62LV5128L IC62LV5128LL WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)) tWC ADDRESS OE tSCE tHA CE tAW WE tSA tHZWE tPWE tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)) tWC ADDRESS OE tSCE tHA CE tAW WE tSA tHZWE tPWE tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Integrated Circuit Solution Inc. LPSR012-0B 08/31/2001 9 IC62LV5128L IC62LV5128LL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Vcc for Data Retention Data Retention Current Test Condition See Data Retention Waveform Vcc = 1.5V, CE ≥ Vcc – 0.2V Com. (-L) Com. (-LL) Ind. (-L) Ind. (-LL) Min. 1.5 — — — — 0 Max. 3.6 10 5 15 9 — — Unit V µA µA µA µA ns ns VDR IDR tSDR tRDR Data Retention Setup Time Recovery Time See Data Retention Waveform See Data Retention Waveform 5 DATA RETENTION WAVEFORM tSDR VCC 2.7V (CE Controlled) Data Retention Mode tRDR 2.2V VDR CE ≥ VCC - 0.2V CE GND 10 Integrated Circuit Solution Inc. LPSR012-0B 08/31/2001 IC62LV5128L IC62LV5128LL ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part No. 55 IC62LV5128L-55T IC62LV5128L-55H IC62LV5128L-55B IC62LV5128L-70T IC62LV5128L-70H IC62LV5128L-70B IC62LV5128L-100T IC62LV5128L-100H IC62LV5128L-100B Package 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA Industrial Range: -40°C to +85°C Speed (ns) Order Part No. 55 IC62LV5128L-55TI IC62LV5128L-55HI IC62LV5128L-55BI IC62LV5128L-70TI IC62LV5128L-70HI IC62LV5128L-70BI IC62LV5128L-100TI IC62LV5128L-100HI IC62LV5128L-100BI Package 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 70 70 100 100 ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part No. 55 IC62LV5128LL-55T IC62LV5128LL-55H IC62LV5128LL-55B IC62LV5128LL-70T IC62LV5128LL-70H IC62LV5128LL-70B IC62LV5128LL-100T IC62LV5128LL-100H IC62LV5128LL-100B Package 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA Industrial Range: -40°C to +85°C Speed (ns) Order Part No. 55 IC62LV5128LL-55TI IC62LV5128LL-55HI IC62LV5128LL-55BI IC62LV5128LL-70TI IC62LV5128LL-70HI IC62LV5128LL-70BI Package 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 70 70 100 100 IC62LV5128LL-100TI 8*20mm TSOP-1 IC62LV5128LL-100HI 8*13.4mm TSOP-1 IC62LV5128LL-100BI 6*8mm TF-BGA Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw Integrated Circuit Solution Inc. LPSR012-0B 08/31/2001 11