IS61LV25616-8K

IS61LV25616 FEATURES • • • • • 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY High-speed access time: 8, 10, 12, and 15 ns CMOS low power operation TTL compatible interface levels Single 3.3V ± 10% power supply Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial temperature available DESCRIPTION The 1+51 IS61LV25616 is a high-speed, 4,194,304-bit static RAM organized as 262,144 words by 16 bits. It is fabricated using 1+51's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61LV25616 is packaged in the JEDEC standard 44-pin 400mil SOJ, 44 pin 400mil TSOP-2 and 48-pin 6*8 TFBGA. FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER 256K x 16 MEMORY ARRAY VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CE OE WE UB LB CONTROL CIRCUIT ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. SR040-0C 1 IS61LV25616 PIN CONFIGURATIONS 44-Pin TSOP-2 and SOJ 48-Pin TF-BGA 1 2 OE UB I/O2 I/O3 I/O4 I/O5 NC A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O10 I/O11 I/O12 I/O13 WE A11 6 N/C I/O8 I/O9 Vcc GND I/O14 I/O15 NC A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 A B C D E F G H LB I/O0 I/O1 GND Vcc I/O6 I/O7 NC PIN DESCRIPTIONS A0-A17 I/O0-I/O15 CE OE WE Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input LB UB NC Vcc GND Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground TRUTH TABLE Mode Not Selected Output Disabled Read WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LB X X H L H L L H L UB X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Vcc Current ISB, ISB ICC ICC Write ICC 2 Integrated Circuit Solution Inc. SR040-0C IS61LV25616 ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS VCC TSTG PT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Vcc Related to GND Storage Temperature Power Dissipation Value –0.5 to Vcc+0.5 –45 to +90 –0.3 to +4.0 –65 to +150 1.0 Unit V °C V °C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.  OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ± 10% 3.3V ± 10% ! " Min. 2.4 — 2.0 –0.3 GND < VIN < VCC GND < VOUT < VCC Outputs Disabled Com. Ind. Com. Ind. –1 –5 –1 –5 Max. — 0.4 VCC + 0.3 0.8 1 5 1 5 Unit V V V V µA µA DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA # $ % & ' Notes: 1. VIL (min.) = –2.0V for pulse width less than 10 ns. 2. The Vcc operating range for 8 ns is 3.3V +10%, -5%. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC ISB Parameter Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL CE ≥ VIH , f = 0 VCC = Max., CE ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Com. Ind. Com. Ind. -8 ns Min. Max. — — — — — — 350 360 55 65 10 15 -10 ns Min. Max. — — — — — — 320 330 55 65 10 15 -12 ns Min. Max. — — — — — — 290 300 55 65 10 15 -15 ns Min. Max. — — — — — — 260 270 55 65 10 15 Unit mA mA    3 ISB mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Integrated Circuit Solution Inc. SR040-0C IS61LV25616 CAPACITANCE(1) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time  Note: 1. Tested initially and after any design or process changes that may affect these parameters. Min. 8 — 3 — — 0 0 0 3 — 0 0 -8 Max. — 8 — 8 4 4 — 4 — 4 4 — -10 Min. Max. 10 — 3 — — — 0 0 3 — 0 0 — 10 — 10 5 5 — 5 — 5 5 — -12 Min. Max. 12 — 3 — — — 0 0 3 — 0 0 — 12 — 12 6 6 — 6 — 6 6 — -15 Min. Max. 15 — 3 — — 0 0 0 3 — 0 0 — 15 — 15 7 6 — 6 — 7 6 — Unit ns ns ns ns ns ns ns ns ns ns ns ns tRC tAA tOHA tACE tDOE tHZOE tLZOE  OE to High-Z Output OE to Low-Z Output CE to High-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output tHZCE tBA tHZB tLZB tLZCE  CE to Low-Z Output Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 Notes: 1. The Vcc operating range for 8 ns is 3.3V +10%, -5%. AC TEST LOADS 3.3V 319 Ω 3.3V 319 Ω OUTPUT 30 pF Including jig and scope 353 Ω OUTPUT 5 pF Including jig and scope 353 Ω Figure 1 4 Figure 2 Integrated Circuit Solution Inc. SR040-0C IS61LV25616 AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL) t RC ADDRESS  t OHA DATA VALID t AA t OHA DOUT PREVIOUS DATA VALID ! " READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA # $ % tHZCE tHZB DATA VALID OE tDOE tHZOE CE tLZCE tLZOE tACE LB, UB tBA tLZB & '    DOUT HIGH-Z Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. Integrated Circuit Solution Inc. SR040-0C 5 IS61LV25616 WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width Data Setup to Write End Data Hold from Write End  Min. 8 7 7 0 0 7 7 4.5 0 — 3 -8 Max. — — — — — — — — — 4 — -10 Min. Max. 10 8 8 0 0 8 8 5 0 — 3 — — — — — — — — — 5 — -12 Min. Max. 12 9 9 0 0 9 9 6 0 — 3 — — — — — — — — — 6 — -15 Min. Max. 15 10 10 0 0 10 10 7 0 — 3 — — — — — — — — — 7 — Unit ns ns ns ns ns ns ns ns ns ns ns tWC tSCE tAW tHA tSA tPWB tPWE tSD tHD tHZWE WE LOW to High-Z Output tLZWE  WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 6 Integrated Circuit Solution Inc. SR040-0C IS61LV25616 AC WAVEFORMS WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW) (1 ) t WC ADDRESS VALID ADDRESS  t HA t SA CE t SCE WE t AW t PWE1 t PWE2 t PWB ! " t LZWE HIGH-Z UB, LB t HZWE DOUT DATA UNDEFINED # $ % & '    t SD DIN t HD DATAIN VALID Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). Integrated Circuit Solution Inc. SR040-0C 7 IS61LV25616 AC WAVEFORMS WRITE CYCLE NO. 2(WE Controlled. OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA UB, LB t PWB t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID WRITE CYCLE NO. 3(WE Controlled. OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE CE LOW t HA LOW t AW t PWE2 WE t SA UB, LB t PWB t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID 8 Integrated Circuit Solution Inc. SR040-0C IS61LV25616 AC WAVEFORMS WRITE CYCLE NO. 4(LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS ADDRESS 1 t WC ADDRESS 2  OE t SA CE LOW ! t HA t SA t HA t PWB WORD 2 WE t PWB UB, LB WORD 1 " t LZWE t HZWE DOUT HIGH-Z # $ % & '    DATA UNDEFINED t SD DIN DATAIN VALID t HD t SD DATAIN VALID t HD Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The tSA, tHA, tSD, and tHD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. Integrated Circuit Solution Inc. SR040-0C 9 IS61LV25616 ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 8 Order Part No. IS61LV25616-8T IS61LV25616-8K IS61LV25616-8B IS61LV25616-10T IS61LV25616-10K IS61LV25616-10B IS61LV25616-12T IS61LV25616-12K IS61LV25616-12B IS61LV25616-15T IS61LV25616-15K IS61LV25616-15B Package 400mil TSOP-2 400mil SOJ 6*8mm TF-BGA 400mil TSOP-2 400mil SOJ 6*8mm TF-BGA 400mil TSOP-2 400mil SOJ 6*8mm TF-BGA 400mil TSOP-2 400mil SOJ 6*8mm TF-BGA ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) 8 Order Part No. IS61LV25616-8TI IS61LV25616-8KI IS61LV25616-8BI IS61LV25616-10TI IS61LV25616-10KI IS61LV25616-10BI IS61LV25616-12TI IS61LV25616-12KI IS61LV25616-12BI IS61LV25616-15TI IS61LV25616-15KI IS61LV25616-15BI Package 400mil TSOP-2 400mil SOJ 6*8mm TF-BGA 400mil TSOP-2 400mil SOJ 6*8mm TF-BGA 400mil TSOP-2 400mil SOJ 6*8mm TF-BGA 400mil TSOP-2 400mil SOJ 6*8mm TF-BGA 10 10 12 12 15 15 HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 Integrated Circuit Solution Inc. BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 10 Integrated Circuit Solution Inc. SR040-0C