71256SA25Y

CMOS Static RAM 256K (32K x 8-Bit) Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71256SA/TTSA Description 32K x 8 advanced high-speed CMOS static RAM Commercial (0° to 70°C) and Industrial (-40° to 85°C) temperature options Equal access and cycle times – Commercial and Industrial: 12/15/20/25ns One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly TTL-compatible Low power consumption via chip deselect Commercial product available in 28-pin 300- and 600-mil Plastic DIP, 300 mil Plastic SOJ and TSOP packages Industrial product available in 28-pin 300 mil Plastic SOJ and TSOP packages The IDT71256SA is a 262,144-bit high-speed Static RAM organized as 32K x 8. It is fabricated using IDT’s high-perfomance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The IDT71256SA has an output enable pin which operates as fast as 6ns, with address access times as fast as 12ns. All bidirectional inputs and outputs of the IDT71256SA are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71256SA is packaged in 28-pin 300- and 600-mil Plastic DIP, 28-pin 300 mil Plastic SOJ and TSOP. Functional Block Diagram A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 262,144-BIT MEMORY ARRAY ADDRESS DECODER , I/O0 - I/O7 8 8 I/O CONTROL 2948 drw 01 CS WE OE CONTROL LOGIC OCTOBER 2008 1 ©2007 Integrated Device Technology, Inc. DSC-2948/09 IDT71256SA CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges Absolute Maximum Ratings(1) Pin Configurations Symbol A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 28 2 27 3 26 4 25 5 24 6 7 8 9 SO28-5 P28-2 P28-1 10 VCC WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 23 22 21 20 11 19 18 12 17 13 16 14 15 , 22 21 23 20 24 19 25 18 26 17 27 16 1 15 SO28-8 Unit VCC Supply Voltage Relative to GND -0.5 to +7.0 V VTERM Terminal Voltage Relative to GND -0.5 to VCC+0.5 V TBIAS Temperature Under Bias -55 to +125 o C -55 to +125 o C TSTG Storage Temperature PT Power Dissipation 1.0 IOUT DC Output Current 50 W mA NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DIP/SOJ Top View 28 Value 2948 tbl 02 2948 drw 02 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 Rating 14 2 13 3 12 4 11 5 10 6 9 7 8 A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 Truth Table(1,2) , CS OE WE I/O L L H DATA OUT Read Data L X L DATAIN Write Data L H H High-Z Outputs Disabled H X X High-Z Deselecte d - Standby (ISB) V HC(3) X X High-Z Deselecte d - Standby (ISB1) Function 2948 drw 02a TSOP Top View Recommended DC Operating Conditions Recommended Operating Temperature and Supply Voltage Grade Commercial Industrial 2948 tbl 03 NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VCC –0.2V. 3. Other inputs ≥VHC or ≤VLC. Temperature GND Vcc Symbol 0OC to +70OC 0V 4.5V ± 5.5V VCC Supply Voltage -40OC to +85OC 0V 4.5V ± 5.5V GND Ground VIH VIL 2948 tbl 01 Parameter Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V Input High Voltage 2.2 ____ VCC +0.5 V Input Low Voltage -0.5(1) ____ 0.8 NOTE: 1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle. 2 V 2948 tbl 04 IDT71256SA CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges DC Electrical Characteristics (VCC = 5.0V ± 10%) IDT71256SA Symbol Parameter Test Conditions Min. Max. Unit 5 µA |ILI| Input Leakage Current VCC = Max., VIN = GND to VCC ___ |ILO| Output Leakage Current VCC = Max., CS = VIH, VOUT = GND to V CC ___ 5 µA VOL Output Low Voltage IOL = 8mA, VCC = Min. ___ 0.4 V 2.4 ___ V VOH Output High Voltage IOH = -4mA, VCC = Min. 2948 tbl 05 DC Electrical Characteristics(1) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC–0.2V) Symbol Parameter 71256SA12 71256SA15 71256SA20 71256SA25 Unit ICC Dynamic Operating Current CS < VIL, Outputs Open, VCC = Max., f = fMAX(2) 160 150 145 145 mA ISB Standby Power Supply Current (TTL Level) CS > VIH, Outputs Open, VCC = Max., f = fMAX(2) 50 40 40 40 mA ISB1 Standby Power Supply Current (CMOS Level) CS > VHC, Outputs Open, VCC = Max., f = 0(2), VIN < VLC or VIN > VHC 15 15 15 15 mA 2948 tbl 06 NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. Capacitance AC Test Conditions Input Pulse Levels (TA = +25°C, f = 1.0MHz, SOJ package) GND to 3.0V Parameter(1) Symbol Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V CIN Input Capacitance Output Reference Levels 1.5V CI/O I/O Capacitance AC Test Load See Figures 1 and 2 Conditions Max. Unit VIN = 3dV 7 pF VOUT = 3dV 7 pF 2948 tbl 08 2948 tbl 07 NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. 5V 5V 480Ω 480Ω DATA OUT DATA OUT 30pF* 5pF* 255Ω 2948 drw 03 255Ω . , 2948 drw 04 Figure 1. AC Test Load Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ , tOW, and tWHZ) *Including jig and scope capacitance. 6.42 3 IDT71256SA CMOS Static RAM 256K (32K x 8-Bit) AC Electrical Characteristics Commercial and Industrial Temperature Ranges (VCC = 5.0V ± 10%) 71256SA12 71256SA15 71256SA20 71256SA25 Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle Time 12 ____ 15 ____ 20 ____ 25 ____ ns Address Access Time ____ 12 ____ 15 ____ 20 ____ 25 ns tACS Chip Select Access Time ____ 12 ____ 15 ____ 20 ____ 25 ns tCLZ(1) Chip Select to Output in Low-Z 4 ____ 4 ____ 4 ____ 4 ____ ns tCHZ(1) Chip Sele ct to Output in High-Z 0 Symbol Parameter Read Cycle tRC tAA 6 0 7 0 10 0 11 ns ____ 6 ____ 7 ____ 10 ____ 11 ns tOE Output Enable to Output Valid tOLZ(1) Output Enab le to Output in Low-Z 0 ____ 0 ____ 0 ____ 0 ____ ns tOHZ(1) Output Disab le to Output in High-Z 0 6 0 6 0 8 0 10 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ 3 ____ ns tPU(1) Chip Sele ct to Power Up Time 0 ____ 0 ____ 0 ____ 0 ____ ns tPD(1) Chip Deselect to Power Down Time ____ 12 ____ 15 ____ 20 ____ 25 ns 12 ____ 15 ____ 20 ____ 25 ____ ns 10 ____ 15 ____ 20 ____ ns Write Cycle tWC Write Cycle Time tAW Address Valid to End-of-Write 9 ____ tCW Chip Select to End-of-Write 9 ____ 10 ____ 15 ____ 20 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ 0 ____ ns 8 ____ 10 ____ 15 ____ 20 ____ ns 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width tWR Write Recovery Time 0 ____ tDW Data Valid to End-of-Write 6 ____ 7 ____ 11 ____ 13 ____ ns tDH Data Hold Time 0 ____ 0 ____ 0 ____ 0 ____ ns tOW(1) Output Active from End-of-Write 4 ____ 4 ____ 4 ____ 4 ____ ns tWHZ(1) Write Enab le to Output in High-Z 0 6 0 6 0 10 0 11 ns NOTE: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. 4 2948 tbl 09 IDT71256SA CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 1(1) tRC ADDRESS tAA OE tOE tOLZ CS (5) tACS tCLZ tOHZ tCHZ HIGH IMPEDANCE DATAOUT VCC SUPPLY CURRENT (3) (5) ICC (5) (5) DATA OUT VALID tPD tPU ISB 2948 drw 05 , Timing Waveform of Read Cycle No. 2(1,2,4) tRC ADDRESS tAA tOH DATAOUT tOH DATAOUT VALID PREVIOUS DATAOUT VALID 2948 drw 06 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. 6.42 5 , IDT71256SA CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4) tWC ADDRESS tAW CS tAS tWP (2) tWR WE tWHZ (5) DATAOUT tOW(5) HIGH IMPEDANCE (3) tDW DATAIN tCHZ (5) (3) tDH DATAIN VALID , 2948 drw 07 Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4) tWC ADDRESS tAW CS tAS tWR tCW WE tDW DATAIN tDH DATAIN VALID 2948 drw 08 , NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured ±200mV from steady state. 6 IDT71256SA CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges Ordering Information — Commercial 71256 TT Device Type SA XX Power Speed XXX X Package X Process/ Temperature Range Blank Commercial (0°C to +70°C) G Restricted Hazardous Substance Device P TP Y PZ 600-mil Plastic DIP (P28-1) only 25ns available 300-mil Plastic DIP (P28-2) 300-mil SOJ (SO28-5) TSOP Type I (SO28-8) 12 15 20 25 Blank TT First generation or current die step Current generation die step optional Ordering Information — Industrial 71256 Device Type TT SA XX Power Speed XXX Package X , Speed in nanoseconds 2948 drw 09 X Process/ Temperature Range I Industrial (-40°C to +85°C) G Restricted hazardous substance device Y PZ 300-mil SOJ (SO28-5) TSOP Type I (SO28-8) 12 15 20 25 Speed in nanoseconds Blank First generation or current die step TT Current generation die step optional 2948 drw 10 6.42 7 , IDT71256SA CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges Datasheet Document History 1/7/00 Pp. 1, 3, 4, 7 Pg. 6 Pg. 8 08/09/00 02/01/01 09/30/04 02/20/07 10/13/08 Pg. 7 Pg. 7 Pg. 7 Updated to new format Revised Industrial Temperature range offerings Removed Note No. 1 for Write Cycle diagrams, renumbered footnotes and notes Added Datasheet Document History Not recommended for new designs Removed "Not recommended for new designs" Added "Restricted hazardous substance device" to ordering informations. Added TT generation die step to data sheet ordering information. removed "IDT" from orderable part number CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 8 for Tech Support: ipchelp@idt.com 800-345-7015