18Mb Pipelined
QDR™II SRAM
Burst of 2
Features
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IDT71P72804
IDT71P72604
Description
18Mb Density (1Mx18, 512kx36)
Separate, Independent Read and Write Data Ports
Supports concurrent transactions
Dual Echo Clock Output
2-Word Burst on all SRAM accesses
DDR (Double Data Rate) Multiplexed Address Bus
One Read and One Write request per clock cycle
DDR (Double Data Rate) Data Buses
Two word burst data per clock on each port
Four word transfers per clock cycle (2 word bursts
on 2 ports)
Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals
from 1.4V to 1.9V.
Scalable output drivers
Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
Output Impedance adjustable from 35 ohms to 70
ohms
Commercial and Industrial Temperature Ranges
1.8V Core Voltage (VDD)
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
JTAG Interface
The IDT QDRIITM Burst of two SRAMs are high-speed synchronous memories with independent, double-data-rate (DDR), read and
write data ports. This scheme allows simultaneous read and write
access for the maximum device throughput, with two data items passed
with each read or write. Four data word transfers occur per clock
cycle, providing quad-data-rate (QDR) performance. Comparing this
with standard SRAM common I/O (CIO), single data rate (SDR) devices, a four to one increase in data access is achieved at equivalent
clock speeds. Considering that QDRII allows clock speeds in excess of
standard SRAM devices, the throughput can be increased well beyond
four to one in most applications.
Using independent ports for read and write data access, simplifies
system design by eliminating the need for bi-directional buses. All buses
associated with the QDRII are unidirectional and can be optimized for
signal integrity at very high bus speeds. The QDRII has scalable output
impedance on its data output bus and echo clocks, allowing the user to
tune the bus for low noise and high performance.
The QDRII has a single DDR address bus with multiplexed read
and write addresses. All read addresses are received on the first half of
the clock cycle and all write addresses are received on the second half
of the clock cycle. The read and write enables are received on the first
half of the clock cycle. The byte and nibble write signals are received on
both halves of the clock cycle simultaneously with the data they are
controlling on the data input bus.
Functional Block Diagram
(Note1)
D
(Note1)
DATA
REG
(Note2)
ADD
REG
DATA
REG
(Note1)
K
K
C
C
18M
MEMORY
ARRAY
(Note4)
(Note4)
OUTPUT SELECT
(Note3)
CTRL
LOGIC
OUTPUT REG
R
W
BWx
SENSE AMPS
SA
WRITE/READ DECODE
WRITE DRIVER
(Note2)
CLK
GEN
(Note1)
Q
CQ
CQ
SELECT OUTPUT CONTROL
6109 drw 16
Notes
1) Represents 18 signal lines for x18, and 36 signal lines for x36
2) Represents 19 address signal lines for x18, and 18 address signal lines for x36.
3) Represents 2 signal lines for x18, and 4r signal lines for x36.
4) Represents 36 signal lines for x18, and 72 signal lines for x36.
OCTOBER 2008
1
©2005 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.
DSC-6109/0A
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
The QDRII has echo clocks, which provide the user with a clock that
is precisely timed to the data output, and tuned with matching impedance
and signal quality. The user can use the echo clock for downstream
clocking of the data. Echo clocks eliminate the need for the user to
produce alternate clocks with precise timing, positioning, and signal qualities to guarantee data capture. Since the echo clocks are generated by
the same source that drives the data output, the relationship to the data is
not significantly affected by voltage, temperature and process, as would
be the case if the clock were generated by an outside source.
All interfaces of the QDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface. The interface
can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a VDDQ and a separate Vref,
allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V VDD. The output impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
The device is capable of sustaining full bandwidth on both the input
and output ports simultaneously. All data is in two word bursts, with
addressing capability to the burst level.
Clocking
The QDRII SRAM has two sets of input clocks, namely the K, K
clocks and the C, C clocks. In addition, the QDRII has an output “echo”
clock, CQ, CQ.
The K and K clocks are the primary device input clocks. The K clock
is, used to clock in the control signals (R, W and BWx), the read address, and the first word of the data burst during a write operation. The
K clock is used to clock in the control signals (BWx), write address and
the second word of the data burst during a write operation. The K and
K clocks are also used internally by the SRAM. In the event that the user
disables the C and C clocks, the K and K clocks will also be used to clock
the data out of the output register and generate the echo clock. The C
and C clocks may be used to clock the data out of the output register
during read operations and to generate the echo clocks. C and C must
be presented to the SRAM within the timing tolerances. The output data
from the QDRII will be closely aligned to the C and C input, through the
use of an internal DLL. When C is presented to the QDRII SRAM, the
DLL will have already internally clocked the first data word to arrive at
the device output simultaneously with the arrival of the C clock.
The C clock and second data word of the burst will also correspond.
Single Clock Mode
The QDRII SRAM may be operated with a single clock pair. C and
C may be disabled by tying both signals high, forcing the outputs and
echo clocks to be controlled instead by the K and K clocks.
DLL Operation
The DLL in the output structure of the QDRII SRAM can be used to
closely align the incoming clocks C and C with the output of the data,
generating very tight tolerances between the two. The user may disable
the DLL by holding Doff low. With the DLL off, the C and C (or K and K
if C and C are not used) will directly clock the output register of the
SRAM. With the DLL off, there will be a propagation delay from the time
the clock enters the device until the data appears at the output.
Echo Clock
The echo clocks, CQ and CQ, are generated by the C and C clocks
(or K, K if C, C are disabled). The rising edge of C generates the rising
edge of CQ, and the falling edge of CQ. The rising edge of C generates
the rising edge of CQ and the falling edge of CQ. This scheme improves
the correlation of the rising and falling edges of the echo clock and will
improve the duty cycle of the individual signals.
The echo clock is very closely aligned with the data, guaranteeing
that the echo clock will remain closely correlated with the data, within the
tolerances designated.
Read and Write Operations
QDRII devices internally store the two words of the burst as a single,
wide word and will retain their order in the burst. There is no ability to
address to the single word level or reverse the burst order; however, the
byte and nibble write signals can be used to prevent writing any individual bytes, or combined to prevent writing one word of the burst.
Read operations are initiated by holding the read port select (R) low,
and presenting the read address to the address port during the rising
edge of K which will latch the address. The data will then be read and will
appear at the device output at the designated time in correspondence
with the C and C clocks.
Write operations are initiated by holding the write port select (W) low
and designating with the Byte Write inputs (BWx) which bytes are to be
written. The first word of the data must also be present on the data input
bus D[X:0]. Upon the rising edge of K the first word of the burst will be
latched into the input register. After K has risen, and the designated hold
times observed, the second half of the clock cycle is initiated by presenting the write address to the address bus SA[X:0], the BWx inputs for the
second data word of the burst, and the second data item of the burst to the
data bus D[X:0]. Upon the rising edge of K, the second word of the burst
will be latched, along with the designated address. Both the first and
second words of the burst will then be written into memory as designated
by the address and byte write enables.
Output Enables
The QDRII SRAM automatically enables and disables the Q[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the Q outputs will come up in a high impedance
state.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on
the SRAM and Vss to allow the SRAM to adjust its output drive impedance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted
every 1024 clock cycles to correct for drifts in supply voltage and temperature. If the user wishes to drive the output impedance of the SRAM
to it’s lowest value, the ZQ pin may be tied to VDDQ.
6.42
2
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Pin Definitions
Symbol
Pin Function
D[X:0]
Input
Synchronous
BW0, BW1
BW2, BW3
Input
Synchronous
SA
Input
Synchronous
Q[X:0]
Output
Synchronous
W
Input
Synchronous
R
Input
Synchronous
C
Input Clock
Description
Data input signals, sampled on the rising edge of K and K clocks during valid write operations
1M x 18 -- D[17:0]
512K x 36 -- D[35:0]
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of K
clocks during write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data.
Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written in to the device.
1M x 18 -- BW0 controls D[8:0] and BW1 controls D[17:9]
512K x 36 -- BW0 controls D[8:0], BW1 controls D[17:9], BW2 controls D[26:18] and BW3 controls D[35:27]
Address Inputs. Read addresses are sampled on the rising edge of K clock during active read operations. Write
addresses are sampled on the rising edge of K clock during active write operations. These address inputs are
multiplexed, so that both a read and write operation can occur on the same clock cycle. These inputs are ignored when
the appropriate port is deselected.
Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising
edge of both the C and C clocks during Read operations or K and K when operating in single clock mode. When the
Read port is deselected, Q[X:0] are automatically three-stated.
Write Control Logic active Low. Sampled on the rising edge of the positive input clock (K). When asserted active, a write
operation in initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause
D[X:0] to be ignored.
Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read
operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is
allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock.
Each read access consists of a burst of two sequential transfer.
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be
used together to deskew the flight times of various devices on the board back to the controller. See application example
for further details.
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can
be used together to deskew the flight times of various devices on the board back to the controller. See application
example for further details.
C
Input Clock
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out
data through Q[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.
Input Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data
through Q[X:0] when in single clock mode.
K
CQ, CQ
ZQ
Output Clock
Input
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs
and can be used as a data valid indication. These signals are free running and do not stop when the output data is tristated.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance.
Q[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this
pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected
directly to GND or left unconnected.
6109 tbl 02a
6.42
3
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Pin Definitions continued
Symbol
Pin Function
Description
Doff
Input
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL turned off will be
different from those listed in this data sheet. There will be an increased propagation delay from the incidence of C and C
to Q, or K and K to Q as configured. The propagation delay is not a tested parameter, but will be similar to the
propagation delay of other SRAM devices in this speed grade.
TDO
Output
TDO pin for JTAG
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG. An internal resistor will pull TDI to V DD when the pin is unconnected.
TMS
Input
TMS pin for JTAG. An internal resistor will pull TMS to V DD when the pin is unconnected.
NC
No Connect No connects inside the package. Can be tied to any voltage level
VREF
Input
Reference
Reference Voltage input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC
measurement points.
V DD
Power
Supply
Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.
V SS
Ground
Ground for the device. Should be connected to ground of the system.
VDDQ
Power
Supply
Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or scaled to the
desired output voltage.
6109 tbl 02b
6.42
4
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Pin Configuration IDT71P72804 (1M x 18)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
VSS/
SA (3)
NC/
SA (1)
W
BW1
K
NC
R
SA
VSS/
SA (2)
CQ
B
NC
Q9
D9
SA
NC
K
BW0
SA
NC
NC
Q8
C
NC
NC
D10
VSS
SA
SA
SA
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
SA
SA
SA
VSS
NC
NC
D1
P
NC
NC
Q17
SA
SA
C
SA
SA
NC
D0
Q0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
165-ball FBGA Pinout
TOP VIEW
6109 tbl 12b
NOTES:
1. A3 is reserved for the 36Mb expansion address.
2. A10 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 2 (71P72804) devices.
3. A2 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 2 (71P72804) devices.
6.42
5
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Pin Configuration IDT71P72604 (512K x 36)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
VSS/
SA (4)
NC/
SA (2)
W
BW2
K
BW1
R
NC/
SA (1)
VSS/
SA (3)
CQ
B
Q27
Q18
D18
SA
BW3
K
BW0
SA
D17
Q17
Q8
C
D27
Q28
D19
VSS
SA
SA
SA
VSS
D16
Q7
D8
D
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
SA
SA
SA
VSS
Q10
D9
D1
P
Q35
D35
Q26
SA
SA
C
SA
SA
Q9
D0
Q0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
6109 tbl 12c
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A9 is reserved for the 36Mb expansion address.
2. A3 is reserved for the 72Mb expansion address.
3. A10 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 2 (71P72604)
devices.
4. A2 is reserved for the 288Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 2 (71P72604)
devices.
6.42
6
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Absolute Maximum Ratings(1) (2)
Symbol
Value
Unit
Symbol
Supply Voltage on VDD with
Respect to GND
–0.5 to +2.9
V
CIN
VTERM
Supply Voltage on VDDQ with
Respect to GND
–0.5 to VDD +0.3
V
VTERM
Voltage on Input terminals with
respect to GND.
–0.5 to VDD +0.3
V
VTERM
Voltage on Output and I/O
terminals with respect to GND.
-0.5 to VDDQ +0.3
V
TBIAS
Temperature Under Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
IOUT
Continuous Current into Outputs
+ 20
mA
VTERM
Rating
Capacitance (TA = +25°C, f = 1.0MHz)(1)
CCLK
CO
Parameter
BW2
BW3
Write Byte 0
L
X
X
X
Write Byte 1
X
L
X
X
Write Byte 2
X
X
L
X
Write Byte 3
X
X
X
L
5
pF
Clock Input Capacitance
6
pF
7
pF
VDD = 1.8V
VDDQ = 1.5V
Output Capacitance
Recommended DC Operating and
Temperature Conditions
Write Descriptions(1,2,3)
BW1
Unit
6109 tbl 06
NOTE:
1. Tested at characterization and retested after any design or process
change that may affect these parameters.
6109 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VDDQ must not exceed VDD during normal operation.
BW0
Max.
Input Capacitance
Symbol
Signal
Conditions
Parameter
Min.
Typ.
Max.
Unit
VDD
Power Supply Voltage
1.7
1.8
1.9
V
VDDQ
I/O Supply Voltage
1.4
1.5
VDD
V
VSS
Ground
0
0
0
V
VREF
Input Reference Voltage
0.68
VDDQ/2
0.95
V
TA
Ambient
Temperature
Commercial
(1)
Industrial
0 to +70
o
c
-40 to +85
o
c
6109 tbl 04
NOTE:
1. During production testing, the case temperature equals the ambient
temperature.
6109 tbl 09
NOTES:
1) All byte write (BWx) signals are sampled on
the rising edge of K and again on K. The data that is present on the
data bus in the designated byte will be latched into the input if
the corresponding BWx is held low. The rising edge of K will
sample the first byte of the two word burst and the rising edge
of K will sample the second byte of the two word burst.
2) The availability of the BWx on designated devices is de
scribed in the pin description table.
3) The QDRII Burst of two SRAM has data forwarding. A read request
that is initiated on the same cycle as a write request to the same
address will produce the newly written data in response to the read
request.
6.42
7
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Application Example
SRAM #1
VT
SRAM #4
D
ZQ
Q
SA R W B W 0 B W 1 C C
KK
250
Ω
D
SA R W B W 0 B W 1 C C
ZQ
Q
KK
250
Ω
R
Data In
Data Out
Address
R
W
BWx
MEMORY
CONTROLLER
R
R
R
R
R
VT VT
R
R
Return CLK
Source CLK
Return C L K
Source C L K
R = 50Ω
VT = VREF
6109 drw 20
6.42
8
VT
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current
IIL
VDD = Max VIN = VSS to VDDQ
-2
+2
µA
Output Leakage Current
IOL
Output Disabled
-2
+2
µA
Operating Current
(x36): DDR
Operating Current
(x18): DDR
Standby Current: NOP
IDD
IDD
ISB1
VDD = Max,
IOUT = 0mA (outputs open),
Cycle Time > tKHKH Min
VDD = Max,
IOUT = 0mA (outputs open),
Cycle Time > tKHKH Min
Device Deselected (in NOP state),
Iout = 0mA (outputs open),
f=Max,
All Inputs VDD -0.2V
Com'l
Ind
200MHZ
-
950
1000
167MHZ
-
850
900
250MHZ
-
850
-
200MHZ
-
750
800
167MHZ
-
650
700
250MHZ
-
375
-
200MHZ
-
335
385
167MHZ
-
300
350
Note
mA
1
mA
1,8
mA
2,8
Output High Voltage
VOH1
RQ = 250Ω, IOH = -15mA
VDDQ/2-0.12
VDDQ/2+0.12
V
3,7
Output Low Voltage
VOL1
RQ = 250Ω, IOL = 15mA
VDDQ/2-0.12
VDDQ/2+0.12
V
4,7
Output High Voltage
VOH2
IOH = -0.1mA
VDDQ-0.2
VDDQ
V
5
Output Low Voltage
VOL2
IOL = 0.1mA
VSS
0.2
V
6
6109 tbl 10c
NOTES:
1. Operating Current is measured at 100% bus utilization.
2. Standby Current is only after all pending read and write burst operations are completed.
3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω , which gives a nominal 50Ω output impedance.
4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω , which gives a nominal 50Ω output impedance.
5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an
impedance measurement point.
6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance
measurement point.
7. Programmable Impedance Mode.
8. Industrial temperature range is not available for the 250MHz speed grade.
6.42
9
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Commercial and IndustrialTemperature Range
Input Electrical Characteristics Over
Undershoot Timing
the Operating Temperature and
Supply Voltage Range
VIH
(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Parameter
Symbol
Input High Voltage, DC
VIH (DC)
Input Low Voltage, DC
VIL (DC)
-0.3
Input High Voltage, AC
VIH (AC)
VREF +0.2
Input Low Voltage, AC
VIL (AC)
Min
Max
Unit
Notes
V
1,2
VREF -0.1
V
1,3
-
V
4,5
VREF +0.1 VDDQ +0.3
-
VREF -0.2
V
VSS
VSS-0.25V
VSS-0.5V
6109 drw 22
20% tKHKH (MIN)
4,5
6109 tbl 10d
NOTES:
1.These are DC test criteria. DC design criteria is VREF + 50mV. The
AC VIH/VIL levels are defined separately for measuring timing param
eters.
2. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse
width