71V67703S80PFI

256K X 36, 512K X 18 IDT71V67703 3.3V Synchronous SRAMs IDT71V67903 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ data, address and control registers. There are no registers in the data output path (flow-through architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V67703/7903 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will flow-through from the array after a clock-to-data access time delay from the rising clock edge of the same cycle. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin. The IDT71V67703/7903 SRAMs utilize IDT’s latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA). 256K x 36, 512K x 18 memory configurations Supports fast access times: – 7.5ns up to 117MHz clock frequency – 8.0ns up to 100MHz clock frequency – 8.5ns up to 87MHz clock frequency LBO input selects interleaved or linear burst mode GW Self-timed write cycle with global write control (GW GW), byte write BWE BW enable (BWE BWE), and byte writes (BW BWx) 3.3V core power supply Power down controlled by ZZ input 3.3V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin thin plastic quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA). Description The IDT71V67703/7903 are high-speed SRAMs organized as 256K x 36/512K x 18. The IDT71V67703/7903 SRAMs contain write, Pin Description Summary A0-A18 Address Inputs Input Synchronous CE Chip Enable Input Synchronous CS0, CS1 Chip Selects Input Synchronous OE Output Enable Input Asynchronous GW Global Write Enable Input Synchronous BWE Byte Write Enable Input Synchronous BW1, BW2, BW3, BW4(1) Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV Burst Address Advance Input Synchronous ADSC Address Status (Cache Controller) Input Synchronous ADSP Address Status (Processor) Input Synchronous LBO Linear / Interleaved Burst Order Input DC ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply N/A VSS Ground Supply N/A 5309 tbl 01 NOTE: 1. BW3 and BW4 are not applicable for the IDT71V67903. FEBRUARY 2009 DECEMBER 2003 1 ©2002 Integrated Device Technology, Inc. DSC-5309/05 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Pin Definitions(1) Symbol Pin Function I/O Active Description A 0-A18 Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of CLK and ADSC Low or ADSP Low and CE Low. ADSC Address Status (Cache Controller) I LOW Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the address registers with new addresses. ADSP Address Status (Processor) I LOW Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address registers with new addresses. ADSP is gated by CE. ADV Burst Address Advance I LOW Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst counter, controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not incremented; that is, there is no address advance. BWE Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are blocked and only GW can initiate a write cycle. BW1-BW4 Individual Byte Write Enables I LOW Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active byte write causes all outputs to be disabled. CE Chip Enable I LOW Synchronous chip enable. CE is used with CS 0 and CS1 to enable the IDT71V67703/7903. CE also gates ADSP. CLK Clock I N/A This is the clock input. All timing references for the device are made with respect to this input. CS0 Chip Select 0 I HIGH Synchronous active HIGH chip select. CS 0 is used with CE and CS1 to enable the chip. CS1 Chip Select 1 I LOW Synchrono us active LOW chip select. CS1 is used with CE and CS0 to enable the chip. GW Global Write Enable I LOW Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of CLK. GW supersedes individual byte write enables. I/O0-I/O31 I/OP1-I/OP4 Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The data output path is flow-through (no output register). LBO Linear Burst Order I LOW Asynchronous burst order selection input. When LBO is HIGH, the inter-leaved burst sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state while the device is operating. OE Output Enable I LOW Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a highimpedance state. V DD Power Supply N/A N/A 3.3V core power supply. VDDQ Power Supply N/A N/A 3.3V I/O Supply. V SS Ground N/A N/A Ground. NC No Connect N/A N/A NC pins are not electrically connected to the device. ZZ Sleep Mode 1 HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V67703/7903 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode. NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 6.42 2 5309 tbl 02 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Functional Block Diagram LBO AD V CLK 2 Binary Counter AD SC Q1 ADSP A0–A17/18 GW BW E BW Burst Logic Q0 CLR CLK EN ADDRESS REGISTER INTERNAL ADDRESS Burst Sequence CEN 2 A0,A1 18/19 A0* A1* A2 - A18 36/18 18/19 Byte 1 Write Register 9 Byte 2 Write Driver 2 9 Byte 3 Write Register BW Byte 3 Write Driver 3 9 Byte 4 Write Register BW 36/18 Byte 1 Write Driver 1 Byte 2 Write Register BW 256K x 36/ 512K x 18BIT MEMORY ARRAY Byte 4 Write Driver 4 9 CE CS0 CS 1 D Q Enable Register DATA INPUT REGISTER CLK EN ZZ Powerdown OE OE I/O0–I/O31 I/OP1–I/OP4 OUTPUT BUFFER 36/18 5309 drw 01 6.42 3 , IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Absolute Maximum Ratings(1) Symbol (2) Rating Commercial Unit VTERM Terminal Voltage with Respect to GND -0.5 to +4.6 V VTERM(3,6) Terminal Voltage with Respect to GND -0.5 to VDD V VTERM(4,6) Terminal Voltage with Respect to GND -0.5 to VDD +0.5 V VTERM(5,6) Terminal Voltage with Respect to GND -0.5 to VDDQ +0.5 V TA (7) Operating Temperature -0 to +70 o C C Recommended Operating Temperature Supply Voltage Grade Temperature(1) VSS VDD V DDQ Commercial 0°C to +70°C 0V 3.3V±5% 3.3V±5% Industrial -40°C to +85°C 0V 3.3V±5% 3.3V±5% 5309 tbl 04 NOTE: 1. TA is the "instant on" case temperature. Recommended DC Operating Conditions Symbol TBIAS Temperature Under Bias -55 to +125 o TSTG Storage Temperature -55 to +125 o C PT Power Dissipation 2.0 W IOUT DC Output Current 50 mA CIN Input Capacitance CI/O I/O Capacitance 3.135 3.3 3.465 V V DDQ I/O Supply Voltage 3.135 3.3 3.465 V VSS Supply Voltage 0 0 0 V VIH Input High Voltage - Inputs 2.0 ____ VDD +0.3 V 2.0 ____ VDDQ +0.3 V ____ 0.8 V VIL CIN Input Capacitance CI/O I/O Capacitance Input High Voltage - I/O Input Low Voltage (1) -0.3 NOTE: 1. VIL (min) = -1.0V for pulse width less than t CYC/2, once per cycle. Parameter(1) Conditions Max. Unit Symbol VIN = 3dV 5 pF CIN Input Capacitance VOUT = 3dV 7 pF CI/O I/O Capacitance 5309 tbl 07 (TA = +25° C, f = 1.0MHz) Parameter(1) Unit 5309 tbl 05 (TA = +25° C, f = 1.0MHz) 119 BGA Capacitance Symbol Max. 165 fBGA Capacitance (TA = +25° C, f = 1.0MHz) Parameter(1) Typ. Core Supply Voltage VIH 100-Pin TQFP Capacitance Symbol Min. VDD 5309 tbl 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD terminals only. 3. VDDQ terminals only. 4. Input terminals only. 5. I/O terminals only. 6. This is a steady-state DC parameter that applies after the power supplies have ramped up. Power supply sequencing is not necessary; however, the voltage on any input or I/O pin cannot exceed V DDQ during power supply ramp up. 7. TA is the "instant on" case temperature. Parameter Conditions Max. Unit VIN = 3dV 7 pF VOUT = 3dV 7 pF 5309 tbl 07a NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. 6.42 4 Conditions Max. Unit VIN = 3dV 7 pF VOUT = 3dV 7 pF 5309 tbl 07b IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges A6 A7 CE CS0 BW4 BW3 BW2 BW1 CS1 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 Pin Configuration – 256K x 36, 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/OP3 I/O16 I/O17 VDDQ VSS I/O18 I/O19 I/O20 I/O21 VSS VDDQ I/O22 I/O23 VSS(1) VDD NC VSS I/O24 I/O25 VDDQ VSS I/O26 I/O27 I/O28 I/O29 VSS VDDQ I/O30 I/O31 I/OP4 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 51 30 I/OP2 I/O15 I/O14 VDDQ VSS I/O13 I/O12 I/O11 I/O10 VSS VDDQ I/O9 I/O8 VSS NC VDD ZZ(2) I/O7 I/O6 VDDQ VSS I/O5 I/O4 I/O3 I/O2 VSS VDDQ I/O1 I/O0 I/OP1 NC A17 A10 A11 A12 A13 A14 A15 A16 NC NC VSS VDD LBO A5 A4 A3 A2 A1 A0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Top View NOTES: 1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL. 2. Pin 64 can be left unconnected and the device will always remain in active mode. 6.42 5 5309 drw 02a , IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges A6 A7 CE CS0 NC NC BW2 BW1 CS1 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 Pin Configuration – 512K x 18, 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC NC NC 1 80 2 79 3 VDDQ VSS NC NC I/O8 I/O9 VSS VDDQ I/O10 I/O11 VSS(1) VDD NC VSS I/O12 I/O13 VDDQ VSS I/O14 I/O15 I/OP2 NC VSS VDDQ NC NC NC 4 78 77 5 76 6 75 7 74 73 8 9 72 71 10 11 70 12 69 13 68 14 67 66 15 16 65 64 17 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 A10 NC NC VDDQ VSS NC I/OP1 I/O7 I/O6 VSS VDDQ I/O5 I/O4 VSS NC VDD ZZ(2) I/O3 I/O2 VDDQ VSS I/O1 I/O0 NC NC VSS VDDQ NC NC NC LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC A18 A11 A12 A13 A14 A15 A16 A17 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Top View NOTES: 1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL. 2. Pin 64 can be left unconnected and the device will always remain in active mode. 6.42 6 5309 drw 02b , IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Pin Configuration – 256K x 36, 119 BGA 1 2 3 4 5 6 7 A VDDQ A6 A4 ADSP A8 A16 VDDQ B NC CS0(4) A3 ADSC A9 A17 NC C NC A7 A2 VDD A12 A15 NC D I/O16 I/OP3 VSS NC VSS I/OP2 I/O15 E I/O17 I/O18 VSS CE VSS I/O13 I/O14 F VDDQ I/O19 VSS OE VSS I/O12 VDDQ G I/O20 I/O21 BW3 ADV BW2 I/O11 I/O10 H I/O22 I/O23 VSS GW VSS I/O9 I/O8 J VDDQ V DD NC VDD NC VDD VDDQ K I/O24 I/O26 VSS CLK VSS I/O6 I/O7 L I/O25 I/O27 BW4 NC BW1 I/O4 I/O5 M VDDQ I/O28 VSS BWE VSS I/O3 VDDQ N I/O29 I/O30 VSS A1 VSS I/O2 I/O1 P I/O31 I/OP4 VSS A0 VSS I/OP1 I/O 0 R NC A5 LBO VDD VSS(1) A13 NC T NC NC A 10 A11 A14 NC ZZ(2) VDDQ DNU(3) DNU(3) DNU(3) DNU(3) DNU(3) U VDDQ 5309 drw 02c Top View Pin Configuration – 512K x 18, 119 BGA A 1 2 VDDQ A6 (4) 3 4 5 6 7 A4 ADSP A8 A16 VDDQ B NC CS0 A3 ADSC A9 A18 NC C NC A7 A2 VDD A13 A17 NC D I/O8 NC VSS NC VSS I/OP1 NC E NC I/O9 VSS CE VSS NC I/O7 F VDDQ NC VSS OE VSS I/O6 VDDQ G NC I/O10 BW2 ADV VSS NC I/O5 H I/O11 NC VSS GW VSS I/O4 NC J VDDQ V DD NC VDD NC VDD VDDQ K NC I/O12 VSS CLK VSS NC I/O3 L I/O13 NC VSS NC BW1 I/O2 NC M VDDQ I/O14 VSS BWE VSS NC VDDQ N I/O15 NC VSS A1 VSS I/O1 NC P NC I/OP2 VSS A0 VSS NC I/O0 R NC A5 LBO VDD VSS(1) A12 NC T NC A10 A 15 NC A14 A11 ZZ (2) VDDQ DNU(3) DNU(3) DNU(3) DNU(3) DNU(3) U VDDQ 5309 drw 02d Top View NOTES: 1. R5 does not have to be directly connected to VSS as long as the input voltage is < VIL. 2. T7 can be left unconnected and the device will always remain in active mode. 3. DNU= Do not use; these signals can either be left unconnected or tied to Vss. 4. On future 18M devices CS0 will be removed, B2 will be used for address expansion. 6.42 7 , IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Pin Configuration – 256K x 36, 165 fBGA 1 2 3 4 5 6 7 8 9 10 11 A NC A7 CE BW3 BW2 CS1 BWE ADSC ADV A8 NC B NC A6 CS0 BW4 BW1 CLK GW OE ADSP A9 NC(3) C I/OP3 NC VDDQ V SS V SS VSS VSS VSS VDDQ NC I/OP2 D I/O17 I/O16 VDDQ V DD V SS VSS VSS VDD VDDQ I/O15 I/O14 E I/O19 I/O18 VDDQ V DD V SS VSS VSS VDD VDDQ I/O13 I/O12 F I/O21 I/O20 VDDQ V DD V SS VSS VSS VDD VDDQ I/O11 I/O10 G I/O23 I/O22 VDDQ V DD V SS VSS VSS VDD VDDQ I/O9 I/O8 H VSS (1) NC NC V DD V SS VSS VSS VDD NC NC ZZ(2) J I/O25 I/O24 VDDQ V DD V SS VSS VSS VDD VDDQ I/O7 I/O6 K I/O27 I/O26 VDDQ V DD V SS VSS VSS VDD VDDQ I/O5 I/O4 L I/O29 I/O28 VDDQ V DD V SS VSS VSS VDD VDDQ I/O3 I/O2 M I/O31 I/O30 VDDQ V DD V SS VSS VSS VDD VDDQ I/O1 I/O0 N I/OP4 NC VDDQ V SS NC NC(3) NC (3) (3) (4) VSS VDDQ NC I/OP1 (4) P NC NC A5 A2 DNU A1 DNU A10 A13 A14 A17 R LBO NC(3) A4 A3 DNU(4) A0 DNU(4) A11 A12 A15 A16 5309tbl 17a Pin Configuration – 512K x 18, 165 fBGA 1 2 3 4 5 6 7 8 9 10 11 A NC(3) A7 CE BW2 NC CS1 BWE ADSC ADV A8 A10 B NC A6 CS 0 NC BW1 CLK GW OE ADSP A9 NC(3) C NC NC VDDQ V SS VSS V SS VSS VSS VDDQ NC I/OP1 D NC I/O8 VDDQ V DD VSS V SS VSS VDD VDDQ NC I/O7 E NC I/O9 VDDQ V DD VSS V SS VSS VDD VDDQ NC I/O6 F NC I/O10 VDDQ V DD VSS V SS VSS VDD VDDQ NC I/O5 G NC I/O11 VDDQ V DD VSS V SS VSS VDD VDDQ NC I/O4 H VSS(1) NC NC V DD VSS V SS VSS VDD NC NC ZZ(2) J I/O12 NC VDDQ V DD VSS V SS VSS VDD VDDQ I/O3 NC K I/O13 NC VDDQ V DD VSS V SS VSS VDD VDDQ I/O2 NC L I/O14 NC VDDQ V DD VSS V SS VSS VDD VDDQ I/O1 NC M I/O15 NC VDDQ V DD VSS V SS VSS VDD VDDQ I/O0 NC NC N I/OP2 NC (3) VDDQ V SS (3) NC (4) NC VSS VDDQ NC NC (4) P NC NC A5 A2 DNU A1 DNU A11 A14 A15 A18 R LBO NC(3) A4 A3 DNU(4) A0 DNU(4) A12 A13 A16 A17 5309 tbl 17b NOTES: 1. H1 does not have to be directly connected to V SS, as long as the input voltage is < VIL. 2. H11 can be left unconnected and the device will always remain in active mode. 3. Pin N6, B11, A1, R2 and P2 are reserved for 18M, 36M, 72M, and 144M and 288M respectively. 4. DNU= Do not use; these signals can either be left unconnected or tied to Vss. 6.42 8 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V ± 5%) Symbol Parameter Test Conditions Min. Max. Unit |ILI| Input Leakage Current VDD = Max., VIN = 0V to V DD ___ 5 µA |ILI| LBO Input Leakage Current(1) VDD = Max., VIN = 0V to V DD ___ 30 µA 5 µA V |ILO| Output Leakage Current VOUT = 0V to V CC ___ VOL Output Low Voltage IOL = +8mA, VDD = Min. ___ 0.4 VOH Output High Voltage IOH = -8mA, VDD = Min. 2.4 ___ V 5309 tbl 08 NOTE: 1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ in will be internally pulled to V SS if not actively driven. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (1) 7.5ns 8ns 8.5ns Unit Symbol IDD ISB1 ISB2 IZZ Parameter Operating Power Supply Current Test Conditions Com'l Ind Com'l Ind Com'l Ind 265 285 210 230 190 210 50 70 50 70 50 70 Device Deselected, Outputs Open, V DD = Max., VDDQ = Max., VIN > VHD or < VLD, f = fMAX (2,.3) 145 165 140 160 135 155 ZZ > VHD, VDD = Max. 50 70 50 70 50 70 Device Se lected, Outputs Open, V DD = Max., VDDQ = Max., VIN > VIH or < VIL, f = fMAX(2) mA CMOS Standby Power Supply Current Device Deselected, Outputs Open, VDD = Max., VDDQ = Max., VIN > VHD or < VLD, f = 0(2,3) Clock Running Power Supply Current Full Sleep Mode Supply Current mA mA 5309 tbl 09 NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing. 3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V. AC Test Conditions AC Test Load (VDDQ = 3.3V/2.5V) Input Pulse Levels 0 to 2ns Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V AC Test Load VDDQ/2 50Ω 3V Input Rise/Fall Times mA I/O Z0 = 50Ω , 5309 drw 03 6 See Figure 1 5 Figure 1. AC Test Load 5309 tbl 10 4 ∆tCD 3 (Typical, ns) 2 1 20 30 50 80 100 Capacitance (pF) 200 5309 drw 05 Figure 2. Lumped Capacitive Load, Typical Derating 6.42 9 , IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Synchronous Truth Table (1,3) Address Used CE CS0 CS 1 ADSP ADSC ADV GW BWE BWx OE (2) CLK I/O Deselected Cycle, Power Down None H X X X L X X X X X ↑ HI-Z Deselected Cycle, Power Down None L X H L X X X X X X ↑ HI-Z Deselected Cycle, Power Down None L L X L X X X X X X ↑ HI-Z Deselected Cycle, Power Down None L X H X L X X X X X ↑ HI-Z Deselected Cycle, Power Down None L L X X L X X X X X ↑ HI-Z Read Cycle, Begin Burst External L H L L X X X X X L ↑ DOUT Read Cycle, Begin Burst External L H L L X X X X X H ↑ HI-Z Read Cycle, Begin Burst External L H L H L X H H X L ↑ DOUT Read Cycle, Begin Burst External L H L H L X H L H L ↑ DOUT Read Cycle, Begin Burst External L H L H L X H L H H ↑ HI-Z Write Cycle, Begin Burst External L H L H L X H L L X ↑ DIN Write Cycle, Begin Burst External L H L H L X L X X X ↑ DIN Read Cycle, Continue Burst Next X X X H H L H H X L ↑ DOUT Read Cycle, Continue Burst Next X X X H H L H H X H ↑ HI-Z Read Cycle, Continue Burst Next X X X H H L H X H L ↑ DOUT Read Cycle, Continue Burst Next X X X H H L H X H H ↑ HI-Z Read Cycle, Continue Burst Next H X X X H L H H X L ↑ DOUT Read Cycle, Continue Burst Next H X X X H L H H X H ↑ HI-Z Read Cycle, Continue Burst Next H X X X H L H X H L ↑ DOUT Read Cycle, Continue Burst Next H X X X H L H X H H ↑ HI-Z Write Cycle, Continue Burst Next X X X H H L H L L X ↑ DIN Write Cycle, Continue Burst Next X X X H H L L X X X ↑ DIN Write Cycle, Continue Burst Next H X X X H L H L L X ↑ DIN Write Cycle, Continue Burst Next H X X X H L L X X X ↑ DIN Read Cycle, Suspend Burst Current X X X H H H H H X L ↑ DOUT Read Cycle, Suspend Burst Current X X X H H H H H X H ↑ HI-Z Read Cycle, Suspend Burst Current X X X H H H H X H L ↑ DOUT Read Cycle, Suspend Burst Current X X X H H H H X H H ↑ HI-Z Read Cycle, Suspend Burst Current H X X X H H H H X L ↑ DOUT Read Cycle, Suspend Burst Current H X X X H H H H X H ↑ HI-Z Read Cycle, Suspend Burst Current H X X X H H H X H L ↑ DOUT Read Cycle, Suspend Burst Current H X X X H H H X H H ↑ HI-Z Write Cycle, Suspend Burst Current X X X H H H H L L X ↑ DIN Write Cycle, Suspend Burst Current X X X H H H L X X X ↑ DIN Write Cycle, Suspend Burst Current H X X X H H H L L X ↑ DIN Write Cycle, Suspend Burst Current H X X X H H L X X X ↑ DIN Operation 5309 tbl 11 NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. OE is an asynchronous input. 3. ZZ - low for the table. 6.42 10 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Synchronous Write Function Truth Table (1, 2) Operation GW BWE BW 1 BW 2 BW 3 BW 4 Read H H X X X X Read H L H H H H Write all Bytes L X X X X X Write all Bytes H L L L L L Write Byte 1(3) H L L H H H Write Byte 2(3) H L H L H H Write Byte 3(3) H L H H L H Write Byte 4(3) H L H H H L 5309 tbl 12 NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. BW3 and BW4 are not applicable for the IDT71V67903. 3. Multiple bytes may be selected during the same cycle. Asynchronous Truth Table (1) Operation(2) OE ZZ I/O Status Power Read L L Data Out Active Read H L High-Z Active Write X L High-Z – Data In Active Deselected X L High-Z Standby Sleep Mode X H High-Z Sleep 5309 tbl 13 NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. Synchronous function pins must be biased appropriately to satisfy operation requirements. Interleaved Burst Sequence Table ( LBO=VDD) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 0 0 1 1 1 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address(1) 1 1 1 0 0 1 0 0 5309 tbl 14 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state. Linear Burst Sequence Table ( LBO=VSS) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 1 0 1 1 0 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address(1) 1 1 0 0 0 1 1 0 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state. 6.42 11 5309 tbl 15 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges) 7.5ns Symbol Parameter 8ns 8.5ns Min. Max. Min. Max. Min. Max. Unit 8.5 ____ 10 ____ 11.5 ____ ns Clock Parameter tCYC Clock Cycle Time tCH(1) Clock High Pulse Width 3 ____ 4 ____ 4.5 ____ ns tCL(1) Clock Low Pulse Width 3 ____ 4 ____ 4.5 ____ ns ____ 7.5 ____ 8 ____ 8.5 ns 2 ____ 2 ____ ns Output Parameters tCD Clock High to Valid Data tCDC Clock High to Data Change 2 ____ tCLZ(2) Clock High to Output Active 0 ____ 0 ____ 0 ____ ns tCHZ(2) Clock High to Data High-Z 2 3.5 2 3.5 2 3.5 ns tOE Output Enable Access Time ____ 3.5 ____ 3.5 ____ 3.5 ns tOLZ(2) Output Enable Low to Output Active 0 ____ 0 ____ 0 ____ ns tOHZ(2) Output Enable High to Output High-Z ____ 3.5 ____ 3.5 ____ 3.5 ns 1.5 ____ 2 ____ 2 ____ ns 2 ____ 2 ____ ns Set Up Times tSA Address Setup Time tSS Address Status Setup Time 1.5 ____ tSD Data In Setup Time 1.5 ____ 2 ____ 2 ____ ns tSW Write Setup Time 1.5 ____ 2 ____ 2 ____ ns 1.5 ____ 2 ____ 2 ____ ns 1.5 ____ 2 ____ 2 ____ ns tSAV tSC Address Advance Setup Time Chip Enable/Select Setup Time Hold Times tHA Address Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHS Address Status Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns 0.5 ____ 0.5 ____ ns tHD Data In Hold Time 0.5 ____ tHW Write Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHAV Address Advance Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns 0.5 ____ 0.5 ____ 0.5 ____ ns 100 ____ 100 ____ 100 ____ ns 100 ____ 100 ____ ns 40 ____ 50 ____ tHC Chip Enable/Select Hold Time Sleep Mode and Configuration Parameters tZZPW ZZ Pulse Width tZZR(3) ZZ Recovery Time 100 ____ tCFG(4) Configuration Set-up Time 34 ____ NOTES: 1. Measured as HIGH above VIH and LOW below VIL. 2. Transition is measured ±200mV from steady-state. 3. Device must be deselected when powered-up from sleep mode. 4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation. 6.42 12 ns 5309 tbl 16 6.42 13 Output Disabled tSC tSA tSS tHS tOLZ tOE O1(Ax) tHC tHA Flow-through Read Ax tOHZ Ay (1) tCH tCD tSAV tHAV O1(Ay) tCDC tSW tCL O3(Ay) O4(Ay) (Burst wraps around to its initial state) ADV HIGH suspends burst Burst Flow-through Read O2(Ay) tHW O1(Ay) tCHZ O2(Ay) 5309 drw 06 , NOTES: 1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. ZZ input is LOW and LBO is Don't Care for this cycle. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH. DATAOUT OE AD V (Note 3) C E, CS 1 G W , BW E, BW x ADDRESS ADSC AD SP CLK tCYC IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Timing Waveform of Flow-Through Read Cycle (1,2) 6.42 14 Ax (2) Single Read tSA tHA tSS tHS tCLZ tCD tOE O1(Ax) tOHZ tSW Ay tCH Write I1(Ay) tSD tHD tCL tHW Az tCD tOLZ O2(Az) O3(Az) Flow-through Burst Read O1(Az) tCDC 5309 drw 07 O4(Az) , NOTES: 1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH. 2. ZZ input is LOW and LBO is Don't Care for this cycle. 3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address Az; O2 (Az) represents the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. DATAOUT DATAIN OE ADV GW ADDRESS ADSP CLK tCYC IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Timing Waveform of Combined Flow-Through Read and Write Cycles (1,2,3) 6.42 15 tHC O3(Aw) tSC tSA tHA tSS tHS Ax O4(Aw) (1) Ay tCL tOHZ I1(Ax) I1(Ay) I2(Ay) (ADV suspends burst) tSAV G W is ignored when ADSP initiates a cycle and is sampled on the next cycle rising edge tCH I2(Ay) (2) I3(Ay) tHAV I4(Ay) tSD I1(Az) tHW tSW Az I2(Az) tHD 5309 drw 08 I3(Az) Timing Waveform of Write Cycle No. 1 - GW Controlled , NOTES: 1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle. 2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH. DATAOUT DATAIN OE ADV (Note 3) CE, CS 1 GW ADDRESS ADSC ADSP CLK tCYC IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges (1,2,3) 6.42 16 tHC Burst Read O3(Aw) tSC tSA tHA tSS tHS O4(Aw) Ax Ay tCL Single Write tOHZ I1(Ax) I1(Ay) Burst Write I2(Ay) (AD V HIGH suspends burst) I2(Ay) BW x is ignored when ADSP initiates a cycle and is sampled on the next clock rising edge BW E is ignored when ADSP initiates a cycle and is sampled on the next cycle rising edge tCH I3(Ay) I4(Ay) tSD Extended Burst Write I1(Az) tSAV tHW tSW tHW tSW Az I2(Az) tHD 5309 drw 09 I3(Az) Timing Waveform of Write Cycle No. 2 - Byte Controlled NOTES: 1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle. 2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH. DATAOUT DATAIN OE ADV (Note 3) CE, CS1 BWx BWE ADDRESS ADSC ADSP CLK tCYC IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges (1,2,3) , 6.42 17 tSS tSC tSA tHS tOLZ tOE Ax Single Read O1(Ax) tHC tHA tCH tCL tZZPW Snooze Mode NOTES: 1. Device must power up in deselected Mode. 2. LBO is Don't Care for this cycle. 3. It is not necessary to retain the state of the input registers throughout the Power-down cycle. 4. CS0 timing transitions are identical but inverted to the CE and CS1 signaals. For example, when CE and CS1 are LOW ZZ DATAOUT OE ADV (Note 4) CE,CS 1 GW ADDRESS ADSC ADSP CLK tCYC on this waveform, CS0 is HIGH. tZZR Az 5309 drw 13 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Timing Waveform of Sleep (ZZ) and Power-Down Modes (1,2,3) , IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Non-Burst Read Cycle Timing Waveform CLK AD SP AD SC ADDRESS Av Aw Ax Ay Az G W , BW E, BW x CE, CS 1 CS0 OE (Av) DATAOUT (Aw) (Ax) (Ay) NOTES: 1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle. 2. (Ax) represents the data for address Ax, etc. 3. For read cycles, ADSP and ADSC function identically and are therefore interchangable. 5309 drw 10 , Non-Burst Write Cycle Timing Waveform CLK AD SP ADSC ADDRESS Av Aw Ax Ay Az (Ax) (Ay) (Az) GW CE, CS 1 CS0 DATAIN (Av) (Aw) 5309 drw 11 NOTES: 1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle. 2. (Ax) represents the data for address Ax, etc. 3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW. 4. For write cycles, ADSP and ADSC have different limitations. 6.42 18 , IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 100-Pin Thin Plastic Quad Flatpack (TQFP) Package Diagram Outline 6.42 19 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 119 Ball Grid Array (BGA) Package Diagram Outline 6.42 20 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline 6.42 21 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Ordering Information XXX Device Type S X XX Power Speed Package X Process/ Temperature Rance Blank I Commercial (0°C to +70°C) Industrial (-40°C to +85°C) PF BG BQ 100-Pin Plastic Thin Quad Flatpack (TQFP) 119 Ball Grid Array (BGA) 165 fine pitch Ball Grid Array (fBGA) 75 80 85 Access Time in Tenths of Nanoseconds 71V67703 71V67903 256K x 36 Flow-Through Burst Synchronous SRAM 512K x 18 Flow-Through Burst Synchronous SRAM , 5309 drw 12 6.42 22 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Datasheet Document History 12/31/99 04/26/00 Created Datasheet from 71V677 and 71V679 Datasheets For 2.5V I/O offering, see 71V67702 AND 71V67902 Datasheets. Add capacitance for BGA package; Insert clarification note to Absolute Max Ratings and Recommended Operating Temperature tables. Replace Pin U6 with TRST pin in BGA pin configuration; Add pin description note in pinout Inserted 100 pin TQFP Package Diagram Outline Pg. 4 Pg. 7 Pg. 18 05/24/00 04/15/03 12/20/03 Pg. 1,4,8,21 22 Pg. 5,6,7,8 Pg. 20 Pg. 5,6,8 Pg. 7 Pg. 20 Pg. 9 Pg. 1,2 Pg. 7 Pg. 8 Pg. 9 Pg. 1-23 Pg. 4,9,12, 22 Pg. 4 Pg. 7 02/20/09 Pg. 22 07/12/00 12/18/00 10/29/01 10/22/02 Add new package offering, 13 x 15 fBGA Correct note 2 on BGA and TQFP pin configuration Correction in the 119 BGA Package Diagram Outline Remove note from TQFP and BQ165 pinouts Add/Remove note from BG119 pinout Update BG 119 pinout Updated ISB2 levels for 7.5-8.5ns. Remove JTAG pins Changed U2-U6 pins to DNU. Changed P5,P7,R5 & R7 to DNU pins. Raised specs by 10mA on 7.5ns, 8ns and 8.5ns. Changed datasheet from Advanced to Final Release. Added I temp to datasheet. Updated 165 fBGA table from TBD to 7. Updated 119BGS pin configurations- reordered I/O signals on P6, P7 (128K x 36) and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18). Removed "IDT" from orderable part number. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 23 for Tech Support: sramhelp@idt.com 800-544-7726