74LVCH16373APAG

IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT IDT74LVCH16373A TRANSPARENT D-TYPE OBSOLETE PART LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION FEATURES: The LVCH16373A 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. This high-speed, low-power latch is ideal for temporary storage of data. The LVCH16373A can be used for implementing memory address latches, I/O ports, and bus drivers. The Output Enable and Latch Enable controls are organized to operate each device as two 8-bit latches or one 16-bit latch. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. All pins of the LVCH16373A can be driven from either 3.3V or 5V devices. This feature allows the use of the device as a translator in a mixed 3.3V/5V supply system. The LVCH16373A has “bus-hold” which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range μ W typ. static) • CMOS power levels (0.4μ • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in TSSOP package R T O R F A P ED E D T S N E N E L G M O I S M S B E O O EC D R EW T N O N DRIVE FEATURES: • High Output Drivers: ±24mA • Reduced system switching noise APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 1OE 1 1LE 48 1D1 47 2OE D C Q 2 24 2LE 25 2D1 36 D 13 C Q 1Q1 2Q1 TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS INDUSTRIAL TEMPERATURE RANGE MARCH 2006 1 © 2006 Integrated Device Technology, Inc. DSC-4735/6 IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V 1OE 1 48 1LE TSTG Storage Temperature –65 to +150 °C 1Q1 2 47 1D1 IOUT DC Output Current –50 to +50 mA IIK IOK Continuous Clamp Current, VI < 0 or VO < 0 –50 mA ICC ISS Continuous Current through each VCC or GND ±100 mA 1Q2 3 46 1D2 GND 4 45 GND 1Q3 5 44 1D3 1Q4 6 43 1D4 VCC 7 42 VCC 1Q5 8 41 1D5 1Q6 9 40 1D6 GND 10 39 GND 1Q7 11 38 1D7 1Q8 12 37 1D8 2Q1 13 36 2D1 2Q2 14 35 2D2 GND 15 34 GND 2Q3 16 33 2D3 2Q4 17 32 2D4 VCC 18 31 VCC 2Q5 19 30 2D5 2Q6 20 29 2D6 GND 21 28 GND xDx Data Inputs 2Q7 22 27 2D7 xLE Latch Enable Input 2Q8 23 26 2D8 xOE Output Enable Inputs (Active LOW) 2LE xQx 3-State Outputs 2OE 24 25 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol Conditions Typ. Max. CIN Input Capacitance VIN = 0V 4.5 6 Unit pF COUT Output Capacitance VOUT = 0V 6.5 8 pF CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names Description (1) NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. TSSOP TOP VIEW FUNCTION TABLE(1) Inputs xDx xLE Outputs xOE xQx H H L H L H L L X L L Q(2) X X H Z NOTES: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level Z = High-Impedance 2. Output level before the indicated steady-state input conditions were established. 2 IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ΔICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 — — 10 mV µA 3.6 ≤ VIN ≤ 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND — — — — 10 500 µA Min. Typ.(2) Max. Unit – 75 — — µA VI = 0.8V 75 — — VI = 1.7V — — — IIH IIL Quiescent Power Supply Current Variation NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Test Conditions Bus-Hold Input Sustain Current VCC = 3V Bus-Hold Input Sustain Current VCC = 2.3V Bus-Hold Input Overdrive Current VCC = 3.6V VI = 2V IBHL IBHH IBHL IBHHO IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3 VI = 0.7V — — — VI = 0 to 3.6V — — ±500 µA µA IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL Test Conditions(1) Parameter Output HIGH Voltage Output LOW Voltage Min. Max. Unit V VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — VCC = 2.7V 2.2 — VCC = 3V 2.4 — VCC = 3V IOH = – 24mA 2.2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance per Latch Outputs enabled CPD Power Dissipation Capacitance per Latch Outputs disabled Test Conditions Typical Unit CL = 0pF, f = 10Mhz 39 pF 6 SWITCHING CHARACTERISTICS(1) VCC = 2.7V Symbol Parameter tPLH Propagation Delay tPHL xDx to xQx tPLH Propagation Delay tPHL xLE to xQx tPZH Output Enable Time VCC = 3.3V ± 0.3V Min. Max. Min. Max. Unit — 4.9 1.6 4.2 ns — 5.3 2.1 4.6 ns — 5.7 1.3 4.7 ns — 6.3 2.5 5.9 ns tPZL xOE to xQx tPHZ Output Disable Time tPLZ xOE to xQx tSU Set-up Time, data before LE↓ HIGH or LOW 1.7 — 1.7 — ns tH Hold Time, data after LE↓ HIGH or LOW 1.2 — 1.2 — ns Pulse Width xLE HIGH 3.3 — 3.3 — ns Output Skew(2) — — — 500 ps tW tSK(o) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VLOAD 6 VCC(2)= 2.5V±0.2V Unit 2 x Vcc V 6 VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION tPLH tPHL tPLH tPHL OUTPUT VIH VT 0V OPPOSITE PHASE INPUT TRANSITION LVC Link Propagation Delay Pulse (1, 2) Generator tPZL GND 500Ω VOUT OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH D.U.T. 500Ω RT CL Test Circuit for All Outputs VIH VT 0V CONTROL INPUT Open VIN DISABLE ENABLE VLOAD VCC tPLZ VLOAD/2 VT VLOAD/2 VLZ VOL tPHZ VOH VHZ 0V VT 0V LVC Link LVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. DATA INPUT SWITCH POSITION Switch Open Drain Disable Low Enable Low VLOAD ASYNCHRONOUS CONTROL Disable High Enable High GND SYNCHRONOUS CONTROL All Other Tests Open OUTPUT 1 tPLH1 tSK (x) tSK (x) tPLH2 tH Set-up, Hold, and Release Times VOH VT VOL VT tW HIGH-LOW-HIGH PULSE VT LVC Link tPHL2 Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) tSU LOW-HIGH-LOW PULSE VOH VT VOL OUTPUT 2 tREM LVC Link VIH VT 0V tPHL1 tH TIMING INPUT Test INPUT tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V LVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT LVC X XX Bus-Hold Temp. Range XX Family XX XXXX Device Type Package PA PAG Thin Shrink Small Outline Package TSSOP - Green 373A 16-Bit Transparent D-Type Latch with 3- State Outputs 16 Double-Density, ±24mA H Bus-hold 74 -40°C to +85°C DATASHEET DOCUMENT HISTORY 07/13/2015 09/06/2019 PDN# CQ-14-05 issued. See IDT.com for PDN specifics. Datasheet changed to Obsolete Status. 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