854105AGLF

Low Skew, 1-to-4, LVCMOS/LVTTL-to-LVDS Fanout Buffer 854105 DATA SHEET General Description Features The 854105 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS), the 854105 provides a low power, low noise solution for distributing clock signals over controlled impedances of 100. The 854105 accepts an LVCMOS/LVTTL input level and translates it to LVDS output levels. • • • • • • • • • • • • Guaranteed output and part-to-part skew characteristics make the 854105 ideal for those applications demanding well defined performance and repeatability. Block Diagram One single-ended LVCMOS/LVTTL input CLK can accept the following input levels: LVCMOS, LVTTL Maximum output frequency: 250MHz Translates single-ended input signals to LVDS levels Additive phase jitter, RMS: 0.16ps (typical) Output skew: 55ps (maximum) Part-to-part skew: 350ps (maximum) Propagation delay: 1.62ns (maximum) 3.3V operating supply 0°C to 70°C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment Q0 OE0 OE1 OE2 VDD nQ0 Pullup OE0 GND CLK nc OE3 Q1 nQ1 CLK Pulldown Four differential LVDS output pairs Pullup 16 15 14 13 12 11 10 9 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 OE1 854105 Q2 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View nQ2 Pullup 1 2 3 4 5 6 7 8 OE2 Q3 nQ3 Pullup 854105 Rev A 7/10/15 OE3 1 ©2015 Integrated Device Technology, Inc. 854105 DATA SHEET Table 1. Pin Descriptions Number Name Type Description 1 OE0 Input Pullup Output enable pin for Q0, nQ0 outputs. See Table 3. LVCMOS/LVTTL interface levels. 2 OE1 Input Pullup Output enable pin for Q1, nQ1 outputs. See Table 3. LVCMOS/LVTTL interface levels. 3 OE2 Input Pullup Output enable pin for Q2, nQ2 outputs. See Table 3. LVCMOS/LVTTL interface levels. 4 VDD Power Positive supply pin. 5 GND Power Power supply ground. 6 CLK Input 7 nc Unused Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. No connect. 8 OE3 Input 9, 10 nQ3, Q3 Output Pullup Differential output pair. LVDS interface levels. Output enable pin for Q3, nQ3 outputs. See Table 3. LVCMOS/LVTTL interface levels. 11, 12 nQ2, Q2 Output Differential output pair. LVDS interface levels. 13, 14 nQ1, Q1 Output Differential output pair. LVDS interface levels. 15, 16 nQ0, Q0 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k Function Table Table 3. Output Enable Function Table Inputs Outputs OE[3:0] Q[3:0], nQ[3:0] 0 High-Impedance 1 Active (default) Rev A 7/10/15 2 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER 854105 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, JA 100.3°C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. LVDS Power Supply DC Characteristics,VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 75 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V CLK VDD = VIN = 3.465V 150 µA OE[3:0] VDD = VIN = 3.465V 5 µA CLK VDD = 3.465V, VIN = 0V -5 µA OE[3:0] VDD = 3.465V, VIN = 0V -150 µA Table 4C. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Minimum Typical Maximum Units 250 350 450 mV 50 mV 1.45 V 50 mV 1.15 3 1.3 Rev A 7/10/15 854105 DATA SHEET Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical fMAX Output Frequency tPD Propagation Delay; NOTE 1 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section tsk(o) Output Skew; NOTE 2, 4 55 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 350 ps tR / tF Output Rise/Fall Time odc Output Duty Cycle 1.0 155.52MHz, Integration Range: (12kHz – 20MHz) Maximum Units 250 MHz 1.62 ns 0.16 ps 20% to 80% 130 660 ps ƒ  133MHz 45 55 % ƒ >133MHz 40 60 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing point. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load conditions. Using the same type of input on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. Rev A 7/10/15 4 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER 854105 DATA SHEET Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. SSB Phase Noise dBc/Hz Additive Phase Jitter @ 155.52MHz 12kHz to 20MHz = 0.16ps (typical) Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER The source generator "Rohde & Schwarz SMA100 Signal Generator as external input to an Agilent 8133A 3GHz Pulse Generator". 5 Rev A 7/10/15 854105 DATA SHEET Parameter Measurement Information nQx Qx VDD nQy Qy GND Output Skew 3.3V LVDS Output Load AC Test Circuit Par t 1 nQx VDD Qx 2 CLK nQy nQ[0:3] Par t 2 Qy Q[0:3] tPD tsk(pp) Part-to-Part Skew Propagation Delay nQ[0:3] Q[0:3] nQ[0:3] 80% 80% VOD Q[0:3] 20% 20% tR tF Output Duty Cycle/Pulse Width/Period Output Rise/Fall Time Rev A 7/10/15 6 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER 854105 DATA SHEET Parameter Measurement Information, continued Differential Output Voltage Setup LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Offset Voltage Setup 7 Rev A 7/10/15 854105 DATA SHEET Application Information Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVDS Outputs All control pins have internal pullups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. 3.3V LVDS Driver Termination A general LVDS interface is shown in Figure 1. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 50Ω 3.3V LVDS Driver + R1 100Ω – 50Ω 100Ω Differential Transmission Line Figure 1. Typical LVDS Driver Termination Rev A 7/10/15 8 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER 854105 DATA SHEET Power Considerations This section provides information on power dissipation and junction temperature for the 854105. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 854105 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 75mA = 259.875mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 100.3°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.260W * 100.3°C/W = 96.1°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER 0 1 2.5 100.3°C/W 96.0°C/W 93.9°C/W 9 Rev A 7/10/15 854105 DATA SHEET Reliability Information Table 7. JA vs. Air Flow Table for a 16 Lead TSSOP JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 100.3°C/W 96.0°C/W 93.9°C/W Transistor Count The transistor count for 854105 is: 286 Package Outline and Package Dimensions Package Outline - G Suffix for 16 Lead TSSOP Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75  0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 Rev A 7/10/15 10 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER 854105 DATA SHEET Ordering Information Table 9. Ordering Information Part/Order Number 854105AGLF 854105AGLFT Marking 854105AL 854105AL Package “Lead-Free” 16 Lead TSSOP “Lead-Free” 16 Lead TSSOP Shipping Packaging Tube Tape & Reel Temperature 0C to 70C 0C to 70C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER 11 Rev A 7/10/15 854105 DATA SHEET Revision History Sheet Rev A Rev A 7/10/15 Table Page T9 11 Description of Change Date Ordering Information - removed leaded devices. Updated data sheet format. 12 7/10/15 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. 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