12:2, Differential-to-LVDS Multiplexer
ICS854S202I
DATASHEET
General Description
Features
The ICS854S202I is a 12:2 Differential-to-LVDS Clock Multiplexer
which can operate up to 3GHz. The ICS854S202I has twelve selectable differential clock inputs, any of which can be independently routed to either of the two LVDS outputs. The CLKx, nCLKx input pairs
can accept LVPECL, LVDS, CML levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits.
• Two differential 3.3V LVDS clock outputs
• Twelve selectable differential clock inputs
• CLKx, nCLKx pairs can accept the following differential input levels:
LVPECL, LVDS, CML
• Maximum output frequency: 3GHz
• Propagation delay: 1.1ns (maximum)
• Input skew: 100ps (maximum)
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Additive phase jitter, RMS (12kHz – 20MHz): 0.16ps (typical)
• Full 3.3V operating supply mode
• -40°C to 85°C ambient operating temperature
Pin Assignment
Block Diagram
4
nCLK1
CLK1
GND
nCLK0
CLK0
VDD
OEB
CLK11
nCLK11
GND
CLK10
nCLK10
SELA_[3:0] Pulldown
CLK0 Pulldown
nCLK0 Pullup/Pulldown
CLK1 Pulldown
nCLK1 Pullup/Pulldown
CLK2 Pulldown
nCLK2 Pullup/Pulldown
QA
nQA
CLK3 Pulldown
nCLK3 Pullup/Pulldown
Pullup
CLK4 Pulldown
nCLK4 Pullup/Pulldown
OEA
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
48-Pin LQFP
5
32
6
7mm x 7mm x 1.4mm 31
7
30
package body
8
29
Y Package
9
28
Top View
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
ICS854S202I
CLK9
nCLK9
SELB_0
SELB_1
VDD
QB
nQB
GND
SELB_2
SELB_3
CLK8
nCLK8
nCLK4
CLK4
GND
nCLK5
CLK5
VDD
OEA
CLK6
nCLK6
GND
CLK7
nCLK7
CLK5 Pulldown
Pullup/Pulldown
nCLK5
CLK2
nCLK2
SELA_0
SELA_1
VDD
QA
nQA
GND
SELA_2
SELA_3
CLK3
nCLK3
CLK6 Pulldown
nCLK6 Pullup/Pulldown
CLK7 Pulldown
nCLK7 Pullup/Pulldown
CLK8 Pulldown
nCLK8 Pullup/Pulldown
QB
nQB
CLK9 Pulldown
Pullup/Pulldown
nCLK9
Pullup
OEB
CLK10 Pulldown
nCLK10 Pullup/Pulldown
CLK11 Pulldown
nCLK11 Pullup/Pulldown
SELB_[3:0] Pulldown
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ICS854S202I Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
1
CLK2
Input
Pulldown
2
nCLK2
Input
Pullup/Pulldown
3,
4,
9,
10
SELA_0,
SELA_1,
SELA_2,
SELA_3
Input
Pulldown
5, 18, 32, 43
VDD
Power
Power supply pins.
6, 7
QA, nQA
Output
Clock outputs. LVDS interface levels.
8, 15, 22, 29,
39, 46
GND
Power
Power supply ground.
11
CLK3
Input
Pulldown
12
nCLK3
Input
Pullup/Pulldown
Inverting differential clock input. VDD/2 default when left floating.
13
nCLK4
Input
Pullup/Pulldown
Inverting differential clock input. VDD/2 default when left floating.
14
CLK4
Input
Pulldown
16
nCLK5
Input
Pullup/Pulldown
17
CLK5
Input
Pulldown
18, 43
VDD
Power
19
OEA
Input
Pullup
20
CLK6
Input
Pulldown
21
nCLK6
Input
Pullup/Pulldown
23
CLK7
Input
Pulldown
24
nCLK7
Input
Pullup/Pulldown
Inverting differential clock input. VDD/2 default when left floating.
25
nCLK8
Input
Pullup/Pulldown
Inverting differential clock input. VDD/2 default when left floating.
26
CLK8
Input
Pulldown
Non-inverting differential clock input.
27,
28,
33,
34
SELB_3,
SELB_2,
SELB_1,
SELB_0
Input
Pulldown
Clock select pins for Bank B output pair. See Control Input Function
Table. LVCMOS/LVTTL interface levels. See Table 3C.
30, 31
nQB, QB
Output
35
nCLK9
Input
Pullup/Pulldown
36
CLK9
Input
Pulldown
37
nCLK10
Input
Pullup/Pulldown
38
CLK10
Input
Pulldown
40
nCLK11
Input
Pullup/Pulldown
41
CLK11
Input
Pulldown
42
OEB
Input
Pullup
44
CLK0
Input
Pulldown
ICS854S202AYI REVISION A JANUARY 21, 2013
Description
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Clock select pins for Bank A output pair. See Control Input Function
Table. LVCMOS/LVTTL interface levels. See Table 3B.
Non-inverting differential clock input.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Positive supply pins.
Output enable pin. Controls enabling and disabling of QA, nQA
output pair. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Clock outputs. LVDS interface levels.
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Output enable pin. Controls enabling and disabling of QB, nQB
output pair. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
2
©2013 Integrated Device Technology, Inc.
ICS854S202I Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Number
Name
Type
Description
45
nCLK0
Input
Pullup/Pulldown
47
CLK1
Input
Pulldown
48
nCLK1
Input
Pullup/Pulldown
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
2
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
Function Tables
Table 3A. OEA, OEB Control Input Function Table
Input
Output
OEA, OEB
QA, nQA, QB, nQB
0
Disabled (Logic LOW)
1
Active (default)
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ICS854S202I Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 3B. SEL_A Control Input Function Table
Control Input
Input Selected to QA, nQA
SELA_3
SELA_2
SELA_1
SELA_0
0
0
0
0
CLK0, nCLK0 (default)
0
0
0
1
CLK1, nCLK1
0
0
1
0
CLK2, nCLK2
0
0
1
1
CLK3, nCLK3
0
1
0
0
CLK4, nCLK4
0
1
0
1
CLK5, nCLK5
0
1
1
0
CLK6, nCLK6
0
1
1
1
CLK7, nCLK7
1
0
0
0
CLK8, nCLK8
1
0
0
1
CLK9, nCLK9
1
0
1
0
CLK10, nCLK10
1
0
1
1
CLK11, nCLK11
1
1
0
0
Output at logic LOW
1
1
0
1
Output at logic LOW
1
1
1
0
Output at logic LOW
1
1
1
1
Output at logic LOW
Table 3C. SEL_B Control Input Function Table
Control Input
Input Selected to QA, nQA
SELB_3
SELB_2
SELB_1
SELB_0
0
0
0
0
CLK0, nCLK0 (default)
0
0
0
1
CLK1, nCLK1
0
0
1
0
CLK2, nCLK2
0
0
1
1
CLK3, nCLK3
0
1
0
0
CLK4, nCLK4
0
1
0
1
CLK5, nCLK5
0
1
1
0
CLK6, nCLK6
0
1
1
1
CLK7, nCLK7
1
0
0
0
CLK8, nCLK8
1
0
0
1
CLK9, nCLK9
1
0
1
0
CLK10, nCLK10
1
0
1
1
CLK11, nCLK11
1
1
0
0
Output at logic LOW
1
1
0
1
Output at logic LOW
1
1
1
0
Output at logic LOW
1
1
1
1
Output at logic LOW
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ICS854S202I Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, JA
70.2C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Characteristic Tables
Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Test Conditions
Parameter
VDD
Power Supply Voltage
IDD
Power Supply Current
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
110
138
mA
Typical
Maximum
Units
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
2.2
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input High
Current
IIL
Input Low
Current
Test Conditions
Minimum
SELA_[3:0],
SELB_[3:0
VDD = 3.465V
150
A
OEA, OEB
VDD = 3.465V
10
A
SELA_[3:0,
SELB_[3:0
VDD = 3.465V, VIN = 0V
-10
A
OEA, OEB
VDD = 3.465V, VIN = 0V
-150
A
Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
IIH
Input High
Current
CLK[0:11],
nCLK[0:11]
VDD = VIN = 3.465V
150
A
Input Low
Current
CLK[0:11]
VDD = 3.465V, VIN = 0V
-10
A
IIL
nCLK[0:11]
VDD = 3.465V, VIN = 0V
-150
A
VPP
Peak-to-Peak Input Voltage; NOTE 1
VCMR
Common Mode Input Voltage:
NOTE 1, 2
0.15
1.5
V
GND + 0.5
VDD – 0.7
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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ICS854S202I Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 4D. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VOD
Differential Output Voltage
VOD
VOD Magnitude Change
VOS
Offset Voltage
VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
247
1.2
Maximum
Units
454
mV
50
mV
1.4
V
50
mV
Maximum
Units
3
GHz
AC Characteristics Table
Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency
tpLH
Propagation Delay, Low to High;
NOTE 1
tpHL
Propagation Delay, High to Low;
NOTE 1
tsk(o)
Test Conditions
Minimum
Typical
fOUT < 2GHz
450
660
1100
ps
fOUT > 2GHz
600
750
900
ps
fOUT < 2GHz
450
660
1100
ps
fOUT > 2GHz
600
750
900
ps
Output Skew; NOTE 2, 3
25
50
ps
tsk(i)
Input Skew; NOTE 3
25
100
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
250
ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
section, NOTE 5
0.16
0.215
ps
t R / tF
Output Rise/Fall Time
50
110
250
ps
odc
Output Duty Cycle; NOTE 6
40
50
60
%
MUXISOLATION
MUX Isolation
155.52MHz,
Integration Range:
12kHz - 20MHz
20% to 80%
fOUT < 1.2GHz
75
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range. Note that phase noise may increase
slightly with higher operating temperature. However, they will remain in spec as long as the maximum transistor junction temperature is not
violated. The device will meet specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input cross point to the differential output cross point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output
cross point.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of input on each device, measured at the differential output cross point.
NOTE 5: Driving only one input clock.
NOTE 6: The output duty cycle will depend on the input duty cycle.
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ICS854S202I Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Additive Phase Jitter
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
SSB PHASE NOISE dBc/HZ
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot and
is most often the specified plot in many applications. Phase noise is
defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
Offset From Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements have
issues. The primary issue relates to the limitations of the equipment.
Often the noise floor of the equipment is higher than the noise floor
of the device. This is illustrated above. The device meets the noise
floor of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
ICS854S202AYI REVISION A JANUARY 21, 2013
Used the Rhode & Schwartz SMA100 as the input source.
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ICS854S202I Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Parameter Measurement Information
VDD
SCOPE
VDD
3.3V±5%
POWER SUPPLY
+ Float GND –
Qx
nCLK[0:11]
V
Cross Points
PP
V
CMR
CLK[0:11]
nQx
GND
Differential Input Level
3.3V Output Load Test Circuit
nCLKx
CLKx
Par t 1
nQx
nQA
Qx
nQy
QA
Par t 2
tPD1
Qy
tsk(pp)
nCLKy
Part-to-Part Skew
CLKy
nQB
QB
tPD2
nQx
tsk(i) = |tPD1 - tPD2|
Qx
Input Skew
nQy
Qy
tsk(o)
Output Skew
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ICS854S202I Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Parameter Measurement Information, continued
nQA, nQB
nQA, nQB
QA, QB
80%
80%
t PW
t
VOD
PERIOD
t PW
odc =
20%
20%
QA, QB
tF
tR
x 100%
t PERIOD
Output Duty Cycle/Pulse Width
Output Rise/Fall Time
Spectrum of Output Signal Q
MUX selects active
input clock signal
A0
Amplitude (dB)
nCLK[0:11]
CLK[0:11]
MUX_ISOL = A0 – A1
nQA, nQB
MUX selects static input
A1
QA, QB
tpLH
tpHL
ƒ
(fundamental)
MUX Isolation
Propagation Delay
VDD
VDD
out
out
DC Input
DC Input
Frequency
100
VOD/Δ VOD
LVDS
out
out
VOS/Δ VOS
ä
Offset Voltage Setup
Differential Output Voltage Setup
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ICS854S202I Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVDS Outputs
For applications requiring only one differential input, the unused CLK
and nCLK input can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK pin to
ground.
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VDD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1in the center of the input voltage swing. For
example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2
value should be adjusted to set V1 at 1.25V. The values below are for
when both the single ended swing and VDD are at the same voltage.
This configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
impedance. For most 50 applications, R3 and R4 can be 100. The
values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
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ICS854S202I Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
3.3V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, CML and other differential
signals. Both VSWING and VOH must meet the VPP and VCMR input
requirements. Figures 2A to 2E show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. If the driver is from
another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
3.3V
3
3.3V
3.3V
Zo = 50Ω
3.3V
CLK
CLK
R1
100Ω
nCLK
Zo = 50Ω
nCLK
LVPECL
Input
CML
CML Built-In Pullup
Figure 2A. CLK/nCLK Input Driven by a CML Driver
Figure 2B. CLK/nCLK Input Driven by a
3Built-In Pullup CML Driver
3.3V
3.3V
3.3V
3.3V
R3
125Ω
3.3V
R4
125Ω
3.3V
R3
84
Zo = 50Ω
3.3V LVPECL
CLK
Zo = 50Ω
C1
Zo = 50Ω
C2
R4
84
CLK
Zo = 50Ω
nCLK
nCLK
LVPECL
R1
84Ω
R2
84Ω
Differential
Input
R5
100 - 200
R6
100 - 200
R1
125
R2
125
LVPECL
Input
Figure 2D. CLK/nCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
3.3V
Zo = 50Ω
CLK
R1
100Ω
Zo = 50Ω
LVDS
nCLK
Receiver
Figure 2E. CLK/nCLK Input Driven by a 3.3V LVDS Driver
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ICS854S202I Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
LVDS
Driver
standard termination schematic as shown in Figure 3A can be used
with either type of output structure. Figure 3B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
ZO ZT
ZT
LVDS
Receiver
Figure 3A. Standard Termination
LVDS
Driver
ZO ZT
C
ZT
2 LVDS
ZT Receiver
2
Figure 3B. Optional Termination
LVDS Termination
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ICS854S202I Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
LVDS Power Considerations
This section provides information on power dissipation and junction temperature for the ICS854S202I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS854S202I is the sum of the core power plus the output power dissipated due to the load.
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
PowerMAX = VDD_MAX * IDD_MAX = 3.4655V * 138mA = 478.17mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 70.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.478W * 70.2°C/W = 118.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 48 Lead LQFP, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
ICS854S202AYI REVISION A JANUARY 21, 2013
0
1
2.5
70.2°C/W
60.4°C/W
56.9°C/W
13
©2013 Integrated Device Technology, Inc.
ICS854S202I Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Reliability Information
Table 7. JA vs. Air Flow Table for a 48 Lead LQFP,
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
70.2°C/W
60.4°C/W
56.9°C/W
Transistor Count
The transistor count for ICS854S202I is: 8,537
ICS854S202AYI REVISION A JANUARY 21, 2013
14
©2013 Integrated Device Technology, Inc.
ICS854S202I Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Package Outline and Package Dimensions
Package Outline - Y Suffix for 48 Lead LQFP
Table 8. Package Dimensions for 48 Lead LQFP
JEDEC Variation: BBC - HD
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
48
A
1.60
A1
0.05
0.10
0.15
A2
1.35
1.40
1.45
b
0.17
0.22
0.27
c
0.09
0.20
D&E
9.00 Basic
D1 & E1
7.00 Basic
D2 & E2
5.50 Ref.
e
0.5 Basic
L
0.45
0.60
0.75
0°
7°
ccc
0.08
Reference Document: JEDEC Publication 95, MS-026
ICS854S202AYI REVISION A JANUARY 21, 2013
15
©2013 Integrated Device Technology, Inc.
ICS854S202I Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Ordering Information
Table 9. Ordering Information
Part/Order Number
854S202AYILF
854S202AYIFT
Marking
ICS54S202AIL
ICS54S202AIL
ICS854S202AYI REVISION A JANUARY 21, 2013
Package
“Lead-Free” 48 Lead LQFP
“Lead-Free” 48 Lead LQFP
16
Shipping Packaging
Tray
Tape & Reel
Temperature
-40C to 85C
-40C to 85C
©2013 Integrated Device Technology, Inc.
ICS854S202I Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
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