8S89833AKILF

8S89833 Low Skew, 1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination Datasheet Description Features The 8S89833 is a high speed 1-to-4 Differential-to-LVDS Fanout Buffer with Internal Termination. The 8S89833 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVPECL, LVDS, and CML to be easily interfaced to the input with minimal use of external components. The device also has an output enable pin which may be useful for system test and debug purposes. • • Four differential LVDS outputs • • • • • • • • • Output frequency: 2GHz The 8S89833 is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications. IN, nIN input pair can accept the following differential input levels: LVPECL, LVDS, CML Cycle-to-cycle jitter, RMS: 3.5ps (maximum) Additive phase jitter, RMS: 0.03ps (typical) Output skew: 30ps (maximum) Part-to-part skew: 200ps (maximum) Propagation Delay: 600ps (maximum) Full 3.3V supply mode -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package nQ0 IN Q1 16 15 14 13 12 IN 2 11 VT nQ0 50Ω nQ1 Q1 3 50Ω 10 VREF_AC nQ1 4 nQ2 D Q 7 8 8S89833 Q3 16-Lead VFQFN 3mm x 3mm x 0.925mm package body K Package Top View nQ3 ©2017 Integrated Device Technology, Inc. 6 EN VREF_AC 9 nIN 5 VDD Q2 nQ2 nIN EN Pullup Q0 1 Q2 VT GND Q3 nQ3 Q0 VDD Pin Assignment Block Diagram 1 September 22, 2017 8S89833 Datasheet Table 1. Pin Descriptions Number Name Type Description 1, 2 Q0, nQ0 Output Differential output pair. Normally terminated with 100 across the pair. LVDS interface levels. 3, 4 Q1, nQ1 Output Differential output pair. Normally terminated with 100 across the pair. LVDS interface levels. 5, 6 Q2, nQ2 Output Differential output pair. Normally terminated with 100 across the pair. LVDS interface levels. 7, 14 VDD Power Power supply pins. 8 EN Input 9 nIN Input 10 VREF_AC Output 11 VT Input Input termination center-tap. Each side of the differential input pair terminates to a VT pin. The VT pins provide a center-tap to a termination network for maximum interface flexibility. Non-inverting differential clock input. RT = 50 termination to VT. Pullup Synchronizing output enable pin. When LOW, disables outputs. When HIGH, enables outputs. Internally connected to a 37k pullup resistor. LVTTL / LVCMOS interface levels. Inverting differential LVPECL clock input. RT = 50 termination to VT. Reference voltage for AC-coupled applications. Equal to VDD - 1.4V (approx.). Maximum sink/source current is ±2mA. 12 IN Input 13 GND Power Power supply ground. 15, 16 Q3, nQ3 Output Differential output pair. Normally terminated with 100 across the pair. LVDS interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter RPULLUP Input Pullup Resistor ©2017 Integrated Device Technology, Inc. Test Conditions Minimum Typical 37 2 Maximum Units k September 22, 2017 8S89833 Datasheet Function Tables Table 3. Control Input Function Table Inputs Outputs IN nIN EN Q[0:3] nQ[0:3] 0 1 1 0 1 1 0 1 1 0 X X 0 Disabled LOWNOTE 1 Disabled HIGHNOTE 1 NOTE 1: On the next negative transition of the input signal (IN). EN VDD/2 tS VDD/2 tH nIN IN nQx VIN → tPD ← VOD Qx Figure 1. EN Timing Diagram ©2017 Integrated Device Technology, Inc. 3 September 22, 2017 8S89833 Datasheet Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Input Current, IN, nIN ±50mA VT Current, IVT ±100mA Input Sink/Source, IREF_AC ± 2mA Operating Temperature Range, TA -40°C to +85°C Package Thermal Impedance, JA, (Junction-to-Ambient) 74.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter VDD Positive Supply Voltage IDD Power Supply Current Test Conditions Minimum Typical Maximum Units 3.0 3.3 3.6 V 100 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage 2.2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current VDD = VIN = 3.6V 10 µA IIL Input Low Current VDD = 3.6V, VIN = 0V ©2017 Integrated Device Technology, Inc. Test Conditions 4 Minimum -150 Typical µA September 22, 2017 8S89833 Datasheet Table 4C. Differential DC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units RDIFF_IN Differential Input Resistance 80 100 120  RIN Input Resistance 40 50 60  VIH Input High Voltage (IN, nIN) 1.2 VDD V VIL Input Low Voltage (IN, nIN) 0 VIH – 0.15 V VIN Input Voltage Swing 0.15 1.2 V VDIFF_IN Differential Input Voltage Swing 0.3 VREF_AC Bias Voltage IIN Input Current; NOTE 1 (IN, nIN) IN-to-VT VDD – 1.44 V VDD – 1.38 IN-to-VT VDD – 1.32 V 35 mA NOTE 1: Guaranteed by design. Table 4D. LVDS DC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change ©2017 Integrated Device Technology, Inc. Test Conditions Minimum Typical 247 1.2 5 1.4 Maximum Units 454 mV 50 V 1.6 V 50 mV September 22, 2017 8S89833 Datasheet AC Electrical Characteristics Table 5. AC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency tPD Propagation Delay, (Differential); NOTE 1 tsk(o) Test Conditions Maximum Units 2 GHz 600 ps Output Skew; NOTE 2, 3 30 ps IN-to-Qx Minimum Typical 400 tsk(pp) Part-to-Part Skew; NOTE 3, 4 200 ps tjit(cc) Cycle-to-Cycle Jitter, RMS; NOTE 5, 6 3.5 ps tjit Buffer Additive Jitter; RMS; refer to Additive Phase Jitter Section ƒ = 622.08MHz, Integration Range: 12kHz - 20MHz 0.03 ƒ  156.25MHz, Integration Range: 12kHz - 20MHz ps 0.25 ps tS Clock Enable Setup Time EN to IN/nIN 300 ps tH Clock Enable Hold Time EN to IN/nIN 500 ps tR / tF Output Rise/Fall Time 20% – 80% 75 200 ps NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters characterized at  1.4GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 5: Tested at ƒ  750MHz. NOTE 6: The cycle-to-cycle jitter is dependent on the input source and measurement equipment. ©2017 Integrated Device Technology, Inc. 6 September 22, 2017 8S89833 Datasheet Additive Phase Jitter fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the SSB Phase Noise dBc/Hz Additive Phase Jitter @ 622.08MHz 12kHz to 20MHz = 0.03ps (typical) Offset from Carrier Frequency (Hz) The source generator “IFR2042 10kHz – 6.4GHz Low Noise Signal Generator as external input to an Agilent 8133A 3GHz Pulse Generator”. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. ©2017 Integrated Device Technology, Inc. 7 September 22, 2017 8S89833 Datasheet Parameter Measurement Information VDD SCOPE 3.3V±0.3V POWER SUPPLY + Float GND – nIN Qx VDD V Cross Points IN V IH IN nQx V IL GND LVDS Output Load AC Test Circuit nQx Differential Input Level Par t 1 nQx Qx Qx nQy Par t 2 nQy Qy Qy tsk(pp) Part-to-Part Skew Output Skew nQ[0:3] nIN Q[0:3] IN tcycle n tcycle n+1 nQ[0:3] tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles Q[0:3] tPD Cycle-to-Cycle Jitter, RMS ©2017 Integrated Device Technology, Inc. Propagation Delay 8 September 22, 2017 8S89833 Datasheet Parameter Measurement Information, continued nQ[0:3] VIN VDIFF_IN 80% 80% VOD Q[0:3] 20% 20% tR tF Differential Voltage Swing = 2 x Single-ended VIN Single-Ended & Differential Input Voltage Swing Output Rise/Fall Time Offset Voltage Setup Differential Output Voltage Setup ©2017 Integrated Device Technology, Inc. 9 September 22, 2017 8S89833 Datasheet Applications Information 3.3V Differential Input with Built-In 50 Termination Interface The IN /nIN with built-in 50 terminations accept LVDS, LVPECL, CML and other differential signals. Both differential signals must meet the VIN and VIH input requirements. Figures 2A to 2D show interface examples for the IN/nIN input with built-in 50 terminations driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. Figure 2A. IN/nIN Input with Built-In 50 Driven by an LVDS Driver Figure 2B. IN/nIN Input with Built-In 50 Driven by an LVPECL Driver 3.3V 3.3V 3.3V CML with Built-In Pullup Zo = 50Ω C1 IN 50Ω VT Zo = 50Ω C2 50Ω nIN V_REF_AC Receiver with Built-In 50Ω Figure 2D. IN/nIN Input with Built-In 50 Driven by a CML Driver with Built-In 50 Pullup Figure 2C. IN/nIN Input with Built-In 50 Driven by a CML Driver with Open Collector Recommendations for Unused Output Pins Outputs LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached. ©2017 Integrated Device Technology, Inc. 10 September 22, 2017 8S89833 Datasheet VFQFN EPAD Thermal Release Path and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadframe Base Package, Amkor Technology. In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 3. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE SOLDER LAND PATTERN (GROUND PAD) THERMAL VIA PIN PIN PAD Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) LVDS Driver Termination A general LVDS interface is shown in Figure 4. Standard termination for LVDS type output structure requires both a 100 parallel resistor at the receiver and a 100 differential transmission line environment. In order to avoid any transmission line reflection issues, the 100 resistor must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure X can be used with either type of output structure. If using a non-standard termination, it is recommended to contact IDT and confirm if the output is a current source or a voltage source type structure. In addition, since these outputs are LVDS compatible, the amplitude and common mode input range of the input receivers should be verified for compatibility with the output. + LVDS Driver 100Ω LVDS Receiver – 100Ω Differential Transmission Line Figure 4. Typical LVDS Driver Termination ©2017 Integrated Device Technology, Inc. 11 September 22, 2017 8S89833 Datasheet Power Considerations This section provides information on power dissipation and junction temperature for the 8S89833. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 8S89833 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 0.3V = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VDD_MAX * IDD_MAX = 3.63V * 100mA = 363mW • Power Dissipation for internal termination RT Power (RT)MAX = (VIN_MAX)2 / RT_MIN = (1.2V)2 / 80 = 18mW Total Power_MAX = 363mW + 18mW = 381mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.381W * 74.7°C/W = 113.5°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 16 Lead VFQFN Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 74.7°C/W 65.3°C/W 58.5°C/W Reliability Information Table 7. JA vs. Air Flow Table for a 16 Lead VFQFN JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 74.7°C/W 65.3°C/W 58.5°C/W Transistor Count The transistor count for 8S89833 is: 353 This device is pin and function compatible and a suggested replacement for 889833. ©2017 Integrated Device Technology, Inc. 12 September 22, 2017 8S89833 Datasheet Package Outline Drawings The package outline drawings are located in the last section of this document. The package information is the most current data available and is subject to change without notice or revision of this document. Ordering Information Table 9. Ordering Information Part/Order Number 8S89833AKILF 8S89833AKILFT Marking 833A 833A Package “Lead-Free” 16 Lead VFQFN “Lead-Free” 16 Lead VFQFN Shipping Packaging Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C Revision History Revision Date September 22, 2017 Description of Change ▪ Updated the package outline drawings; however, no mechanical changes ▪ Completed other minor improvements August 24, 2016 ▪ Table 4C Differential DC Characteristics Table, typo correction: – VIL row, maximum spec changed from VIN - 0.15V to VIH - 0.15V. ▪ Deleted “I” suffix from the part number. February 8, 2016 ▪ Removed ICS from part number where needed. ▪ Removed LF note below Ordering Information table. ▪ Updated header and footer. ©2017 Integrated Device Technology, Inc. 13 September 22, 2017 �ENES� 16L-QFN Package Outline Drawing 3.0 x 3.0 x 1.0 mm, 0.5 mm Pitch, 1.70 x 1.70 mm Epad NL/NLG16P2, PSC-4169-02, Rev 03, Page 1 vi Io.101 c 1 PIN 1 CORNER ------- + 7 3.10 2.90 Q 0.10 C TOP VIEW Llill 1.60 1.80 1.60 0.50 8 X 0.30 8 X __._ ��------��__:..i ���1 �6 -X�0.30 0.20 �j�� BOTTOM VIEW NOTES: 1. ALL DIMENSIONS ARE IN mm.ANGLES IN DEGREES © 2019 Renesas Electronics Corporation 0.70 BSC SEATING PLANEQJL � 0.00 SIDE VIEW lolo.oslcl �ENES� 16L-QFN Package Outline Drawing 3.0 x 3.0 x 1.0 mm, 0.5 mm Pitch, 1.70 x 1.70 mm Epad NL/NLG16P2, PSC-4169-02, Rev 03, Page 2 0.55 3.30 2.20 C0.35 --- + 1.70 --+----+- 1.70 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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