8T49N008A-050NLGI8

Programmable FemtoClock® NG LVPECL/LVDS Clock Generator with 8-Outputs IDT8T49N008I DATASHEET General Description Features The IDT8T49N008I is an eight output Clock Synthesizer with selectable LVDS or LVPECL outputs. The IDT8T49N008I can synthesize any one of four frequencies from a single crystal or reference clock. The four frequencies are selected from the Frequency Selection Table (Table 3A) and are programmed via I2C interface. The four predefined frequencies are selected in the user application by two frequency selection pins. Note the desired programmed frequencies must be used with the corresponding crystal or clock frequency as indicated in Table 3A. • • • Fourth Generation FemtoClock NG PLL technology • • FemtoClock NG VCO Range: 1.91GHz - 2.5GHz • • • • RMS phase jitter at 156.25MHz (10kHz - 1MHz): 175fs (typical) • • -40°C to 85°C ambient operating temperature Excellent phase noise performance is maintained with IDT’s Fourth Generation FemtoClock® NG PLL technology, which delivers sub-400fs RMS phase jitter. Eight selectable LVPECL or LVDS outputs CLK, nCLK input pair can accept the following differential input levels: LVPECL, LVDS, HCSL RMS phase jitter at 156.25MHz (12kHz - 20MHz): 228fs (typical) Full 2.5V or 3.3V power supply I2C programming interface PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter compliant Lead-free (RoHS 6) packaging Q4 nQ4 Q5 nQ5 VCCO Q6 nQ6 Q7 nQ7 VEE Pin Assignment 30 29 28 27 26 25 24 23 22 21 VEE SCLK SDATA VEE VCCA LOCK VEE VCC CLK_SEL VEE 31 20 32 19 33 18 34 17 35 16 36 15 37 14 38 13 39 12 11 40 2 3 4 5 6 7 8 9 10 Q0 nQ0 Q1 nQ1 VCCO Q2 nQ2 Q3 nQ3 VEE 1 FSEL1 VCC VEE ADDR_SEL FSEL0 nCLK CLK VEE XTAL_OUT XTAL_IN IDT8T49N008I 40-Lead VFQFN 6mm x 6mm x 0.925mm package body 4.65mm x 4.65mm E-Pad NL Package IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 1 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet Block Diagram LOCK Q0 nQ0 Q1 nQ1 CLK SEL Q2 Pulldown nQ2 Q3 XTAL_IN 1 Xtal Osc CLK nCLK PS Pulldown PU/PD nQ3 0 XTAL_OUT ÷P[1:0] 1 Phase Detector + Charge Pump ÷N[6:0] FemtoClock®NG VCO Q4 0 nQ4 Q5 nQ5 ÷M [8:1] Q6 nQ6 Q7 VPP/FSEL 0 G_CLK/FSEL 1 SCLK SDATA ADDR_SEL nQ7 Pulldown Divider, Pulldown Output Type Pullup & Output Pullup Enable Pulldown Selection IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 8 OUTPUT ENABLE 8 OUTPUT STYLE 2 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name 1, 2 Q0, nQ0 Output Type Differential output pair. LVPECL or LVDS interface levels. Description 3, 4 Q1, nQ1 Output Differential output pair. LVPECL or LVDS interface levels. 5, 26 VCCO Power Output supply pins. 6, 7 Q2, nQ2 Output Differential output pair. LVPECL or LVDS interface levels. 8, 9 Q3, nQ3 Output Differential output pair. LVPECL or LVDS interface levels. 10, 13, 18, 21, 31, 34, 37, 40 VEE Power Negative supply pins. 11, 12 XTAL_IN XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Crystal frequency is selected from Table 3A. 14 CLK Input Pulldown Non-inverting differential clock input. 15 nCLK Input Pullup/ Pulldown Inverting differential clock input. Internal resistor bias to VCC/2. 16, 20 FSEL0, FSEL1 Input Pulldown Frequency and configuration. Selects between one of four factory programmable power-up default configurations. The four configurations can have different PLL states, output frequencies, output styles and output states. These default configurations can be overwritten after power-up via I2C. LVCMOS/LVTTL interface levels. 00 = Configuration 0 (default) 01 = Configuration 1 10 = Configuration 2 11 = Configuration 3 17 ADDR_SEL Input Pulldown I2C Address select pin. LVCMOS/LVTTL interface levels. 19, 38 VCC Power Core supply pins. 22, 23 nQ7, Q7 Output Differential output pair. LVPECL or LVDS interface levels. 24, 25 nQ6, Q6 Output Differential output pair. LVPECL or LVDS interface levels. 27, 28 nQ5, Q5 Output Differential output pair. LVPECL or LVDS interface levels. 29, 30 nQ4, Q4 Output 32 SCLK Input Pullup I2C Clock Input. LVCMOS/LVTTL interface levels. 33 SDATA Input/Output Pullup I2C Data Input. Input: LVCMOS/LVTTL interface levels. Output: Open Drain. 35 VCCA Power 36 LOCK Output 39 CLK_SEL Input Differential output pair. LVPECL or LVDS interface levels. Analog supply pin. PLL Lock Indicator. LVCMOS/LVTTL interface levels. Pulldown Input source control pin. LVCMOS/LVTTL interface levels. 0 = XTAL (default) 1 = CLK, nCLK NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 3.5 pF RPULLDOWN Input Pulldown Resistor 51 k RPULLUP Input Pullup Resistor 51 k IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 Test Conditions 3 Minimum Typical Maximum Units ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet Frequency Configuration Table 3A. Frequency Configuration Examples Output Frequencies (MHz) 30.72 61.44 62.5 76.8 78.125 100 106.25 122.8 125 133.33 148.5 150 153.6 155.52 156.25 159.375 160 166.66 184.32 187.5 200 212.5 250 300 311.04 312.5 318.75 322.265625 375 400 425 491.52 614.4 622.08 625 1228.88 Input Frequency or Crystal Frequency (MHz) 30.72 30.72 25 30.72 25 25 26.5625 30.72 25 25 27 25 30.72 19.44 25 100 125 26.5625 20 25 30.72 61.44 25 25 26.5625 25 25 19.44 77.76 155.52 25 125 156.25 26.5625 25.78125 25 25 26.5625 30.72 30.72 122.88 153.6 19.44 25 30.72 Input Clock Divider P 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 5 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 5 1 2 1 1 1 1 1 2 5 1 1 1 Input Clock Prescaler PS x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x1 x2 x2 x2 x2 x2 x1 x1 x2 x2 x2 x2 x2 x1 x1 x2 x1 x2 x2 x1 x1 x2 x2 x2 x2 x1 x2 x2 x2 x2 Feedback Divider M 32 32 40 40 50 40 40 32 40 48 44 42 40 64 50 50 50 36 48 40 36 36 90 40 40 40 48 64 32 32 50 40 40 36 150 90 40 40 32 40 40 40 64 50 40 Output Divider N 64 32 32 32 32 20 20 16 16 18 16 14 16 16 16 16 16 12 12 12 12 12 12 10 10 8 8 8 8 8 8 8 8 6 6 6 5 5 4 4 4 4 4 4 2 VCO Frequency (MHz) 1966.08 1966.08 2000 2457.6 2500 2000 2125 1966.08 2000 2400 2376 2100 2457.6 2488.32 2500 2500 2500 1912.5 1920 2000 2211.84 2211.84 2250 2000 2125 2000 2400 2488.32 2488.32 2488.32 2500 2500 2500 1912.5 1933.59375 2250 2000 2125 1966.08 2457.6 2457.6 2457.6 2488.32 2500 2457.6 NOTE: Each device supports 4 output frequencies (with related input or crystal value) as selected from this table Register Settings. NOTE: XTAL operation: fOUT = fREF * PS * M / N; CLK, nCLK input operation: fOUT = (fREF / P) * PS * M / N. IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 4 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet Table 3B. I2C Register Map Register Binary Register Address Register Bit D7 D6 D5 D4 D3 D2 D1 D0 0 00000 M0[8] M0[7] M0[6] M0[5] M0[4] M0[3] M0[2] M0[1] 1 00001 M1[8] M1[7] M1[6] M1[5] M1[4] M1[3] M1[2] M1[1] 2 00010 M2[8] M2[7] M2[6] M2[5] M2[4] M2[3] M2[2] M2[1] 3 00011 M3[8] M3[7] M3[6] M3[5] M3[4] M3[3] M3[2] M3[1] 4 00100 unused N0[6] N0[5] N0[4] N0[3] N0[2] N0[1] N0[0] 5 00101 unused N1[6] N1[5] N1[4] N1[3] N1[2] N1[1] N1[0] 6 00110 unused N2[6] N2[5] N2[4] N2[3] N2[2] N2[1] N2[0] 7 00111 unused N3[6] N3[5] N3[4] N3[3] N3[2] N3[1] N3[0] 8 01000 unused BYPASS0 PS0[1] PS0[0] P0[1] P0[0] CP0[1] CP0[0] 9 01001 unused BYPASS1 PS1[1] PS1[0] P1[1] P1[0] CP1[1] CP1[0] 10 01010 unused BYPASS2 PS2[1] PS2[0] P2[1] P2[0] CP2[1] CP2[0] 11 01011 unused BYPASS3 PS3[1] PS3[0] P3[1] P3[0] CP3[1] CP3[0] 12 01100 LVDS_ SEL0[Q7] LVDS_ SEL0[Q6] LVDS_ SEL0[Q5] LVDS_ SEL0[Q4] LVDS_ SEL0[Q3] LVDS_ SEL0[Q2] LVDS_ SEL0[Q1] LVDS_ SEL0[Q0] 13 01101 LVDS_ SEL1[Q7] LVDS_ SEL1[Q6] LVDS_ SEL1[Q5] LVDS_ SEL1[Q4] LVDS_ SEL1[Q3] LVDS_ SEL1[Q2] LVDS_ SEL1[Q1] LVDS_ SEL1[Q0] 14 01110 LVDS_ SEL2[Q7] LVDS_ SEL2[Q6] LVDS_ SEL2[Q5] LVDS_ SEL2[Q4] LVDS_ SEL2[Q3] LVDS_ SEL2[Q2] LVDS_ SEL2[Q1] LVDS_ SEL2[Q0] 15 01111 LVDS_ SEL3[Q7] LVDS_ SEL3[Q6] LVDS_ SEL3[Q5] LVDS_ SEL3[Q4] LVDS_ SEL3[Q3] LVDS_ SEL3[Q2] LVDS_ SEL3[Q1] LVDS_ SEL3[Q0] 16 10000 OE0[Q7] OE0[Q6] OE0[Q5] OE0[Q4] OE0[Q3] OE0[Q2] OE0[Q1] OE0[Q0] 17 10001 OE1[Q7] OE1[Q6] OE1[Q5] OE1[Q4] OE1[Q3] OE1[Q2] OE1[Q1] OE1[Q0] 18 10010 OE2[Q7] OE2[Q6] OE2[Q5] OE2[Q4] OE2[Q3] OE2[Q2] OE2[Q1] OE2[Q0] 19 10011 OE3[Q7] OE3[Q6] OE3[Q5] OE3[Q4] OE3[Q3] OE3[Q2] OE3[Q1] OE3[Q0] 20 10100 reserved reserved reserved reserved reserved reserved unused unused 21 10101 unused unused unused unused unused unused unused unused 22 10110 unused unused unused unused unused unused unused unused 23 10111 unused unused unused unused unused unused unused unused IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 5 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet Table 3C. I2C Function Descriptions Bits Name Pn[1:0] Input Clock Divider Register n (n = 0...3) Sets the PLL input clock divider. The divider value has the range of 1, 2, 4 and 5. See Table 3F. Pn[1:0] bits are programmed with values to support default configuration settings for FSEL[1:0]. PSn(1:0) Input Prescaler Register n (n = 0...3) Sets the PLL input clock prescaler value. Valid prescaler values are x0.5, x1 or x2. See Table 3F. Set prescaler to x2 for optimum phase noise performance. PSn[1:0] bits are programmed with values to support default configuration settings for FSEL[1:0]. Mn[8:1] Integer Feedback Divider Register n (n = 0...3) Sets the integer feedback divider value. Based on the FemtoClock NG VCO range, the applicable feedback dividers settings are 16 thru 250. Please note the register value presents bits [8:1] of Mn, the LSB of Mn is not in the register. Mn[8:1] bits are programmed with values to support default configuration settings for FSEL[1:0]. Nn[6:0] Output Divider Register n (n = 0...3) Sets the output divider. The output divider value can range from 2, 3, 4, 5, 6 and 8, 10, 12 to 126 (step: 2). See Table 3G for the output divider coding. Nn[6:0] bits are programmed with values to support default configuration settings for FSEL[1:0]. CPn[1:0] PLL Bandwidth Register n (n = 0...3) Sets the FemtoClock NG PLL bandwidth by controlling the charge pump current. See Table 3H. CPn[1:0] bits are programmed with values to support default configuration settings for FSEL[1:0]. PLL Bypass Register n (n = 0...3) Bypasses PLL. Output of the prescaler is routed through the output divider N to the output fanout buffer. Programming a 1 to this bit bypasses the PLL. Programming a 0 to this bit routes the output of the prescaler through the PLL. BYPASSn bits are programmed with values to support default configuration settings for FSEL[1:0]. BYPASSn OEn[Q0] OEn[Q1] OEn[Q2] OEn[Q3] OEn[Q4] OEn[Q5] OEn[Q6] OEn[Q7] LVDS_SELn[Q0] LVDS_SELn[Q1] LVDS_SELn[Q2] LVDS_SELn[Q3] LVDS_SELn[Q4] LVDS_SELn[Q5] LVDS_SELn[Q6] LVDS_SELn[Q7] Output Enable Register n (n = 0...3) Output Style Register n (n = 0...3) IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 Function Sets the outputs to Active or High Impedance. Programming a 0 to this bit sets the outputs to High Impedance. Programming a 1 sets the outputs to active status. OEn[Q0], OEn[Q1], OEn[Q2], OEn[Q3], OEn[Q4], OEn[Q5], OEn[Q6], OEn[Q7] bits are programmed with values to support default configuration settings for FSEL[1:0]. Sets the differential output style to either LVDS or LVPECL interface levels. Programming a 1 to this bit sets the output styles to LVDS levels. Programming a 0 to this bit sets the output styles to LVPECL levels. LVDS_SELn[Q0], LVDS_SELn[Q1], LVDS_SELn[Q2], LVDS_SELn[Q3] LVDS_SELn[Q4], LVDS_SELn[Q5], LVDS_SELn[Q6], LVDS_SELn[Q7] bits are programmed with values to support default configuration settings for FSEL[1:0]. 6 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet Table 3D. Feedback Divider Mn Coding Register Bit Mn[8:1] Feedback Divider Mn Do Not Use 1 thru 15 00001000 16 00001001 18 00001010 20 00001011 22 00001100 thru 00011111 24 thru 62 00100000 64 00100001 66 00100010 68 00100011 70 00100100 72 ... Mn 00110010 100 00110011 102 00110100 104 00110101 106 ... Mn 01111010 244 01111011 246 01111100 248 01111101 250 Note: Mn is always an even value. The Mn[0] bits are not implemented. Table 3E. PLL Pre-Scaler P Coding CLK_SEL 0 Input XTAL P[1:0] xx 00 01 1 Input Frequency (MHz) PS[1:0] Input Clock Divider P Input Clock Prescaler PS Minimum Maximum 00 1 x1 10 40 01 1 x0.5 20 40 1x 1 x2 5 40 00 1 x1 10 120 01 1 x0.5 20 240 1x 1 x2 5 60 00 2 x1 20 240 01 2 x0.5 40 480 1x 2 x2 10 120 00 4 x1 40 480 01 4 x0.5 80 800 1x 4 x2 20 240 00 5 x1 50 600 01 5 x0.5 100 800 1x 5 x2 25 300 CLK 10 11 IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 7 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet Table 3F. PLL Post Divider N Coding Register Bit Output Frequency Range Nn[6:0] Output Divider N 000000X 2 0000010 2 955 1250 0000011 3 636.67 833.33 0000100 4 477.5 625 0000101 5 382 500 000011X 6 318.33 416.67 000100X 8 238.75 312.5 000101X 10 191 250 000110X 12 159.1667 208.33 000111X 14 136.4286 178.57 001000X 16 119.375 156.25 ... N (even integer) (1910 ÷ N) (2500 ÷ N) 111101X 124 15.40 20.16 111111X 126 15.16 19.84 fOUT_MIN (MHz) fOUT_MAX (MHz) Do Not Use NOTE: X denotes “don’t care”. Table 3G. FemtoClock NG PLL Bandwidth Coding Register Bit Feedback Divider Value Range CPn1 CPn0 Minimum Maximum 0 0 16 48 0 1 48 100 1 0 100 250 1 1 192 250 NOTE: FemtoClock NG PLL stability is only guaranteed over the feedback divider ranges listed is Table 3G. IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 8 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet Power-up Default Configuration Description The IDT8T49N008I supports a variety of options such as different output styles, number of programmed default frequencies, output enable and operating temperature range. The device options and default frequencies must be specified at the time of order and are programmed by IDT prior to shipment. The document, Programmable FemtoClock® NG Product Ordering Guide specifies the available order codes, including the device options and default frequency configurations. Example part number: 8T49N004A-007NLGI, specifies a quad frequency clock generator with default frequencies of 106.25MHz, 133.333MHz, 156.25MHz and 156.25MHz, with four LVDS outputs that are enabled after power-up, specified over the industrial temperature range and housed in a lead-free (6/6 RoHS) VFQFN package. Other order codes with respective programmed frequencies are available from IDT upon request. After power-up changes to the output frequencies are controlled by FSEL[1:0] or the I2C interface. Changes to the output styles and states of outputs (enabled or disabled) can also be controlled with the I2C interface after power up. Table 3H. Power-up Default Settings FSEL1 FSEL0 Frequency PLL State (On or Bypass) Output State (Active or High Impedance) Output Style (LVDS or LVPECL) 0 (default) 0 (default) Frequency 0 PLL State 0 Output State 0 Output Style 0 0 1 Frequency 1 PLL State 1 Output State 1 Output Style 1 1 0 Frequency 2 PLL State 2 Output State 2 Output Style 2 1 1 Frequency 3 PLL State 3 Output State 3 Output Style 3 Serial Interface Configuration Description The IDT8T49N008I has an I2C-compatible configuration interface to access any of the internal registers (Table 3B) for frequency and PLL parameter programming. The IDT849N008I acts as a slave device on the I2C bus and has the address 0b110111x, where x is set by the value on the ADDR_SEL input (see Tables 3I and 3J). The interface accepts byte-oriented block write and block read operations. An address byte (P) specifies the register address (Table 3B) as the byte position of the first register to write or read. Data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first, see Table 3K, 3L). Read and write block transfers can be stopped after any complete byte transfer. It is recommended to terminate the I2C read or write transfer after accessing byte #23 by sending a stop command. For full electrical I2C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal pull-up resistors have a size of 50k typical. Table 3I. I2C Device Slave Address ADDR_SEL = 0 (default) 1 1 0 1 1 1 0 R/W Table 3J. I2C Device Slave Address ADDR_SEL = 1 1 1 0 1 1 1 1 R/W Table 3K. Block Write Operation Bit Description 1 2:8 9 10 11:18 19 20:27 28 29-36 37 ... ... ... START Slave Address W (0) ACK Address Byte P ACK Data Byte (P) ACK Data Byte (P+1) ACK Data Byte ... ACK STOP 1 7 1 1 8 1 8 1 8 1 8 1 1 Length (bits) Table 3L. Block Read Operation Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39-46 47 ... ... ... START Slave Address W (0) A C K Address byte P A C K Repeated START Slave address R (1) A C K Data Byte (P) A C K Data Byte (P+1) A C K Data Byte ... A C K STOP 1 7 1 1 8 1 1 7 1 1 8 1 8 1 8 1 1 Description Length (bits) IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 9 ©2014 Integrated Device Technology, Inc. IDT8T49N008I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 3.63V Inputs, VI XTAL_IN Other Input 0V to 2V -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Outputs, IO (SDATA) 10mA Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 32.4C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VCC Core Supply Voltage VCCA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VCC – 0.32 3.3 VCC V VCCO Output Supply Voltage 3.135 3.3 3.465 V ICCA Analog Supply Current 32 mA IEE Power Supply Current LVPECL 225 mA ICC Power Supply Current LVDS 125 mA ICCO Output Supply Current LVDS 162 mA Table 4B. Power Supply DC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VCC Core Supply Voltage VCCA Minimum Typical Maximum Units 2.375 2.5 2.625 V Analog Supply Voltage VCC – 0.28 2.5 VCC V VCCO Output Supply Voltage 2.375 2.5 2.625 V ICCA Analog Supply Current 28 mA IEE Power Supply Current LVPECL 216 mA ICC Power Supply Current LVDS 122 mA ICCO Output Supply Current LVDS 160 mA IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 Test Conditions 10 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage Maximum Units IIH IIL Input Low Current VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 Minimum VCC = 3.3V 2 VCC + 0.3 V VCC = 2.5V 1.7 VCC + 0.3 V VCC = 3.3V -0.3 0.8 V VCC = 2.5V -0.3 0.7 V VCC = 3.3V or 2.5V 0.5 V SCLK, SDATA VCC = VIN = 3.465V or 2.625V 5 µA FSEL[1:0], CLK_SEL, ADDR_SEL VCC = VIN = 3.465V or 2.625V 150 µA SCLK, SDATA, FSEL[1:0], CLK_SEL, ADDR_SEL SCLK, SDATA, CLK_SEL, ADDR_SEL FSEL[1:0], Input High Current Test Conditions Typical SCLK, SDATA VCC = 3.465V or 2.625V, VIN = 0V -150 µA FSEL[1:0], CLK_SEL, ADDR_SEL VCC = 3.465V or 2.625V, VIN = 0V -5 µA LOCK VCC = 3.465V 2.6 V LOCK VCC = 2.625V 1.8 V LOCK VCC = 3.465V or 2.625V 0.5 V NOTE 1: Output terminated with 50 to VCCO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams. Table 4D. Differential DC Characteristics, VCC = VCCO = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1 VEE VCC – 0.85 V Maximum Units CLK, nCLK Minimum Typical VCC = VIN = 3.465V or 2.625V Maximum Units 150 µA nCLK VCC = 3.465V or 2.625V, VIN = 0V -150 µA CLK VCC = 3.465V or 2.625V, VIN = 0V -5 µA NOTE 1: Common mode input voltage is at the cross point. Table 4E. LVPECL DC Characteristics, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical VOH Output High Voltage; NOTE 1 VCC – 1.1 VCCO – 0.75 V VOL Output Low Voltage; NOTE 1 VCC – 2.0 VCCO – 1.6 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs termination with 50 to VCC – 2V. IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 11 ©2014 Integrated Device Technology, Inc. IDT8T49N008I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS Table 4F. LVPECL DC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCC – 1.2 VCCO – 0.75 V VCC – 2.0 VCC – 1.5 V 0.5 1.0 V NOTE 1: Outputs termination with 50 to VCC – 2V. Table 4G. LVDS DC Characteristics, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 247 345 454 mV 50 mV 1.375 V 50 mV 1.15 1.25 Table 4H. LVDS DC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 230 340 454 mV 50 mV 1.375 V 50 mV Maximum Units 1.15 1.25 Table 5. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental Frequency 10 40 MHz Load Capacitance (CL) 10 18 pF 50  Equivalent Series Resistance (ESR) IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 12 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet AC Electrical Characteristics Table 6A. PCI Express Jitter Specifications, VCC = VCCO = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Typical Maximum PCIe Industry Specification Units ƒ = 100MHz, 25MHz Crystal Input Evaluation Band: 0Hz - Nyquist (clock frequency/2) 8.3 13.2 86 ps tREFCLK_HF_RMS Phase Jitter RMS; NOTE 2, 4 (PCIe Gen 2) ƒ = 100MHz, 25MHz Crystal Input High Band: 1.5MHz - Nyquist (clock frequency/2) 0.78 1.35 3.1 ps tREFCLK_LF_RMS (PCIe Gen 2) Phase Jitter RMS; NOTE 2, 4 ƒ = 100MHz, 25MHz Crystal Input Low Band: 10kHz - 1.5MHz 0.05 0.10 3.0 ps tREFCLK_RMS (PCIe Gen 3) Phase Jitter RMS; NOTE 3, 4 ƒ = 100MHz, 25MHz Crystal Input Evaluation Band: 0Hz - Nyquist (clock frequency/2) 0.175 0.34 0.8 ps Symbol Parameter tj (PCIe Gen 1) Phase Jitter Peak-to-Peak; NOTE 1, 4 Test Conditions Minimum NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet. NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification. NOTE 4: This parameter is guaranteed by characterization. Not tested in production. IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 13 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet Table 6B. AC Characteristics, VCC = VCCO = 3.3V ± 5% or 2.5V ± 5% VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions fDIFF_IN Differential Input Frequency fVCO VCO Frequency tjit(Ø) RMS Phase Jitter, Random; NOTE 1 Minimum Typical Maximum Units 10 312.5 MHz 1910 2500 MHz 25MHz Crystal, fOUT = 100MHz, Integration Range: 12kHz – 20MHz 258 332 fs 25MHz Crystal, fOUT = 125MHz, Integration Range: 12kHz – 20MHz 220 291 fs 25MHz Crystal, fOUT = 125MHz, Integration Range: 10kHz – 1MHz 164 232 fs 25MHz Crystal, fOUT = 156.25MHz, Integration Range: 12kHz – 20MHz 228 306 fs 25MHz Crystal, fOUT = 156.25MHz, Integration Range: 10kHz – 1MHz 175 234 fs 25MHz Crystal, fOUT = 250MHz, Integration Range: 12kHz – 20MHz 212 292 fs 30.72MHz Crystal, fOUT = 491.52MHz, Integration Range: 12kHz – 20MHz 213 299 fs 19.44MHz Crystal, fOUT = 622.08MHz, Integration Range: 12kHz – 20MHz 280 386 fs tsk(o) Output Skew; NOTE 2, 3 LVPECL Outputs LVDS_SEL = 0 50 ps LVDS Outputs LVDS_SEL = 1 50 ps tR / tF Output Rise/Fall Time LVPECL Outputs 20% - 80%, LVDS_SEL = 0 100 400 ps LVDS Outputs 20% - 80%, LVDS_SEL = 1 100 400 ps N > 3 Output Divider; LVDS_SEL = 0 or 1 47 53 % N  3 Output Divider; LVDS_SEL = 0 or 1 42 58 % odc Output Duty Cycle tLOCK PLL Lock Time; NOTE 3, 4 LOCK Output 20 ms tTRANSITION Transition Time; NOTE 3, 4 LOCK Output 20 ms NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Refer to Phase Noise Plots. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Refer to tLOCK and tTRANSITION in Parameter Measurement Information. IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 14 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet Noise Power (dBc/Hz) Typical Phase Noise at 100MHz (3.3V) Offset Frequency (Hz) Noise Power (dBc/Hz) Typical Phase Noise at 125MHz (3.3V) Offset Frequency (Hz) IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 15 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet Noise Power (dBc/Hz) Typical Phase Noise at 156.25MHz (3.3V) Offset Frequency (Hz) IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 16 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet Parameter Measurement Information 2V 2V 2V 2V VCC, VCCO VCC, VCCO VCCA -1.3V ± 0.165V VCCA -0.5V ± 0.125V 2.5V LVPECL Output Load AC Test Circuit 3.3V LVPECL Output Load AC Test Circuit SCOPE 3.3V ±5% VCC, VCCO 2.5V±5% POWER SUPPLY + Float GND – VCCA VCC, VCCO V CCA Qx nQx 2.5V LVDS Output Load AC Test Circuit 3.3V LVDS Output Load AC Test Circuit VCC nCLK CLK VEE RMS Phase Jitter Differential Input Levels IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 17 ©2014 Integrated Device Technology, Inc. IDT8T49N008I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS Parameter Measurement Information, continued nQ[0:7] nQx Q[0:7] Qx nQy Qy Output Duty Cycle/Pulse Width/Period Output Skew nQ[0:7] nQ[0:7] 80% 80% VOD Q[0:7] Q[0:7] 20% 20% tF tR LVPECL Output Rise/Fall Time LVDS Output Rise/Fall Time Offset Voltage Setup Differential Output Voltage Setup IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 18 ©2014 Integrated Device Technology, Inc. IDT8T49N008I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS Parameter Measurement Information, continued Lock Time & Transition Time Applications Information Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVPECL Outputs All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVPECL output pairs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CLK/nCLK Inputs LVDS Outputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 19 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage V1 = VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1 in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. The values below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. VCC VCC VCC VCC R3 100 Ro RS R1 1K Zo = 50 Ohm + Driver V1 Ro + Rs = Zo R4 100 Receiv er - C1 0.1uF R2 1K Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 20 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 2A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This VCC can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 2B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. XTAL_OUT R1 100 Ro Rs C1 Zo = 50 ohms XTAL_IN R2 100 Zo = Ro + Rs .1uf LVCMOS Driver Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface XTAL_OUT C2 Zo = 50 ohms XTAL_IN .1uf Zo = 50 ohms LVPECL Driver R1 50 R2 50 R3 50 Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 21 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet 3.3V Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 3.3V 3.3V 3.3V 3.3V 3.3V Zo = 50Ω CLK CLK Zo = 50Ω nCLK R1 50Ω Differential Input LVPECL Differential Input LVPECL nCLK R2 50Ω R2 50Ω Figure 3A. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V 3.3V Zo = 50Ω *R3 CLK CLK R1 100Ω nCLK HCSL *R4 Zo = 50Ω Differential Input LVDS Figure 3C. CLK/nCLK Input Driven by a 3.3V HCSL Driver IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 nCLK Receiver Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver 22 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet 2.5V Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4D show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5V 2.5V 2.5V 2.5V 2.5V R3 250 R4 250 Zo = 50 CLK Zo = 50 CLK Zo = 50 nCLK Zo = 50 nCLK R1 62.5 R1 50 Differential Input LVPECL R2 62.5 Differential Input LVPECL R2 50 R3 18 Figure 4A. CLK/nCLK Input Driven by a 2.5V LVPECL Driver Figure 4B. CLK/nCLK Input Driven by a 2.5V LVPECL Driver 2.5V 2.5V 2.5V 2.5V *R3 33 Zo = 50 Zo = 50 CLK CLK R1 100 Zo = 50 nCLK HCSL *R4 33 R1 50 R2 50 Zo = 50 Differential Input LVDS nCLK Differential Input *Optional – R3 and R4 can be 0 Figure 4C. CLK/nCLK Input Driven by a 2.5V HCSL Driver IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 Figure 4D. CLK/nCLK Input Driven by a 2.5V LVDS Driver 23 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The LVDS Driver standard termination schematic as shown in Figure 5A can be used with either type of output structure. Figure 5B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. ZO  ZT LVDS Receiver ZT Figure 5A. Standard Termination LVDS Driver ZT 2 LVDS ZT Receiver 2 ZO  ZT C Figure 5B. Optional Termination Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 6A and 6B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 R3 125 3.3V R4 125 3.3V 3.3V Zo = 50 + _ LVPECL Input Zo = 50 R1 84 Figure 6A. 3.3V LVPECL Output Termination IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 R2 84 Figure 6B. 3.3V LVPECL Output Termination 24 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet Termination for 2.5V LVPECL Outputs level. The R3 in Figure 7B can be eliminated and the termination is shown in Figure 7C. Figure 7A and Figure 7B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground 2.5V VCCO = 2.5V 2.5V 2.5V VCCO = 2.5V R1 250 R3 250 50 + 50 + 50 – 50 2.5V LVPECL Driver – R1 50 2.5V LVPECL Driver R2 62.5 R2 50 R4 62.5 R3 18 Figure 7A. 2.5V LVPECL Driver Termination Example Figure 7B. 2.5V LVPECL Driver Termination Example 2.5V VCCO = 2.5V 50 + 50 – 2.5V LVPECL Driver R1 50 R2 50 Figure 7C. 2.5V LVPECL Driver Termination Example IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 25 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 8. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 8. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 26 ©2014 Integrated Device Technology, Inc. IDT8T49N008I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS Schematic Layout Figure 9 (next page) shows an example of IDT8T49N008I application schematic. The schematic focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uF capacitor in each power pin filter should be placed on the device side of the PCB and the other components can be placed on the opposite side. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. In this example the device is operated at VCC = VCCO = VCCA = 3.3V rather than 2.5V. The CLK, nCLK inputs are provided by a 3.3V LVPECL driver and depicted with a Y-termination rather than the standard four resistor VCC - 2V Thevinin termination for reasons of minimum termination power and layout simplicity. Three examples of PECL terminations are shown for the outputs to demonstrate mixing of PECL termination design options. The VCC and VCCO filters start to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. As with any high speed analog circuitry, the power supply pins are vulnerable to noise. To achieve optimum jitter performance, power supply isolation is required. The IDT8T49N006I provides separate power supplies to isolate from coupling into the internal PLL. IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 27 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet 3.3V U1 R1 4. 7K 17 20 16 39 AD D R _SE L FS EL1 FS EL0 C LK_S EL R2 4.7K 33 32 SC LK SD A TA 11 R6 330 36 AD D R _SE L FS E L1 FS E L0 C LK _SE L LO C K SD ATA SC LK Q0 nQ0 XTAL_I N Q1 nQ1 12 25MH z(12pf ) XTAL_OU T X1 C 18 9pF Q2 nQ2 Q3 nQ3 C 23 9pF Q4 nQ4 Zo = 50 Ohm Q5 nQ5 R 3 50 14 C LK 15 Zo = 50 Ohm nC LK R 4 50 Q6 nQ6 Q7 nQ7 P EC L D riv er LOC K 3. 3V 1 2 Q0_P Q0_N R7 133 R8 133 Z o = 50 Ohm 3 4 Q1_P Q1_N 6 7 Q2_P Q2_N 8 9 Q3_P Q3_N 30 29 Q4_P Q4_N 28 27 Q5_P Q5_N 25 24 Q6_P Q6_N 23 22 Q7_P Q7_N + Z o = 50 Ohm - R9 82. 5 R 10 82.5 Optional Four Resistor Thevinin Termination R5 50 19 VC C V C C _38 38 C 10 0. 1uF VC C _19 C 15 0. 1uF VC C A 35 VC C A C7 0. 1uF 5 26 VC C O C 17 0. 1uF Z o = 50 Ohm VC C VC C O VC C O VE E VE E VE E VE E VE E VE E VE E VE E epad + 10 13 18 21 31 34 37 40 Z o = 50 Ohm - R 13 50 R 14 50 41 R 15 50 C9 0. 1uF 3. 3V F B1 1 2 B LM18BB 221SN 1 For AC termination options consult the IDT Applications Note "Termination - 3.3V LVPECL" V C C _19 C 14 C6 0. 1uF 10uF Logic Control Input Examples 3. 3V F B2 1 2 B LM18BB 221SN 1 VC C _38 Set Logic Input to '1' VCC Set Logic Input to '0' VCC C 16 C 19 0. 1uF 10uF RU1 1K RU 2 N ot I ns tal l To Logic Input pins R 16 VC C A RD1 N ot Ins t all 10 To Logic Input pins RD 2 1K C8 10uF 3. 3V 1 FB 3 2 B LM18BB 221SN 1 C 22 0. 1uF VC C O C 21 10uF Figure 9. IDT8T49N008I Application Schematic IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 28 ©2014 Integrated Device Technology, Inc. IDT8T49N008I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: Ht  s  = H3  s    H1  s  – H2  s   The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: Y  s  = X  s   H3  s    H1  s  – H2  s   In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. PCIe Gen 2A Magnitude of Transfer Function PCI Express Common Clock Architecture For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is reported in peak-peak. PCIe Gen 2B Magnitude of Transfer Function For PCI Express Gen 3, one transfer function is defined and the evaluation is performed over the entire spectrum. The transfer function parameters are different from Gen 1 and the jitter result is reported in RMS. PCIe Gen 1 Magnitude of Transfer Function For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in RMS. The two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High Band). The plots show the individual transfer functions as well as the overall transfer function Ht. IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 PCIe Gen 3 Magnitude of Transfer Function For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements. 29 ©2014 Integrated Device Technology, Inc. IDT8T49N008I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS LVPECL Power Considerations This section provides information on power dissipation and junction temperature for the IDT8T49N008I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the IDT8T49N008I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 225mA = 779.625mW • Power (outputs)MAX = 31.55mW/Loaded Output pair If all outputs are loaded, the total power is 8 * 31.55mW = 252.4mW Total Power_MAX (3.465V, with all outputs switching) = 779.625W + 252.4mW = 1032.025W 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 32.4°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 1.032W * 32.4°C/W = 118.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance JA for 40-Lead VFQFN, Forced Convection JA by Velocity Meters per Second 0 1 3 Multi-Layer PCB, JEDEC Standard Test Boards 32.4°C/W 25.7°C/W 23.4°C/W IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 30 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 10. VCCO Q1 VOUT RL 50Ω VCCO - 2V Figure 10. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCC O – 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.75V (VCCO_MAX – VOH_MAX) = 0.75V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.6V (VCCO_MAX – VOL_MAX) = 1.6V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – 0.75V)/50] * 0.75V = 18.75mW Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – 1.6V)/50] * 1.6V = 12.80mW Total Power Dissipation per output pair = Pd_H + Pd_L = 31.55mW IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 31 ©2014 Integrated Device Technology, Inc. IDT8T49N008I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS LVDS Power Considerations This section provides information on power dissipation and junction temperature for the IDT8T49N008I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the IDT8T49N008I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V +5% = 3.465V, which gives worst case results. • Power (core)MAX = VCC_MAX * (ICC_MAX + ICCA_MAX) = 3.465V * (125mA + 32mA) = 544.005mW • Power (outputs)MAX = VCCO_MAX * ICCO_MAX = 3.465V * 162mA = 561.33mW Total Power_MAX = 544.005mW + 561.33mW = 1105.335mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 32.4°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 1.105W * 32.4°C/W = 120.8°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 8. Thermal Resistance JA for 40-Lead VFQFN, Forced Convection JA by Velocity Meters per Second 0 1 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 32.4°C/W 25.7°C/W 23.4°C/W IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 32 ©2014 Integrated Device Technology, Inc. IDT8T49N008I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS Reliability Information Table 9. JA vs. Air Flow Table for a 40-Lead VFQFN JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 32.4°C/W 25.7°C/W 23.4°C/W Transistor Count The transistor count for IDT8T49N008I is: 26,856 IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 33 ©2014 Integrated Device Technology, Inc. IDT8T49N008I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS 40-Lead VFQFN Package Outline and Package Dimensions IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 34 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet 40-Lead VFQFN Package Outline and Package Dimensions, continued 40-Lead VFQFN, D2/E2 EPAD Dimensions: 4.65mm x 4.65mm IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 35 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet Ordering Information Table 10. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 8T49N008A-dddNLGI IDT8T49N008A-dddNLGI “Lead-Free” 40-Lead VFQFN Tray -40C to 85C 8T49N008A-dddNLGI8 IDT8T49N008A-dddNLGI “Lead-Free” 40-Lead VFQFN Tape & Reel -40C to 85C ® NOTE: For the specific -ddd order codes, refer to the Programmable FemtoClock NG Product Ordering Guide document. IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 36 ©2014 Integrated Device Technology, Inc. PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS IDT8T49N008I Data Sheet Revision History Sheet Rev Table A A T10 Page Pin Assignment - repositioned pin numbers (11-20). 4/18/12 36 Changed footer part/order number from IDT8T49N008BNLGI to IDT8T49N008ANLGI. Ordering Information Table - changed Shipping Packaging from 1000 Tape & Reel to 5000 Tape & Reel. 4/23/12 Changed name of the IDT8T49N00xI Programmable FemtoClock® NG Product Ordering Information document to Programmable FemtoClock® Ordering Product Information Deleted quantity from Tape & Reel, Deleted Lead Free note. 8/21/13 Changed title to Programmable FemtoClock® NG LVPECL/LVDS Clock Generator with 8-Outputs. Changed text from ‘Programmable FemtoClock® Ordering Product Information’ to ‘Programmable FemtoClock® NG Product Ordering Guide’. Changed Note from ‘Programmable FemtoClock® Ordering Product Information’ to ‘Programmable FemtoClock® NG Product Ordering Guide’. 9/26/13 Changed the min load capacitance from 12pF to 10pF 10/15/13 Corrected part number in the footer pages from IDT8T49N00BNLGI to IDT8T49N00ANLGI 2/13/14 11, 38 38 1 11 A A A Date 1 A T10 Description of Change T10 38 T5 14 IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 37 ©2014 Integrated Device Technology, Inc. IDT8T49N008I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support Sales netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2014. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.