FemtoClock® NG Octal Universal
Frequency Translator
8T49N287
Datasheet
Description
Features
The 8T49N287 has two independent, fractional-feedback PLLs that
can be used as jitter attenuators and frequency translators. It is
equipped with six integer and two fractional output dividers, allowing
the generation of up to 8 different output frequencies, ranging from
8kHz to 1GHz. Four of these frequencies are completely independent
of each other and the inputs. The other four are related frequencies.
The eight outputs may select among LVPECL, LVDS, HCSL, or
LVCMOS output levels.
•
Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
•
•
•
•
95nF,
otherwise set to 1.
0 = 1ppm accuracy
1 = 16ppm accuracy
DBITM_0
R/W
0b
Digital Lock Manual Override Setting for Analog PLL0:
0 = Automatic Mode
1 = Manual Mode
VCOMAN_0
R/W
1b
Manual Lock Mode VCO Selection Setting for Analog PLL0:
0 = VCO2
1 = VCO1
DBIT1_0[4:0]
R/W
01011b
©2021 Renesas Electronics Corporation.
Manual Mode Digital Lock Control Setting for VCO1 in Analog PLL0.
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8T49N287 Datasheet
Analog PLL0 Control Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
DBIT2_0[4:0]
R/W
00000b
SYN_MODE0
R/W
0b
Rsvd
R/W
-
Description
Manual Mode Digital Lock Control Setting for VCO2 in Analog PLL0.
Frequency Synthesizer Mode Control for PLL0:
0 = PLL0 jitter attenuates and translates one or more input references
1 = PLL0 synthesizes output frequencies using only the crystal as a reference
Note that the STATE0[1:0] field in the Digital PLL0 Control Register must be set to
Force Freerun state.
Reserved. Always write 0 to this bit location. Read values are not defined.
Table 6O. Analog PLL1 Control Register Bit Field Locations and Descriptions
Please contact Renesas through one of the methods listed on the last page of this datasheet for details on how to set these fields for a particular
user configuration.
Analog PLL1 Control Register Block Field Locations
Address (Hex)
D7
D6
00B0
D5
CPSET_1[2:0]
00B1
00B2
D4
Rsvd
D2
RS_1[1:0]
SYN_MOD
E1
Rsvd
00B3
D3
VCOMAN_1
D1
CP_1[1:0]
Rsvd
DLCNT_1
D0
WPOST_1
DBITM_1
DBIT1_1[4:0]
Rsvd
DBIT2_1[4:0]
Analog PLL1 Control Register Block Field Descriptions
Bit Field Name
CPSET_1[2:0]
RS_1[1:0]
Field Type
Default Value
R/W
R/W
Description
100b
Charge Pump Current Setting for Analog PLL1:
000 = 110µA
001 = 220µA
010 = 330µA
011 = 440µA
100 = 550µA
101 = 660µA
110 = 770µA
111 = 880µA
01b
Internal Loop Filter Series Resistor Setting for Analog PLL1:
00 = 330
01 = 640
10 = 1.2k
11 = 1.79k
CP_1[1:0]
R/W
01b
Internal Loop Filter Parallel Capacitor Setting for Analog PLL1:
00 = 40pF
01 = 80pF
10 = 140pF
11 = 200pF
WPOST_1
R/W
1b
Internal Loop Filter 2nd-Pole Setting for Analog PLL1:
0 = Rpost = 497, Cpost = 40pF
1 = Rpost = 1.58k, Cpost = 40pF
DLCNT_1
R/W
1b
Digital Lock Count Setting for Analog PLL1:
Value should be set to 0 (1ppm accuracy) if external capacitor value is >95nF,
otherwise set to 1.
0 = 1ppm accuracy
1 = 16ppm accuracy
DBITM_1
R/W
0b
Digital Lock Manual Override Setting for Analog PLL1:
0 = Automatic Mode
1 = Manual Mode
©2021 Renesas Electronics Corporation.
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8T49N287 Datasheet
Analog PLL1 Control Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
VCOMAN_1
R/W
1b
DBIT1_1[4:0]
R/W
01011b
Manual Mode Digital Lock Control Setting for VCO1 in Analog PLL1.
DBIT2_1[4:0]
R/W
00000b
Manual Mode Digital Lock Control Setting for VCO2 in Analog PLL1.
SYN_MODE1
R/W
0b
Rsvd
R/W
-
Description
Manual Lock Mode VCO Selection Setting for Analog PLL1:
0 = VCO2
1 = VCO1
Frequency Synthesizer Mode Control for PLL1:
0 = PLL1 jitter attenuates and translates one or more input references
1 = PLL1 synthesizes output frequencies using only the crystal as a reference
Note that the STATE1[1:0] field in the Digital PLL1 Control Register must be set to
Force Freerun state.
Reserved. Always write 0 to this bit location. Read values are not defined.
Table 6P. Power Down Control Register Bit Field Locations and Descriptions
Power Down Control Register Block Field Locations
Address (Hex)
D7
D6
D5
00B4
D3
D2
D1
Rsvd
00B5
1
Rsvd
Q7_DIS
00B8
1
PLL1_DIS
Q6_DIS
Q5_DIS
CLK1_DIS
CLK0_DIS
Rsvd
Q4_DIS
Rsvd
D0
DBL_DIS
Rsvd
00B6
00B7
D4
Q3_DIS
Q2_DIS
Q1_DIS
Q0_DIS
DPLL1_DIS
DPLL0_DIS
CALRST1
CALRST0
Power Down Control Register Block Field Descriptions
Bit Field Name
Field
Type
Default Value
Description
DBL_DIS
R/W
0b
Controls whether Crystal Input Frequency is Doubled before Being used in PLL0 or PLL1:
0 = 2x Actual Crystal Frequency Used
1 = Actual Crystal Frequency Used
CLKm_DIS
R/W
0b
Disable Control for Input Reference m:
0 = Input Reference m is Enabled
1 = Input Reference m is Disabled
PLL1_DIS
R/W
0b
Disable Control for Analog PLL1:
0 = PLL1 Enabled
1 = Analog PLL1 Disabled
Qm_DIS
R/W
0b
Disable Control for Output Qm, nQm:
0 = Output Qm, nQm functions normally
1 = All logic associated with Output Qm, nQm is Disabled & Driver in High-Impedance
state
DPLLm_DIS
R/W
0b
Disable Control for Digital PLLm:
0 = Digital PLLm Enabled
1 = Digital PLLm Disabled
CALRSTm
R/W
0b
Reset Calibration Logic for APLLm:
0 = Calibration Logic for APLLm Enabled
1 = Calibration Logic for APLLm Disabled
Rsvd
R/W
-
©2021 Renesas Electronics Corporation.
Reserved. Always write 0 to this bit location. Read values are not defined.
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8T49N287 Datasheet
Table 6Q. Input Monitor Control Register Bit Field Locations and Descriptions
Input Monitor Control Register Block Field Locations
Address (Hex)
D7
D6
D5
00B9
D4
D3
D2
D1
Rsvd
00BA
LOS_0[15:8]
00BB
LOS_0[7:0]
00BC
Rsvd
LOS_1[16]
00BD
LOS_1[15:8]
00BE
LOS_1[7:0]
00BF
Rsvd
00C0
D0
LOS_0[16]
Rsvd
Rsvd
00C1
Rsvd
00C2
Rsvd
Rsvd
00C3
Rsvd
00C4
Rsvd
00C5
Rsvd
00C6
Rsvd
Input Monitor Control Register Block Field Descriptions
Bit Field Name
Field
Type
Default Value
LOS_m[16:0]
R/W
1FFFFh
Rsvd
R/W
-
Description
Number of Input Monitoring clock periods before Input Reference m is considered to be
missed (soft alarm). Minimum setting is 3.
Reserved. Always write 0 to this bit location. Read values are not defined.
Table 6R. Interrupt Enable Control Register Bit Field Locations and Descriptions
Interrupt Enable Control Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
00C7
LOL1_EN
LOL0_EN
HOLD1_EN
HOLD0_EN
Rsvd
Rsvd
LOS1_EN
LOS0_EN
Bit Field Name
Field Type
Default Value
LOLm_EN
R/W
0b
Interrupt Enable Control for Loss-of-Lock Interrupt Status Bit for PLLm:
0 = LOLm_INT register bit will not affect status of nINT output signal
1 = LOLm_INT register bit will affect status of nINT output signal
HOLDm_EN
R/W
0b
Interrupt Enable Control for Holdover Interrupt Status Bit for PLLm:
0 = HOLDm_INT register bit will not affect status of nINT output signal
1 = HOLDm_INT register bit will affect status of nINT output signal
LOSm_EN
R/W
0b
Interrupt Enable Control for Loss-of-Signal Interrupt Status Bit for Input Reference m:
0 = LOSm_INT register bit will not affect status of nINT output signal
1 = LOSm_INT register bit will affect status of nINT output signal
Interrupt Enable Control Register Block Field Descriptions
©2021 Renesas Electronics Corporation.
Description
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8T49N287 Datasheet
Table 6S. Digital Phase Detector Control Register Bit Field Locations and Descriptions
Digital Phase Detector Control Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
00C8
D3
D2
D1
D0
Rsvd
1
Rsvd
Rsvd
Rsvd
1
Rsvd
Rsvd
27h
00C9
Rsvd
1
00CA
27h
00CB
Rsvd
1
Digital Phase Detector Control Register Block Field Descriptions
Bit Field Name
Field Type
Rsvd
R/W
Default Value Description
-
Reserved. Always write 0 to this bit location. Read values are not defined.
Table 6T. Interrupt Status Register Bit Field Locations and Descriptions
This register contains “sticky” bits for tracking the status of the various alarms. Whenever an alarm occurs, the appropriate Interrupt Status bit
will be set. The Interrupt Status bit will remain asserted even after the original alarm goes away. The Interrupt Status bits remain asserted until
explicitly cleared by a write of a ‘1’ to the bit over the serial port. This type of functionality is referred to as Read / Write-1-to-Clear (R/W1C).
Interrupt Status Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
0200
LOL1_INT
LOL0_INT
HOLD1_INT
HOLD0_INT
Rsvd
Rsvd
LOS1_INT
LOS0_INT
0201
Rsvd
0202
Rsvd
0203
Rsvd
Interrupt Status Register Block Field Descriptions
Bit Field Name
LOLm_INT
HOLDm_INT
Field Type
Default Value
R/W1C
R/W1C
0b
Interrupt Status Bit for Loss-of-Lock on PLLm:
0 = No Loss-of-Lock alarm flag on PLLm has occurred since the last time this register
bit was cleared
1 = At least one Loss-of-Lock alarm flag on PLLm has occurred since the last time this
register bit was cleared
0b
Interrupt Status Bit for Holdover on PLLm:
0 = No Holdover alarm flag on PLLm has occurred since the last time this register bit
was cleared
1 = At least one Holdover alarm flag on PLLm has occurred since the last time this
register bit was cleared
Interrupt Status Bit for Loss-of-Signal on Input Reference m:
0 = No Loss-of-Signal alarm flag on Input Reference m has occurred since the last time
this register bit was cleared
1 = At least one Loss-of-Signal alarm flag on Input Reference m has occurred since the
last time this register bit was cleared
LOSm_INT
R/W1C
0b
Rsvd
R/W
-
©2021 Renesas Electronics Corporation.
Description
Reserved. Always write 0 to this bit location. Read values are not defined.
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8T49N287 Datasheet
Table 6U. Output Phase Adjustment Status Register Bit Field Locations and Descriptions
Output Phase Adjustment Status Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
0204
PA_BUSY7
PA_BUSY6
PA_BUSY5
PA_BUSY4
PA_BUSY3
PA_BUSY2
PA_BUSY1
PA_BUSY0
Output Phase Adjustment Status Register Block Field Descriptions
Bit Field Name
PA_BUSYm
Field Type
Default Value
R/O
-
Description
Phase Adjustment Event Status for output Qm, nQm:
0 = No phase adjustment is currently in progress on output Qm, nQm
1 = Phase adjustment still in progress on output Qm, nQm. Do not initiate any new
phase adjustment at this time
The following register is included for debug purposes only. It shows the actual digital PLL0 state directly. This means that the bits may change
rapidly as the DPLL operates. The fields in this register do not represent a “snapshot” in time, so they may be inconsistent with one another if
the DPLL is rapidly changing at the time of reading. Fast changes in the status of the PLL cannot be captured by polling these bits, in which
case, Renesas recommends using the Sticky Bits interrupts and GPIOs.
Table 6V. Digital PLL0 Status Register Bit Field Locations and Descriptions
Digital PLL0 Status Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
0205
Rsvd
EXTLOS0
NO_REF0
0206
Rsvd
PLL0LCK
Rsvd
0207
D2
D0
CURR_REF0[2:0]
Rsvd
Rsvd
SM_STS0[1:0]
Rsvd
0208
Rsvd
0209
Rsvd
020A
D1
Rsvd
Rsvd
020B
Rsvd
020C
Rsvd
020D
Rsvd
020E
Rsvd
Digital PLL0 Status Register Block Field Descriptions
Bit Field Name
Field
Type
EXTLOS0
R/O
-
External Loopback signal lost for PLL0:
0 = PLL0 has a valid feedback reference signal
1 = PLL0 has lost the external feedback reference signal and is no longer locked
NO_REF0
R/O
-
Valid Reference Status for Digital PLL0:
0 = At least one valid Input Reference is present
1 = No valid Input References present
-
Currently Selected Reference Status for Digital PLL0:
000 - 011 = No reference currently selected
100 = Input Reference 0 (CLK0, nCLK0) selected
101 = Input Reference 1 (CLK1, nCLK1) selected
110 = Reserved
111 = Reserved
CURR_REF0[2:0]
R/O
Default Value Description
©2021 Renesas Electronics Corporation.
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8T49N287 Datasheet
Digital PLL0 Status Register Block Field Descriptions
Bit Field Name
Field
Type
PLL0LCK
R/O
Default Value Description
-
Digital PLL0 phase error value is less than lock criteria. Not asserted if PLL0 in Synthesizer
Mode.
SM_STS0[1:0]
R/O
-
Current State of Digital PLL0:
00 = Reserved
01 = Freerun
10 = Normal
11 = Holdover
Rsvd
R/W
-
Reserved. Always write 0 to this bit location. Read values are not defined.
The following register is included for debug purposes only. It shows the actual digital PLL1 state directly. This means that the bits may change
rapidly as the DPLL operates. The fields in this register do not represent a “snapshot” in time, so they may be inconsistent with one another if
the DPLL is rapidly changing at the time of reading. Fast changes in the status of the PLL cannot be captured by polling these bits, in which
case, Renesas recommends using the Sticky Bits interrupts and GPIOs.
Table 6W. Digital PLL1 Status Register Bit Field Locations and Descriptions
Digital PLL1 Status Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
020F
Rsvd
EXTLOS1
NO_REF1
0210
Rsvd
PLL1LCK
Rsvd
0211
D2
D0
CURR_REF1[2:0]
Rsvd
Rsvd
0212
D1
SM_STS1[1:0]
Rsvd
Rsvd
0213
Rsvd
0214
Rsvd
Rsvd
0215
Rsvd
0216
Rsvd
0217
Rsvd
0218
Rsvd
Digital PLL1 Status Register Block Field Descriptions
Bit Field Name
Field
Type
Default Value
EXTLOS1
R/O
-
External Loopback signal lost for PLL1:
0 = PLL1 has a valid feedback reference signal
1 = PLL1 has lost the external feedback reference signal and is no longer locked
NO_REF1
R/O
-
Valid Reference Status for Digital PLL1:
0 = At least one valid Input Reference is present
1 = No valid Input References present
-
Currently Selected Reference Status for Digital PLL1:
000 - 011 = No reference currently selected
100 = Input Reference 0 (CLK0, nCLK0) selected
101 = Input Reference 1 (CLK1, nCLK1) selected
110 = Reserved
111 = Reserved
CURR_REF1[2:0]
R/O
©2021 Renesas Electronics Corporation.
Description
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8T49N287 Datasheet
Digital PLL1 Status Register Block Field Descriptions
Bit Field Name
Field
Type
Default Value
PLL1LCK
R/O
-
Digital PLL1 phase error value is less than the LOCK window setting. Not asserted if PLL1
in Synthesizer Mode.
Description
SM_STS1[1:0]
R/O
-
Current State of Digital PLL1:
00 = Reserved
01 = Freerun
10 = Normal
11 = Holdover
Rsvd
R/W
-
Reserved. Always write 0 to this bit location. Read values are not defined.
Table 6X. General Purpose Input Status Register Bit Field Locations and Descriptions
Global Interrupt Status Register Block Field Locations
Address (Hex)
D7
D6
0219
D5
D4
Rsvd
D3
D2
D1
D0
GPI[3]
GPI[2]
GPI[1]
GPI[0]
General Purpose Input Status Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
GPI[3:0]
R/O
-
Description
Shows current values on GPIO[3:0] pins that are configured as General-Purpose Inputs.
Table 6Y. Global Interrupt Status Register Bit Field Locations and Descriptions
Global Interrupt Status Register Block Field Locations
Address (Hex)
D7
D6
021A
D5
D4
D3
D2
Rsvd
D1
D0
Rsvd
021B
INT
Rsvd
021C
Rsvd
CALI_DBIT0[5:0]
021D
Rsvd
CALI_DBIT1[5:0]
021E
Rsvd
Rsvd
Rsvd
Rsvd
nEEP_CRC
Rsvd
Rsvd
BOOTFAIL
Rsvd
Rsvd
EEPDONE
021F
Rsvd
Bit Field Name
Field Type
INT
R/O
-
Device Interrupt Status:
0 = No Interrupt Status bits that are enabled are asserted (nINT pin released)
1 = At least one Interrupt Status bit that is enabled is asserted (nINT pin asserted low)
BOOTFAIL
R/O
-
Reading of Serial EEPROM failed. Once set this bit is only cleared by reset.
Global Interrupt Status Register Block Field Descriptions
Default Value Description
nEEP_CRC
R/O
-
EEPROM CRC Error (Active Low):
0 = EEPROM was detected and read, but CRC check failed - please reset the device
via the nRST pin to retry (serial port is locked)
1 = No EEPROM CRC Error
EEPDONE
R/O
-
Serial EEPROM Read cycle has completed. Once set this bit is only cleared by reset.
CALI_DBITn[5:0]
R/O
-
Indicates current digital bit setting for PLLn.
Rsvd
R/W
-
Reserved. Always write 0 to this bit location. Read values are not defined.
©2021 Renesas Electronics Corporation.
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8T49N287 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
3.63V
Inputs, VI
OSCI
Other Input
0V to 2V
-0.5V to VCC + 0.5V
Outputs, VO (Q[0:7], nQ[0:7])
-0.5V to VCCOX + 0.5V
Outputs, VO (GPIO[0:3], SDATA, SCLK, nINT)
-0.5V to VCC + 0.5V
Outputs, IO (Q[0:7], nQ[0:7])
Continuous Current
Surge Current
40mA
65mA
Outputs, IO (GPIO[0:3], SDATA, SCLK, nINT)
Continuous Current
Surge Current
8mA
13mA
Junction Temperature, TJ
125C
Storage Temperature, TSTG
-65C to 150C
NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7.
Supply Voltage Characteristics
Table 7A. Power Supply Characteristics, VCC = 3.3V ±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Analog Supply Voltage
ICC
Core Supply Current;
NOTE 1
ICCA
Analog Supply Current;
NOTE 1
IEE
Power Supply Current;
NOTE 2
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VCC – 0.13
3.3
VCC
V
74
100
mA
PLL0 and PLL1 Enabled
206
265
mA
Analog PLL1, Digital PLL1, and
Calibration Logic for analog PLL1 Disabled
122
187
mA
Q[0:7] Configured for LVPECL Logic Levels,
Outputs Unloaded
562
735
mA
NOTE 1: ICC and ICCA are included in IEE when Q[0:7] configured for LVPECL logic levels.
NOTE 2: Internal dynamic switching current at maximum fOUT is included.
©2021 Renesas Electronics Corporation.
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8T49N287 Datasheet
Table 7B. Power Supply Characteristics, VCC = 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VCC
Core Supply Voltage
VCCA
Analog Supply Voltage
ICC
Core Supply Current;
NOTE 1
ICCA
Analog Supply Current;
NOTE 1
IEE
Power Supply Current;
NOTE 2
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
VCC – 0.13
2.5
VCC
V
72
95
mA
PLL0 and PLL1 Enabled
201
260
mA
Analog PLL1, Digital PLL1, and
Calibration Logic for analog PLL1 Disabled
119
182
mA
Q[0:7] Configured for LVPECL Logic Levels,
Outputs Unloaded
533
695
mA
NOTE 1: ICC and ICCA are included in IEE when Q[0:7] configured for LVPECL logic levels.
NOTE 2: Internal dynamic switching current at maximum fOUT is included.
Table 7C. Maximum Output Supply Current, VCC = 3.3V ±5% or 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C
Test
Conditions
VCCOx = 3.3V ±5%
VCCOx =
1.8V ±5%
VCCOx = 2.5V ±5%
LVPECL
LVDS
HCSL
LVCMOS
LVPECL
LVDS
HCSL
LVCMOS
LVCMOS
Units
Outputs
Unloaded
50
60
50
55
40
50
40
45
35
mA
Q1, nQ1 Output
Supply Current
Outputs
Unloaded
50
60
50
55
40
50
40
45
35
mA
ICCO2
Q2, nQ2 Output
Supply Current
Outputs
Unloaded
80
90
80
80
70
80
70
70
60
mA
ICCO3
Q3, nQ3 Output
Supply Current
Outputs
Unloaded
80
90
80
80
70
80
70
70
60
mA
ICCO4
Q4, nQ4 Output
Supply Current
Outputs
Unloaded
55
65
55
55
45
55
45
45
40
mA
ICCO5
Q5, nQ5 Output
Supply Current
Outputs
Unloaded
55
65
55
55
45
55
45
45
40
mA
ICCO6
Q6, nQ6 Output
Supply Current
Outputs
Unloaded
55
65
55
55
45
55
45
45
40
mA
ICCO7
Q7, nQ7 Output
Supply Current
Outputs
Unloaded
55
65
55
55
45
55
45
45
40
mA
Symbol
Parameter
ICCO0
Q0, nQ0 Output
Supply Current
ICCO1
NOTE: Internal dynamic switching current at maximum fOUT is included.
NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7.
©2021 Renesas Electronics Corporation.
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8T49N287 Datasheet
DC Electrical Characteristics
Table 8A. LVCMOS/LVTTL DC Characteristics, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input
High Current
IIL
VOH
VOL
Input
Low Current
Output
High Voltage
Output
Low Voltage
Test Conditions
Minimum
VCC = 3.3V
Typical
Maximum
Units
2
VCC +0.3
V
VCC = 2.5V
1.7
VCC +0.3
V
VCC = 3.3V
-0.3
0.8
V
VCC = 2.5V
-0.3
0.7
V
PLL_BYP, S_A0
VCC = VIN = 3.465V or 2.625V
150
μA
nRST, SDATA, SCLK
VCC = VIN = 3.465V or 2.625V
5
μA
GPIO[3:0]
VCC = VIN = 3.465V or 2.625V
1
mA
PLL_BYP, S_A0
VCC = 3.465V or 2.625V, VIN = 0V
-5
μA
nRST, SDATA, SCLK
VCC = 3.465V or 2.625V, VIN = 0V
-150
μA
GPIO[3:0]
VCC = 3.465V or 2.625V, VIN = 0V
-1
mA
nINT, SDATA,
SCLK; NOTE 1
VCC = 3.3V ±5%, IOH = -5μA
2.6
V
GPIO[3:0]
VCC = 3.3V ±5%, IOH = -50μA
2.6
V
nINT, SDATA,
SCLK; NOTE 1
VCC = 2.5V ±5%, IOH = -5μA
1.8
V
GPIO[3:0]
VCC = 2.5V ±5%, IOH = -50μA
1.8
V
nINT, SDATA,
SCLK; NOTE 1
VCC = 3.3V ±5% or 2.5V±5%, IOL = 5mA
0.5
V
GPIO[3:0]
VCC = 3.3V ±5% or 2.5V±5%, IOL = 5mA
0.5
V
NOTE 1: Use of external pull-up resistors is recommended.
Table 8B. Differential Input DC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
IIH
Input High Current
150
μA
IIL
Input Low Current
VPP
Peak-to-Peak Voltage; NOTE 1
0.15
1.3
V
VCMR
Common Mode Input Voltage;
NOTE 1, 2
VEE
VCC -1.2
V
CLKx,
nCLKx
VCC = VIN = 3.465V or 2.625V
CLKx
VCC = 3.465V or 2.625V, VIN = 0V
-5
μA
nCLKx
VCC = 3.465V or 2.625V, VIN = 0V
-150
μA
NOTE: CLKx denotes CLK0, CLK1. nCLKx denotes nCLK0, nCLK1.
NOTE 1: VIL should not be less than -0.3V. VIH should not be higher than VCC.
NOTE 2: Common mode voltage is defined as the cross-point.
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8T49N287 Datasheet
Table 8C. LVPECL DC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C
VCCOx = 3.3V±5%
Symbol
Parameter
Test Conditions
VOH
Output
High Voltage;
NOTE 1
Qx,
nQx
VOL
Output
Low Voltage;
NOTE 1
Qx,
nQx
Minimum
Typical
VCCOx = 2.5V±5%
Maximum
Minimum
VCCOx - 1.3
VCCOx - 0.8
VCCOx - 1.95
VCCOx - 1.75
Typical
Maximum
Units
VCCOx - 1.4
VCCOx - 0.9
V
VCCOx - 1.95
VCCOx - 1.75
V
NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7.
NOTE: Qx denotes Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7. nQx denotes nQ0, nQ1, nQ2, nQ3, nQ4, nQ5, nQ6, nQ7.
NOTE 1: Outputs terminated with 50 to VCCOx – 2V.
Table 8D. LVDS DC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5% or 2.5V ±5%, VEE = 0V,
TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VOD
Differential Output Voltage
Qx, nQx
VOD
VOD Magnitude Change
Qx, nQx
VOS
Offset Voltage
Qx, nQx
VOS
VOS Magnitude Change
Qx, nQx
Minimum
Typical
195
1.1
Maximum
Units
454
mV
50
mV
1.375
V
50
mV
NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7.
NOTE: Qx denotes Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7. nQx denotes nQ0, nQ1, nQ2, nQ3, nQ4, nQ5, nQ6, nQ7.
NOTE: Terminated 100 across Qx and nQx.
Table 8E. LVCMOS DC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
VCCOx = 3.3V±5%
Test
Conditions
Minimum
2.6
VOH
Output
High Voltage
Qx,
nQx
IOH = -8mA
VOL
Output
Low Voltage
Qx,
nQx
IOL = 8mA
Typical
Maximum
VCCOx = 2.5V±5%
Minimum
Typical
Maximum
1.8
0.5
VCCOx = 1.8V ±5%
Minimum
Typical
Maximum
1.1
0.5
Units
V
0.5
V
NOTE: Qx denotes Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7. nQx denotes nQ0, nQ1, nQ2, nQ3, nQ4, nQ5, nQ6, nQ7.
NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7.
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8T49N287 Datasheet
Table 9. Input Frequency Characteristics, VCC = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol
fIN
Parameter
Input Frequency;
NOTE 1
OSCI, OSCO
Test Conditions
Minimum
Using a crystal (See Table 10,
Crystal Characteristics)
Maximum
Units
10
40
MHz
Overdriving Crystal Input, Doubler
Logic Enabled; NOTE 2
10
62.5
MHz
Overdriving Crystal Input, Doubler
Logic Disabled; NOTE 2
16
125
MHz
0.008
875
MHz
100
400
kHz
CLKx, nCLKx
fSCLK
Serial Port Clock
SCLK
Slave Mode
Typical
NOTE: CLKx denotes CLK0, CLK1. nCLKx denotes nCLK0, nCLK1.
NOTE 1: For the input reference frequency, the divider values must be set for the VCO to operate within its supported range.
NOTE 2. For optimal noise performance, the use of a quartz crystal is recommended. Refer to Applications Information, Overdriving the
Crystal Interface.
Table 10. Crystal Characteristics
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
40
MHz
Fundamental
Frequency
10
Equivalent Series Resistance (ESR)
15
Load Capacitance (CL)
12
pF
Frequency Stability (total)
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8T49N287 Datasheet
AC Electrical Characteristics
Table 11A. AC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5%, 2.5V ±5% or 1.8V ±5% (1.8V only
supported for LVCMOS outputs), TA = -40°C to 85°C
Symbol
Parameter
fVCO
VCO Operating Frequency
fOUT
Test Conditions
LVPECL, LVDS, HCSL
Output
Frequency
Maximum
Units
3000
4000
MHz
Q0, Q1, Q4, Q5, Q6, Q7 Outputs
0.008
1000
MHz
Q2, Q3 Outputs Integer Divide
Ratio & No Added Phase Delay
0.008
666.67
MHz
Q2, Q3 Outputs Non-integer
Divide and/or Added Phase
Delay
0.008
400
MHz
0.008
250
MHz
LVCMOS
tR / tF
SR
Minimum
Typical
LVPECL
20% to 80%
145
360
600
ps
LVDS
Output
HCSL
Rise and
Fall Times
LVCMOS; NOTE 1, 2
20% to 80%
100
230
400
ps
20% to 80%
150
300
600
ps
20% to 80%, VCCOx = 3.3V
180
350
600
ps
20% to 80%, VCCOx = 2.5V
200
350
550
ps
20% to 80%, VCCOx = 1.8V
200
410
650
ps
LVPECL
Measured on
Differential Waveform,
±150mV from Center
1
5
V/ns
LVDS
Measured on
Differential Waveform,
±150mV from Center
0.5
4
V/ns
VCCOx = 2.5V, fOUT 125MHz;
Measured on
Differential Waveform,
±150mV from Center
1.5
4
V/ns
VCCOx = 3.3V, fOUT 125MHz;
Measured on
Differential Waveform,
±150mV from Center
2.5
5.5
V/ns
Output
Slew Rate;
NOTE 3
HCSL
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8T49N287 Datasheet
Symbol
Parameter
Test Conditions
LVPECL
LVDS
tsk(b)
Bank
Skew
HCSL
LVCMOS
odc
Output
Duty
Cycle;
NOTE 9
Minimum
Typical
Maximum
Units
Q0, nQ0, Q1,
nQ1
NOTE 4, 5, 6, 7
75
ps
Q4, nQ4, Q5,
nQ5
NOTE 4, 5, 6, 7
75
ps
Q6, nQ6, Q7,
nQ7
NOTE 4, 5, 6, 7
75
ps
Q0, nQ0, Q1,
nQ1
NOTE 4, 5, 6, 7
75
ps
Q4, nQ4, Q5,
nQ5
NOTE 4, 5, 6, 7
75
ps
Q6, nQ6,
Q7,nQ7
NOTE 4, 5, 6, 7
75
ps
Q0, nQ0, Q1,
nQ1
NOTE 4, 5, 6, 7
75
ps
Q4, nQ4, Q5,
nQ5
NOTE 4, 5, 6, 7
75
ps
Q6, nQ6, Q7,
nQ7
NOTE 4, 5, 6, 7
75
ps
Q0, nQ0, Q1,
nQ1
NOTE 1, 4, 5, 7, 8
80
ps
Q4, nQ4, Q5,
nQ5
NOTE 1, 4, 5, 7, 8
115
ps
Q6, nQ6, Q7,
nQ7
NOTE 1, 4, 5, 7, 8
115
ps
LVPECL, LVDS, HCSL
fOUT 666.667MHz
45
50
55
%
fOUT > 666.667MHz
40
50
60
%
40
50
60
%
50
ppb
LVCMOS
Initial Frequency Offset;
NOTE 10, 11, 12
Switchover or Entering / Leaving
Holdover State
Output Phase Change in Fully Hitless
Switching; NOTE 11, 12, 13
Switchover or Entering / Leaving
Holdover State
5
ns
1kHz
122.88MHz Output
-123
dBc/Hz
10kHz
122.88MHz Output
-131
dBc/Hz
100kHz
122.88MHz Output
-134
dBc/Hz
1MHz
122.88MHz Output
-147
dBc/Hz
SSB(10M)
10MHz
122.88MHz Output
-153
dBc/Hz
SSB(30M)
30MHz
122.88MHz Output
-154
dBc/Hz
800kHz
122.88MHz Output
-83
dBc
SSB(1k)
SSB(10k)
SSB(100k)
SSB(1M)
Single Sideband
Phase Noise;
NOTE 14
Spurious Limit at
Offset; NOTE 15
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8T49N287 Datasheet
Symbol
Parameter
Test Conditions
Internal
OTP Startup;
NOTE 11
tstartup
SPO
Startup Time
External
EEPROM
Startup;
NOTE 11, 16
Static Phase Offset Variation; NOTE 17
Typical
Maximum
Units
from VCC >80% to
First Output Clock Edge
110
150
ms
from VCC >80% to First Output
Clock Edge (0 retries);
I2C Frequency = 100kHz
150
200
ms
from VCC >80% to First Output
Clock Edge (0 retries);
I2C Frequency = 400kHz
130
150
ms
from VCC >80% to First Output
Clock Edge (31 retries);
I2C Frequency = 100kHz
925
1200
ms
from VCC >80% to First Output
Clock Edge (31 retries);
I2C Frequency = 400kHz
360
500
ms
175
ps
fIN = fOUT = 156.25MHz
Minimum
-175
NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Appropriate SE_MODE bit must be configured to select phase-aligned or phase-inverted operation.
NOTE 2: All Q and nQ outputs in phase-inverted operation
NOTE 3: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Measured at the output differential cross point.
NOTE 7: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions running off the same PLL.
NOTE 8: Measured at VCCOx/2 of the rising edge. All Qx and nQx outputs phase-aligned.
NOTE 9: Characterized in synthesizer mode. Duty cycle of bypassed signals (input reference clocks or crystal input) is not adjusted by the device.
NOTE 10: Tested in fast-lock operation after >20 minutes of locked operation to ensure holdover averaging logic is stable.
NOTE 11: This parameter is guaranteed by design.
NOTE 12: Using internal feedback mode configuration.
NOTE 13: Device programmed with SWMODEn = 0 (absorbs phase differences).
NOTE 14: Characterized with 8T49N287B-901 units (synthesizer mode).
NOTE 15: Tested with all outputs operating at 122.88MHz.
NOTE 16: Assuming a clear I2C bus.
NOTE 17: This parameter was measured using CLK0 as the reference input and CLK1 as the external feedback input. Characterized with
8T49N287-908.
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8T49N287 Datasheet
Table 11B. HCSL AC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5% or 2.5V ±5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
VRB
Ring-back Voltage Margin;
NOTE 1, 2
-100
tSTABLE
Time before VRB is allowed;
NOTE 1, 2
500
VMAX
Absolute Max. Output Voltage;
NOTE 3, 4
VMIN
Absolute Min. Output Voltage;
NOTE 3, 5
-300
VCROSS
Absolute Crossing Voltage;
NOTE 6, 7
230
VCROSS
Total Variation of VCROSS Over
all Edges; NOTE 6, 8
Typical
Maximum
Units
100
mV
ps
1150
mV
mV
550
mV
140
mV
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Measurement taken from differential waveform.
NOTE 2: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100mV differential range.
NOTE 3: Measurement taken from single ended waveform.
NOTE 4: Defined as the maximum instantaneous voltage including overshoot.
NOTE 5: Defined as the minimum instantaneous voltage including undershoot.
NOTE 6: Measured at crossing point where the instantaneous voltage value of the rising edge of Qn equals the falling edge of nQn.
NOTE 7: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement.
NOTE 8: Defined as the total variation of all crossing voltages of rising Qn and falling nQn. This is the maximum allowed variance in VCROSS
for any particular system.
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8T49N287 Datasheet
Table 12A. Typical RMS Phase Jitter (Synthesizer Mode), VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5%, 2.5V ±5% or
1.8V ±5% (1.8V only supported for LVCMOS outputs), TA = -40°C to 85°C
Symbol
Units
280
287
fs
264
263
270
fs
289
266
265
N/A
(NOTE 5)
fs
fOUT = 122.88MHz,
Integration Range: 12kHz - 20MHz
312
326
304
318
fs
Q2, Q3
Fractional;
NOTE 4
fOUT = 122.88MHz,
Integration Range: 12kHz - 20MHz
269
280
261
263
fs
Q4, Q5, Q6, Q7;
NOTE 1
fOUT = 122.88MHz,
Integration Range: 12kHz - 20MHz
302
321
295
301
fs
Test Conditions
LVPECL
LVDS
HCSL
fOUT = 122.88MHz, Integration Range:
12kHz - 20MHz; NOTE 1
282
299
fOUT = 156.25MHz, Integration Range:
12kHz - 20MHz; NOTE 2
265
fOUT = 622.08MHz, Integration Range:
12kHz - 20MHz; NOTE 3
Q2, Q3 Integer;
NOTE 1
Q0, Q1
tjit()
RMS Phase
Jitter
(Random)
LVCMOS
NOTE 6
Parameter
NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7.
NOTE: Fox part numbers: 277LF-40-18 and 277LF-38.88-2 used for 40MHz and 38.88MHz crystals, respectively.
NOTE: All outputs configured for the specific output type, as shown in the table.
NOTE 1: Characterized with 8T49N287-901.
NOTE 2: Characterized with 8T49N287-902.
NOTE 3: Characterized with 8T49N287-903.
NOTE 4: Characterized with 8T49N287-900.
NOTE 5: This frequency is not supported for LVCMOS operation.
NOTE 6: Qx and nQx are 180° out of phase.
Table 12B. Typical RMS Phase Jitter (Jitter Attenuator Mode), VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5%, 2.5V ±5%
or 1.8V ±5% (1.8V only supported for LVCMOS outputs), TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
LVPECL
LVDS
HCSL
fOUT = 122.88MHz, Integration Range:
12kHz - 20MHz; NOTE 1
285
299
fOUT = 156.25MHz, Integration Range:
12kHz - 20MHz; NOTE 2
261
fOUT = 622.08MHz, Integration Range:
12kHz - 20MHz; NOTE 3
Q2, Q3 Integer;
NOTE 1
NOTE 6
Units
280
275
fs
252
264
274
fs
221
203
202
N/A
(NOTE 5)
fs
fOUT = 122.88MHz,
Integration Range: 12kHz - 20MHz
312
327
306
306
fs
Q2, Q3
Fractional;
NOTE 4
fOUT = 122.88MHz,
Integration Range: 12kHz - 20MHz
271
282
263
267
fs
Q4, Q5, Q6, Q7;
NOTE 1
fOUT = 122.88MHz,
Integration Range: 12kHz - 20MHz
308
320
295
288
fs
Q0, Q1
tjit()
RMS Phase
Jitter
(Random)
LVCMOS
NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7.
NOTE: Measured using a Rohde & Schwarz SMA100A as the input source.
NOTE: Fox part numbers: 277LF-40-18 and 277LF-38.88-2 used for 40MHz and 38.88MHz crystals, respectively.
NOTE: All outputs configured for the specific output type, as shown in the table.
NOTE 1: Characterized with 8T49N287-905.
NOTE 2: Characterized with 8T49N287-906.
NOTE 3: Characterized with 8T49N287-907.
NOTE 4: Characterized with 8T49N287-904.
NOTE 5: This frequency is not supported for LVCMOS operation.
NOTE 6: Qx and nQx are 180° out of phase.
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8T49N287 Datasheet
Table 13. PCI Express Jitter Specifications, VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5% or 2.5V ±5%,
TA = -40°C to 85°C
Symbol
Parameter
tj
(PCIe Gen 1)
Phase Jitter
Peak-to-Peak;
NOTE 1, 4, 5
Phase Jitter
tREFCLK_HF_RMS
RMS;
(PCIe Gen 2)
NOTE 2, 4, 5
Typical
Maximum
PCIe Industry
Specification
Units
ƒ = 100MHz, 40MHz Crystal Input,
Evaluation Band: 0Hz - Nyquist (Clock
Frequency/2)
8
16
86
ps
ƒ = 100MHz, 40MHz Crystal Input,
High Band: 1.5MHz - Nyquist (Clock
Frequency/2)
0.8
1.8
3.1
ps
Test Conditions
Minimum
tREFCLK_LF_RMS
(PCIe Gen 2)
Phase Jitter
RMS;
NOTE 2, 4, 5
ƒ = 100MHz, 40MHz Crystal Input,
Low Band: 10kHz - 1.5MHz
0.03
0.5
3.0
ps
tREFCLK_RMS
(PCIe Gen 3)
Phase Jitter
RMS;
NOTE 3, 4, 5
ƒ = 100MHz, 40MHz Crystal Input,
Evaluation Band: 0Hz - Nyquist (Clock
Frequency/2)
0.2
0.5
0.8
ps
NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS
(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
NOTE 5: Outputs configured for HCSL mode. Fox 277LF-40-18 crystal used with doubler logic enabled.
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8T49N287 Datasheet
Noise Power dBc/Hz
Typical Phase Noise at 156.25MHz
Offset Frequency (Hz)
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8T49N287 Datasheet
Applications Information
Overdriving the Crystal Interface
The OSCI input can be overdriven by an LVCMOS driver or by one
side of a differential driver through an AC coupling capacitor. The
OSCO pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 5A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 5B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the OSCI input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
26&2
9&&
5
5R
=R Ω
56
&
26&,
M)
=R 5R5V
5
/9&026B'ULYHU
Figure 5A. General Diagram for LVCMOS Driver to XTAL Input Interface
OSCO
C2
Zo = 50Ω
OSCI
0.1μF
Zo = 50Ω
LVPECL_Driver
R1
50
R2
50
R3
50
Figure 5B. General Diagram for LVPECL Driver to XTAL Input Interface
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8T49N287 Datasheet
Wiring the Differential Input to Accept Single-Ended Levels
Figure 6 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VCC/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VCC = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VCC are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Suggest edge
rate faster than 1V/ns. Though some of the recommended
components might not be used, the pads should be placed in the
layout. They can be utilized for debugging purposes. The datasheet
specifications are characterized and guaranteed by using a
differential signal.
Figure 6. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
©2021 Renesas Electronics Corporation.
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8T49N287 Datasheet
3.3V Differential Clock Input Interface
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 7A, the input
termination applies for Renesas open emitter LVHSTL drivers. If you
are using an LVHSTL driver from another vendor, use their
termination recommendation.
CLKx/nCLKx accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figure 7A to Figure 7E show interface
examples for the CLKx/nCLKx input driven by the most common
driver types. The input interfaces suggested here are examples only.
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
Differential
Input
LVHSTL
IDT
LVHSTL Driver
R1
50Ω
R2
50Ω
Figure 7D. CLKx/nCLKx Input Driven by a
3.3V LVPECL Driver
Figure 7A. CLKx/nCLKx Input Driven by a
Renesas Open Emitter LVHSTL Driver
Figure 7B. CLKx/nCLKx Input Driven by a
3.3V LVPECL Driver
3.3V
Figure 7E. CLKx/nCLKx Input Driven by a
3.3V LVDS Driver
3.3V
*R3
CLK
nCLK
HCSL
*R4
Differential
Input
Figure 7C. CLKx/nCLKx Input Driven by a
3.3V HCSL Driver
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8T49N287 Datasheet
2.5V Differential Clock Input Interface
CLKx/nCLKx accepts LVDS, LVPECL, LVHSTL and other differential
signals. Both VSWING and VOH must meet the VPP and VCMR input
requirements. Figure 8A to Figure 8D show interface examples for
the CLKx/nCLKx input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 8A, the input
termination applies for Renesas open emitter LVHSTL drivers. If you
are using an LVHSTL driver from another vendor, use their
termination recommendation.
2.5V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
LVHSTL
IDT Open Emitter
LVHSTL Driver
R1
50Ω
R2
50Ω
Differential
Input
Figure 8A. CLKx/nCLKx Input Driven by a
Renesas Open Emitter LVHSTL Driver
Figure 8C. CLKx/nCLKx Input Driven by a
2.5V LVPECL Driver
Figure 8B. CLKx/nCLKx Input Driven by a
2.5V LVPECL Driver
Figure 8D. CLKx/nCLKx Input Driven by a
2.5V LVDS Driver
©2021 Renesas Electronics Corporation.
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8T49N287 Datasheet
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLKx/nCLKx Input
LVPECL Outputs
For applications not requiring the use one or more reference clock
inputs, both CLKx and nCLKx can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
CLKx to ground. It is recommended that CLKx, nCLKx not be driven
with active signals when not enabled for use.
Any unused LVPECL output pairs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or terminated.
LVDS Outputs
Any unused LVDS output pairs can be either left floating or
terminated with 100 across. If they are left floating there should be
no trace attached.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
LVCMOS Outputs
Any LVCMOS output can be left floating if unused. There should be
no trace attached.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
designed to drive 50 transmission lines. Matched impedance
techniques should be used to maximize operating frequency and
minimize signal distortion. Figure 9A and Figure 9B show two
different layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended that
the board designers simulate to guarantee compatibility across all
printed circuit and clock component process variations.
The differential outputs generate ECL/LVPECL compatible outputs.
Therefore, terminating resistors (DC current path to ground) or
current sources must be used for functionality. These outputs are
R3
125Ω
3.3V
R4
125Ω
3.3V
3.3V
Zo = 50Ω
+
_
Input
Zo = 50Ω
R1
84Ω
Figure 9A. 3.3V LVPECL Output Termination
©2021 Renesas Electronics Corporation.
R2
84Ω
Figure 9B. 3.3V LVPECL Output Termination
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8T49N287 Datasheet
Termination for 2.5V LVPECL Outputs
level. The R3 in Figure 10C can be eliminated and the termination is
shown in Figure 10B.
Figure 10A and Figure 10C show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground
2.5V
VCCO = 2.5V
2.5V
2.5V
VCCO = 2.5V
R1
250
R3
250
50Ω
+
50Ω
+
50Ω
–
50Ω
2.5V LVPECL Driver
–
R1
50
2.5V LVPECL Driver
R2
62.5
R2
50
R4
62.5
R3
18
Figure 10C. 2.5V LVPECL Driver Termination Example
Figure 10A. 2.5V LVPECL Driver Termination Example
2.5V
VCCO = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50
R2
50
Figure 10B. 2.5V LVPECL Driver Termination Example
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8T49N287 Datasheet
2.5V and 3.3V HCSL Recommended Termination
Figure 11A is the recommended source termination for applications
where the driver and receiver will be on a separate PCBs. This
termination is the standard for PCI Express™ and HCSL output
0.5" Max
L1
Rs
types. All traces should be 50Ω impedance single-ended or 100Ω
differential.
L1
0.5 - 3.5"
1-14"
0-0.2"
22 to 33 +/-5%
L2
L4
L2
L4
L5
L5
PCI Expres s
PCI Expres s
Connector
Driver
0-0.2"
L3
L3
PCI Expres s
Add-in Card
49.9 +/- 5%
Rt
Figure 11A. Recommended Source Termination (where the driver and receiver will be on separate PCBs)
Figure 11B is the recommended termination for applications where a
point-to-point connection can be used. A point-to-point connection
contains both the driver and the receiver on the same PCB. With a
matched termination at the receiver, transmission-line reflections will
0.5" Max
L1
L1
Rs
0 to 33
0 to 33
be minimized. In addition, a series resistor (Rs) at the driver offers
flexibility and can help dampen unwanted reflections. The optional
resistor can range from 0Ω to 33Ω. All traces should be 50Ω
impedance single-ended or 100Ω differential.
0-18"
0-0.2"
L2
L3
L2
L3
PCI Expres s
Driver
49.9 +/- 5%
Rt
Figure 11B. Recommended Termination (where a point-to-point connection can be used)
©2021 Renesas Electronics Corporation.
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8T49N287 Datasheet
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. Renesas offers a full line of LVDS compliant devices with
two types of output structures: current source and voltage source.
The standard termination schematic as shown in Figure 12A can be
used with either type of output structure. Figure 12B, which can also
be used with both output types, is an optional termination with center
tap capacitance to help filter common mode noise. The capacitor
value should be approximately 50pF. If using a non-standard
termination, it is recommended to contact Renesas and confirm if the
output structure is current source or voltage source type. In addition,
since these outputs are LVDS compatible, the input receiver’s
amplitude and common-mode input range should be verified for
compatibility with the output.
Figure 12A. Standard LVDS Termination
Figure 12B. Optional LVDS Termination
©2021 Renesas Electronics Corporation.
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8T49N287 Datasheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 13. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Lead frame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 13. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
Schematic and Layout Information
Schematics for 8T49N287 can be found on Renesas.com. Please
search for the 8T49N287 device and click on the link for evaluation
board schematics.
Crystal Recommendation
This device was validated using FOX 277LF series through-hole
crystals including part #277LF-40-18 (40MHz) and #277LF-38.88-2
(38.88MHz). If a surface mount crystal is desired, we recommend
FOX Part #603-40-48 (40MHz) or #603-38.88-7 (38.88MHz).
I2C Serial EEPROM Recommendation
The 8T49N287 was designed to operate with most standard I2C
serial EEPROMs of 256 bytes or larger. Atmel AT24C04C was used
during device characterization and is recommended for use. Please
contact Renesas for review of any other I2C EEPROM’s compatibility
with the 8T49N287.
©2021 Renesas Electronics Corporation.
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8T49N287 Datasheet
PCI Express Application Note
PCI Express jitter analysis methodology models the system
response to reference clock jitter. The block diagram below shows
the most frequently used Common Clock Architecture in which a
copy of the reference clock is provided to both ends of the PCI
Express Link.
In the jitter analysis, the transmit (Tx) and receive (Rx) SerDes PLLs
are modeled as well as the phase interpolator in the receiver. These
transfer functions are called H1, H2, and H3 respectively. The overall
system transfer function at the receiver is:
Ht s = H3 s H1 s – H2 s
The jitter spectrum seen by the receiver is the result of applying this
system transfer function to the clock spectrum X(s) and is:
Y s = X s H3 s H1 s – H2 s
PCIe Gen 2A Magnitude of Transfer Function
In order to generate time domain jitter numbers, an inverse Fourier
Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].
PCI Express Common Clock Architecture
For PCI Express Gen 1, one transfer function is defined and the
evaluation is performed over the entire spectrum: DC to Nyquist (e.g.,
for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is
reported in peak-peak.
PCIe Gen 2B Magnitude of Transfer Function
For PCI Express Gen 3, one transfer function is defined and the
evaluation is performed over the entire spectrum. The transfer
function parameters are different from Gen 1 and the jitter result is
reported in RMS.
PCIe Gen 1 Magnitude of Transfer Function
For PCI Express Gen 2, two transfer functions are defined with 2
evaluation ranges and the final jitter number is reported in rms. The
two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz
(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the
individual transfer functions as well as the overall transfer function Ht.
©2021 Renesas Electronics Corporation.
PCIe Gen 3 Magnitude of Transfer Function
For a more thorough overview of PCI Express jitter analysis
methodology, please refer to Renesas Application Note PCI Express
Reference Clock Requirements.
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8T49N287 Datasheet
Power Dissipation and Thermal Considerations
The 8T49N287 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. Since this device is
highly programmable with a broad range of features and functionality, the power consumption will vary as each of these features and functions
is enabled.
The 8T49N287 device was designed and characterized to operate within the ambient industrial temperature range of -40°C to +85°C. The
ambient temperature represents the temperature around the device, not the junction temperature. When using the device in extreme cases,
such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and reliable
junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature.
The power calculation examples below were generated using a maximum ambient temperature and supply voltage. For many applications, the
power consumption will be much lower. Please contact Renesas technical support for any concerns on calculating the power dissipation for
your own specific configuration.
Power Domains
The 8T49N287 device has a number of separate power domains that can be independently enabled and disabled via register accesses (all
power supply pins must still be connected to a valid supply voltage). Figure 14 below indicates the individual domains and the associated power
pins.
Output Divider / Buffer Q0 (V CCO0)
Output Divider / Buffer Q1 (V CCO1)
Analog & Digital PLL0
(VCCA & Core V CC)
Output Divider / Buffer Q2 (V CCO2)
CLK Input &
Divider Block
(Core VCC)
Output Divider / Buffer Q3 (V CCO3)
Output Divider / Buffer Q4 (V CCO4)
Analog & Digital PLL1
(VCCA & Core V CC)
Output Divider / Buffer Q5 (V CCO5)
Output Divider / Buffer Q6 (V CCO6)
Output Divider / Buffer Q7 (V CCO7)
Figure 14. 8T49N287 Power Domains
For the output paths shown above, there are three different structures that are used. Q0 and Q1 use one output path structure, Q2 and Q3 use
a second structure and Q[4:7] use a 3rd structure. Power consumption data will vary slightly depending on the structure used as shown in the
appropriate tables below.
Power Consumption Calculation
Determining total power consumption involves several steps:
1.
2.
3.
Determine the power consumption using maximum current values for core and analog voltage supplies from Table 7A and Table 7B.
Determine the nominal power consumption of each enabled output path.
a.
This consists of a base amount of power that is independent of operating frequency, as shown in Table 15A through Table 15I
(depending on the chosen output protocol).
b.
Then there is a variable amount of power that is related to the output frequency. This can be determined by multiplying the output
frequency by the FQ_Factor shown in Table 15A through Table 15I.
All of the above totals are then summed.
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Thermal Considerations
Once the total power consumption has been determined, it is necessary to calculate the maximum operating junction temperature for the device
under the environmental conditions it will operate in. Thermal conduction paths, air flow rate and ambient air temperature are factors that can
affect this. The thermal conduction path refers to whether heat is to be conducted away via a heatsink, via airflow or via conduction into the
PCB through the device pads (including the ePAD). Thermal conduction data is provided for typical scenarios in Table 14 below. Please contact
Renesas for assistance in calculating results under other scenarios.
Table 14. Thermal Resistance JA for 56-Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2
16.0°C/W
12.14°C/W
11.02°C/W
Current Consumption Data and Equations
Table 15A. 3.3V LVPECL Output Calculation Table
Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
FQ_Factor (mA/MHz)
Base Current (mA)
0.00593
40.1
0.01363
63.8
0.00591
42.9
Table 15D. 2.5V LVPECL Output Calculation Table
Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Table 15B. 3.3V HCSL Output Calculation Table
Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
FQ_Factor (mA/MHz)
Base Current (mA)
0.00582
40.1
0.01358
63.8
0.00553
43.1
FQ_Factor (mA/MHz)
Base Current (mA)
0.00627
48.6
0.01404
72.5
0.00630
51.3
©2021 Renesas Electronics Corporation.
Base Current (mA)
0.00373
32.8
0.01134
56.5
0.00369
35.7
Table 15E. 2.5V HCSL Output Calculation Table
Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Table 15C. 3.3V LVDS Output Calculation Table
Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
FQ_Factor (mA/MHz)
FQ_Factor (mA/MHz)
Base Current (mA)
0.00354
32.9
0.01125
56.5
0.00353
35.7
Table 15F. 2.5V LVDS Output Calculation Table
Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
66
FQ_Factor (mA/MHz)
Base Current (mA)
0.00366
40.8
0.01148
64.5
0.00367
43.7
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8T49N287 Datasheet
Table 15G. 3.3V LVCMOS Output Calculation Table
Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Table 15I. 1.8V LVCMOS Output Calculation Table
Base Current (mA)
Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
37.4
61.6
40.6
Base Current (mA)
27.4
51.4
30.3
Table 15H. 2.5V LVCMOS Output Calculation Table
Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Base Current (mA)
30.8
54.8
33.7
Applying the values to the following equation will yield output current by frequency:
Qx Current (mA) = FQ_Factor * Frequency (MHz) + Base Current
where:
Qx Current is the specific output current according to output type and frequency
FQ_Factor is used for calculating current increase due to output frequency
Base Current is the base current for each output path independent of output frequency
The second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient, using the following
equation:
TJ = TA + (JA * Pdtotal)
where:
TJ is the junction temperature (°C)
TA is the ambient temperature (°C)
JA is the thermal resistance value from Table 14, dependent on ambient airflow (°C/W)
Pdtotal is the total power dissipation of the 8T49N287 under usage conditions, including power dissipated due to loading (W)
Note that the power dissipation per output pair due to loading is assumed to be 27.95mW for LVPECL outputs and 44.5mW for HCSL outputs.
When selecting LVCMOS outputs, power dissipation through the load will vary based on a variety of factors including termination type and
trace length. For these examples, power dissipation through loading will be calculated using CPD (found in Table 2) and output frequency:
PdOUT = CPD * FOUT * VCCO2
where:
Pdout is the power dissipation of the output (W)
Cpd is the power dissipation capacitance (pF)
Fout is the output frequency of the selected output (MHz)
VCCO is the voltage supplied to the appropriate output (V)
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Example Calculations
Example 1. Common Customer Configuration (3.3V Core Voltage)
Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PLL0
PLL1
Output Type
LVPECL
LVPECL
LVPECL
LVPECL
LVDS
LVDS
LVCMOS
LVCMOS
Frequency (MHz)
245.76
245.76
33.333
33.333
125
125
25
25
Enabled
Enabled
VCCO
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
• Core Supply Current, ICC = 100mA (max)
• Analog Supply Current, ICCA = 265mA (max)
Q0 Current = 0.00593x245.76 + 40.1 = 41.56mA
Q1 Current = 0.00593x245.76 + 40.1 = 41.56mA
Q2 Current = 0.01363x33.333 + 63.8 = 64.25mA
Q3 Current = 0.01363x33.333 + 63.8 = 64.25mA
Q4 Current = 0.00630x125 + 51.3 = 52.09mA
Q5 Current = 0.00630x125 + 51.3 = 52.09mA
Q6 Current = 40.6mA
Q7 Current = 40.6mA
• Total Output Current = 397mA (max)
Total Device Current = 100mA + 265mA + 397mA = 762mA
Total Device Power = 3.465V * 762mA = 2640.3mW
• Power dissipated through output loading:
LVPECL = 27.95mW * 4 = 111.8mW
LVDS = already accounted for in device power
HCSL = n/a
LVCMOS = 14.5pF * 25MHz * 3.465V2 * 2 output pairs = 8.7mW
• Total Power = 2640.3mW + 111.8mW + 8.7mW = 2760.8mW or 2.8W
With an ambient temperature of 85°C and no airflow, the junction temperature is:
TJ = 85°C + 16.1°C/W * 2.8W = 130.1°C
This junction temperature is above the maximum allowable. In instances where maximum junction temperature is exceeded adjustments need
to be made to either airflow or ambient temperature. In this case, adjusting airflow to 1m/s (JA = 12.4°C/W) will reduce junction temperature
to 119.7C. If no airflow adjustments can be made, the maximum ambient operating temperature must be reduced by a minimum of 5.1°C.
©2021 Renesas Electronics Corporation.
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Example 2. High-Frequency Customer Configuration (3.3V Core Voltage)
Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PLL0
PLL1
Output Type
LVDS
LVDS
LVPECL
LVPECL
HCSL
HCSL
HCSL
HCSL
Frequency (MHz)
625.00
625.00
161.133
161.133
25
25
125
156.25
Enabled
Disabled
VCCO
2.5
2.5
2.5
2.5
3.3
3.3
3.3
3.3
• Core Supply Current, ICC = 100mA (max)
• Analog Supply Current, ICCA = 187mA (max, PLL0 path only)
Q0 Current = 0.00366x625 + 40.8 = 43.09mA
Q1 Current = 0.00366x625 + 40.8 = 43.09mA
Q2 Current = 0.01134x161.133 + 56.5 = 58.3mA
Q3 Current = 0.01134x161.133 + 56.5 = 58.3mA
Q4 Current = 0.00553x25 + 43.1 = 43.24mA
Q5 Current = 0.00553x25 + 43.1 = 43.24mA
Q6 Current = 0.00553x125 + 43.1 = 43.79mA
Q7 Current = 0.00553x156.25 + 43.1 = 43.96mA
• Total Output Current = 202.8mA (VCCO = 2.5V), 174.23mA (VCCO = 3.3V)
Total Device Power = 3.465V *(100mA + 187mA + 174.23mA) + 2.625V * 202.8mA = 2130.5mW
• Power dissipated through output loading:
LVPECL = 27.95mW * 2 = 55.9mW
LVDS = already accounted for in device power
HCSL = 44.5mW * 4 = 178mW
LVCMOS = n/a
Total Power = 2130.5mW + 55.9mW + 178mW = 2364.4mW or 2.36W
With an ambient temperature of 85°C, the junction temperature is:
TJ = 85°C + 16.1°C/W *2.36W = 123°C
This junction temperature is below the maximum allowable.
©2021 Renesas Electronics Corporation.
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Example 3. Low Power Customer Configuration (2.5V Core Voltage)
Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PLL0
PLL1
Output Type
LVDS
LVDS
LVDS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVDS
VCCO
Frequency (MHz)
156.25
156.25
161.133
33.333
25
25
25
156.25
Enabled
Enabled
2.5
2.5
2.5
1.8
1.8
1.8
1.8
2.5
• Core Supply Current, ICC = 95mA (max)
• Analog Supply Current, ICCA = 260mA (max)
Q0 Current = 0.00366x156.25 + 40.8 = 41.37mA
Q1 Current = 0.00366x156.25 + 40.8 = 41.37mA
Q2 Current = 0.01148x161.133 + 64.5 = 66.35mA
Q3 Current = 51.4mA
Q4 Current = 30.3mA
Q5 Current = 30.3mA
Q6 Current = 30.3mA
Q7 Current = 0.00367x156.25 + 43.7 = 44.27mA
• Total Output Current = 193.36mA (VCCO = 2.5V), 142.3mA (VCCO = 1.8V)
Total Device Power = 2.625V *(95mA + 260mA + 193.36mA) + 1.89V * 142.3mA = 1708.4mW
• Power dissipated through output loading:
LVPECL = n/a
LVDS = already accounted for in device power
HCSL = n/a
LVCMOS_33.3MHz = 17pF * 33.3MHz * 1.89V2 * 1 output pair = 2.02mW
LVCMOS_25MHz = 12.5pF * 25MHz * 1.89V2 * 3 output pairs = 3.35mW
Total Power = 1708.4mW + 2.02mW + 3.35mW = 1714mW or 1.7W
With an ambient temperature of 85°C, the junction temperature is:
TJ = 85°C + 16.1°C/W *1.7W = 112.4°C
This junction temperature is below the maximum allowable.
©2021 Renesas Electronics Corporation.
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8T49N287 Datasheet
Reliability Information
Table 16. JA vs. Air Flow Table for a 56-Lead VFQFN
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2
16.0°C/W
12.14°C/W
11.02°C/W
NOTE: Theta JA (JA)values calculated using a 4-layer JEDEC PCB (114.3mm x 101.6mm), with 2oz. (70µm) copper plating on all 4 layers.
Transistor Count
The transistor count for 8T49N287 is: 998,958
Package Outline Drawings
The package outline drawings are located at the end of this document and are accessible from the Renesas website. The package information
is the most current data available and is subject to change without revision of this document.
©2021 Renesas Electronics Corporation.
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8T49N287 Datasheet
Marking Diagram
1. Line 1 (excluding “IDT”) and Line 2 is the part number.
2. “ddd” denotes a configuration-specific number (dash code).
3. “#” denotes stepping.
4. “YYWW” denotes: “YY” is the last two digits of the year, and “WW” is the work week number
that the part was assembled.
5. “$” denotes the mark code.
Ordering Information
Table 17. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
8T49N287A-dddNLGI
IDT8T49N287A-dddNLGI
56-Lead VFQFN, Lead-Free
Tray
-40C to +85C
8T49N287A-dddNLGI8
IDT8T49N287A-dddNLGI
56-Lead VFQFN, Lead-Free
Tape & Reel, Pin 1
Orientation: EIA-481-C
-40C to +85C
8T49N287A-dddNLGI#
IDT8T49N287A-dddNLGI
56-Lead VFQFN, Lead-Free
Tape & Reel, Pin 1
Orientation: EIA-481-D
-40C to +85C
NOTE: For the specific, publicly available -ddd order codes, refer to FemtoClock NG Universal Frequency Translator Ordering Product
Information document. For custom -ddd order codes, please contact Renesas for more information.
Table 18. Pin 1 Orientation in Tape and Reel Packaging
Part Number Suffix
Pin 1 Orientation
Illustration
Correct Pin 1 ORIENTATION
NLGI8
CARRIER TAPE TOPSIDE
(Round Sprocket Holes)
Quadrant 1 (EIA-481-C)
USER DIRECTION OF FEED
Correct Pin 1 ORIENTATION
NLGI#
CARRIER TAPE TOPSIDE
(Round Sprocket Holes)
Quadrant 2 (EIA-481-D)
USER DIRECTION OF FEED
©2021 Renesas Electronics Corporation.
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8T49N287 Datasheet
Revision History
Revision Date
Description of Change
March 8, 2021
• Updated Figure 5A
• Completed other minor changes
July 14, 2020
• Corrected the Marking Diagram description
• Changed IDT references to Renesas
January 21, 2019
Corrected the I2C read sequence diagrams in Figure 3 and Figure 4 to match I2C specification and device actual
performance. Note: Only the drawings were incorrect – the part’s behavior did not change and continues to meet
the I2C specification.
January 31, 2018
Updated I2C Mode Operation to indicate support for v2.1 of the I2C specification
October 30, 2017
Added a Marking Diagram
September 11, 2017
• Added a note before Digital PLL0 Status Register Bit Field Locations and Descriptions and Digital PLL1 Status
Register Bit Field Locations and Descriptions
• Added the following fields to Digital PLL0 Status Register Bit Field Locations and Descriptions and Digital PLL1
Status Register Bit Field Locations and Descriptions: NO_REF, SM_STS, and PLLLCK
October 27, 2016
Crystal Recommendation - deleted IDT crystal reference.
February 1, 2016
T17, Per PCN# W1512-01, Effective Date 03/18/2016 - changed Part/Order Number from 8T49N287-dddNLGI
to 8T49N287A-dddNLGI, and
Marking from IDT8T49N287-dddNLGI to IDT8T49N287A-dddNLGI.
Updated Datasheet header/footer.
July 9, 2015
Device Start-up and Reset Behavior - added second paragraph.
AC Characteristics Table - added fOUT minimum parameters.
June 1, 2015
Termination for 3.3V LVPECL Outputs updated Figure 9A.
Updated Crystal Recommendation.
Table 11A, AC Characteristics Table - updated LVDS Rise/Fall Time maximum spec. from 500 to 400ps.
March 20, 2015
November 6, 2014
Miscellaneous content enhancement in: Output Phase Control on Switchover section; Table 6A, Table 6C, Table
6E and Table 6G, and Pin Assignment format.
Description - first paragraph/last sentence, added HCSL.
Features - added HCSL in “Accepts up to two LVPECL....” bullet and “Generates 8 LVPECL...” bullet.
©2021 Renesas Electronics Corporation.
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