MK5811AS

MK5811A Low EMI Clock Generator Description The MK5811A device generates a low EMI output clock from a clock or crystal input. The device is designed to dither a high emissions clock to lower EMI in consumer applications. Using ICS’ proprietary mix of analog and digital Phase Locked Loop (PLL) technology, the device spreads the frequency spectrum of the output and reduces the frequency amplitude peaks by several dB. The MK5811A offers both centered and down spread from a high-speed clock input. For different multiplier configurations, use the MK5812 (2x) or MK5814 (4x). ICS offers many other clocks for computers and computer peripherals. Consult ICS when you need to remove crystals and oscillators from your board. Features • • • • • • • • • • • • • • Packaged in 8-pin SOIC Available in Pb (lead) free package Provides a spread spectrum output clock Supports flat panel controllers Accepts a clock or crystal input (provides same frequency dithered output) Input frequency range of 4 to 32 MHz Output frequency range of 4 to 32 MHz 1X frequency multiplication Center and down spread Peak reduction by 8 dB to 16 dB typical on 3rd through 19th odd harmonics Low EMI feature can be disabled Includes power down Operating voltage of 3.3 V Advanced, low-power CMOS process Block Diagram VDD S1:0 Spread Direction FRSEL 2 X1/CLK Clock Buffer/ Crystal Ocsillator X2 PLL Clock Synthesis and Spread Spectrum Circuitry SSCLK The crystal requires external capacitors for accurate tuning of the clock GND MDS 5811A A Integrated Circuit Systems, Inc. 1 5 25 Race Street, San Jose, CA 95126 t el (408) 297-1201 Revision 091205 w ww.icst.com MK5811A Low EMI Clock Generator Pin Assignment Spread Direction and Spread Percentage 8 7 6 5 X2 VDD FRSEL SSCLK S1 Pin 3 0 0 0 M M M 1 1 1 S0 Pin 4 0 M 1 0 M 1 0 M 1 Spread Direction Center Center Center Center No Spread Down Down Down Down Spread Percentage ±1.4 ±1.1 ±0.6 ±0.5 -1.6 -2.0 -0.7 -3.0 X1/ICLK GND S1 S0 1 2 3 4 8-pin (150 mil) SOIC 0 = connect to GND M = unconnected (floating) 1 = connect directly to VDD Frequency Selection Product MK5811 FRSEL (pin 6) 0 1 M MK58121 0 1 M MK58141 0 1 M Input Freq. Range 4.0 to 8.0 MHz 8.0 to 16.0MHz 16.0 to 32.0MHz 4.0 to 8.0 MHz 8.0 to 16.0MHz 16.0 to 32.0MHz 4.0 to 8.0 MHz 8.0 to 16.0MHz 16.0 to 32.0MHz Multiplier X1 X1 X1 X2 X2 X2 X4 X4 X4 Output Freq. Range 4.0 to 8.0 MHz 8.0 to 16.0MHz 16.0 to 32.0MHz 8.0 to 16.0MHz 16.0 to 32.0MHz 32.0 to 64.0MHz 16.0 to 32.0MHz 32.0 to 64.0MHz 64.0 to 128MHz 0 = connect to GND M = unconnected (floating) 1 = connect directly to VDD Note 1: The information in this datasheet does not apply to the MK5812 and MK5814 as each have independent datasheets available at www.icst.com. MDS 5811A A Integrated Circuit Systems, Inc. 2 5 25 Race Street, San Jose, CA 95126 t el (408) 297-1201 Revision 091205 w ww.icst.com MK5811A Low EMI Clock Generator Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1 2 3 4 5 6 7 8 X1/ICLK GND S1 S0 SSCLK FRSEL VDD X2 Input Power Input Input Output Input Power XO Connect to 4-32 MHz crystal or clock. Connect to ground. Function select 1 input. Selects spread amount and direction per table above. (default-internal mid-level). Function select 0 input. Selects spread amount and direction per table above. (default-internal mid-level). Clock output with Spread spectrum Function select for input frequency range. Default to mid level “M”. Connect to +3.3 V. Crystal connection to 4-32 MHz crystal. Leave unconnected for clock External Components The MK5811A requires a minimum number of external components for proper operation. PCB Layout Recommendations For optimum device performance and lowest output phase noise, observe the following guidelines: 1) Mount the 0.01µF decoupling capacitor on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to the VDD pin and the PCB trace to the ground via should be kept as short as possible. 2) To minimize EMI, place the 20Ω series-termination resistor (if needed) close to the clock output. 3) An optimum layout is one with all components on the same side of the board, thus minimizing vias through other signal layers. Other signal traces should be routed away from the MK5811A device. This includes signal traces located underneath the device, or on layers adjacent to the ground plane layer used by the device. Decoupling Capacitor A decoupling capacitor of 0.01µF must be connected between VDD and GND on pins 7 and 2. Connect the capacitor as close to these pins as possible. For optimum device performance, mount the decoupling capacitor on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor Use series termination when the PCB trace between the clock output and the load is over 1 inch. To series terminate a 50Ω trace (a commonly used trace impedance), place a 20Ω resistor in series with the clock line. Place the resistor as close to the clock output pin as possible. The nominal impedance of the clock output is 30Ω. Crystal Information The crystal used should be a fundamental mode (do not use third overtone), parallel resonant crystal. To optimize the initial accuracy, connect crystal capacitors from pins X1 to ground and X2 to ground. The value of these capacitors is given by the following equation: Crystal caps (pF) = (CL - 6) x 2 Tri-level Select Pin Operation The S1 and S0 select pins are tri-level, meaning that they have three separate states to make the selections shown in the table on page 2. To select the M (mid) level, the connection to these pins must be eliminated by either floating them originally, or tri-stating the GPIO pins which drive the select pins. MDS 5811A A Integrated Circuit Systems, Inc. 3 5 25 Race Street, San Jose, CA 95126 t el (408) 297-1201 Revision 091205 w ww.icst.com MK5811A Low EMI Clock Generator In the equation, CL is the crystal load capacitance. For example, a crystal with a 16 pF load capacitance uses two 20 pF [(16-6) x 2] capacitors. Modulation R ate Spread Spectrum Profile The MK5811A is a low EMI clock generator using a optimized frequency slew rate algorithm to facilitate down stream tracking of zero delay buffers and other PLL devices. Frequency Time Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK5811A. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device, at these or any other conditions, above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V Rating -0.5 V to VDD+0.5 V 0 to +85°C -65 to +150°C 125°C 260°C Recommended Operation Conditions Parameter Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Min. 0 +3.0 Typ. Max. +85 3.63 Units °C V MDS 5811A A Integrated Circuit Systems, Inc. 4 5 25 Race Street, San Jose, CA 95126 t el (408) 297-1201 Revision 091205 w ww.icst.com MK5811A Low EMI Clock Generator DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature 0 to +85°C Parameter Operating Voltage Supply Current Symbol VDD IDD Conditions No load, at 3.3 V, Fin=12 MHz No load, at 3.3 V, Fin=24 MHz No load, at 3.3 V, Fin=32 MHz Min. 3.0 Typ. 3.3 23 Max. 3.63 25 30 35 Units V mA mA mA V V V V V Input High Voltage Input middle Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Input Capacitance Nominal Output Impedance VIH VIHM VIL VOH VOH VOL CIN1 CIN2 ZO CMOS, IOH = 12 mA IOH = 24 mA IOL = -12 mA IOL = -24 mA S0, S1, FRSEL pins X1, X2 pins 0.85VDD 0.4VDD 0.0 2.4 2.0 VDD 0.5VDD 0.0 VDD 0.6VDD 0.15VDD 0.4 1.2 4 6 30 6 9 V V pF pF Ω AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature 0 to +85° C, CL = 15 pF Parameter Input Clock Frequency Output Clock Frequency Input Clock Duty Cycle Output Clock Duty Cycle Cycle-to-cycle Jitter1 1 Symbol Conditions Min. 4 4 Typ. Max. Units 32 32 60 MHz MHz % % ps ps ns ns dB Time above VDD/2 Time above 1.5 V Fin=4MHz, Fout=4 MHz Fin=8MHz, Fout=8 MHz tR tF 0.4 to 2.4 V 2.4 to 0.4 V 40 45 50 350 250 1.2 1.2 8 to 16 55 800 450 Cycle-to-cycle Jitter Output Rise Time Output Fall Time EMI Peak Frequency Reduction Note 1: Spread is enabled. MDS 5811A A Integrated Circuit Systems, Inc. 5 5 25 Race Street, San Jose, CA 95126 t el (408) 297-1201 Revision 091205 w ww.icst.com MK5811A Low EMI Clock Generator Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 8 Millimeters Symbol Min Max Inches Min Max E INDEX AREA H 12 D A A1 B C D E e H h L α 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0° 8° .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0° 8° A A1 h x 45 C -Ce B SEATING PLANE L .10 (.004) C Thermal Characteristics for 8-pin SOIC Parameter Thermal Resistance Junction to Ambient Symbol θJA θJA θJA θJC Conditions Still air 1 m/s air flow 3 m/s air flow Min. Typ. 150 140 120 40 Max. Units °C/W °C/W °C/W °C/W Thermal Resistance Junction to Case MDS 5811A A Integrated Circuit Systems, Inc. 6 5 25 Race Street, San Jose, CA 95126 t el (408) 297-1201 Revision 091205 w ww.icst.com MK5811A Low EMI Clock Generator Ordering Information Part / Order Number MK5811AS MK5811ASTR MK5811ASLF MK5811ASLFTR Marking 5811AS 5811AS 5811ASL 5811ASL Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Package 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC Temperature 0 to +85° C 0 to +85° C 0 to +85° C 0 to +85° C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc. (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS 5811A A Integrated Circuit Systems, Inc. 7 5 25 Race Street, San Jose, CA 95126 t el (408) 297-1201 Revision 091205 w ww.icst.com