TSI381-66IL

® Tsi381™ PCIe® to PCI Bridge Product Brief Features Device Overview General • PCI Express to PCI bridge • Transparent, Non-transparent, and Opaque modes • Efficient queuing and buffering for low latency and high throughput • Compliant with the following specifications: – PCI Express Base 1.1 – PCI Express PCI/PCI-X Bridge 1.0 – PCI-to-PCI Bridge Architecture 1.2 – PCI Local Bus 3.0 – PCI Bus Power Management Interface 1.2 The IDT Tsi381 is a high-performance bus bridge that connects the PCI Express protocol to the PCI bus standard. The Tsi381’s PCIe Interface supports a x1 lane PCIe configuration, which enables the bridge to offer exceptional throughput performance of up to 2.5 Gbps per transmit and receive direction. PCI • • • • • • • PCI • • • • • • The device’s PCI Interface can operate up to 66 MHz. This interface offers designers extensive flexibility by supporting three types of addressing modes: transparent, opaque, and non-transparent. Clocking/ Reset Express x1 lane PCIe Interface Advanced error reporting capability End-to-end CRC check and generation Up to four outstanding memory reads ASPM L0 link state power management Legacy interrupt signaling and MSI interrupts Hot Plug support Interrupt Handling Error Handling 32/64-bit addressing and 32-bit data Operates at 25, 33, 50, and 66 MHz Up to eight outstanding memory reads 3.3V PCI I/Os, 5V tolerant Four external PCI masters supported through internal arbiter MSI generation and handling using interrupt and GPIO signals Other Features • Masquerade mode • JTAG IEEE 1149.1, 1149.6 to allow testing of the PCIe Interface • Four GPIO pins and four interrupt pins that can generate MSIs • D0, D3 hot, D3 cold power management state support • 1.2V core power supply • No power sequencing constraints • Packaging: – 13x13 mm, 144-pin PBGA (10x10 mm option is available; part number Tsi382) – Pinout and footprint compatible with PLX PEX 8111/8112 – Industrial temperature operating range – RoHS-compliant package available 1 of 2  2008 Integrated Device Technology, Inc. Posted Writer Buffer Posted Queue Upstream NonPosted Buffer NonPosted Queue Mux Logic Power Mgmt Mux Logic Posted Writer Buffer Posted Queue Downstream NonPosted Buffer NonPosted Queue GPIO PCI Arbiter EEPROM Controller PCIe Interface (x1) PCI Interface Config Registers JTAG 80E2000_BK001_03 (Tsi381) Figure 1 Block Diagram Simplest, Low-Risk Design The Tsi381 simplifies board design by using only two power supplies with no power sequencing constraints. Its package is designed to simplify board layout for high reliability and signal integrity. A comprehensive suite of design support resources are also available to aid designers. Pin compatibility with the PLX PEX8111 and PEX8112 make it easy for designers to migrate current designs to the Tsi381, and thereby bring them to market quickly and with low risk. August 14, 2009 Tsi381 Evaluation Board Product Brief High Performance In addition to low-latency operation and high throughput, the Tsi381 incorporates performance enhancing features, such as short-term caching, that can provide a significant performance boost in many applications. Transparent, Non-transparent, and Opaque Bridging Transparent mode operation is available for efficient, flow through configurations, while non-transparent bridging allows isolation between the Tsi381’s PCIe and PCI domains. Non-transparent bridging also enables multi-host systems and is used in applications such as intelligent adapter cards. Opaque mode provides semi-transparent operation for multi-processor configurations and enhanced private device support. Typical Applications The Tsi381 is suited to applications that need to bridge PCIe to downstream PCI devices. Its flexibility, high performance, small footprint, and low power consumption, make it ideal for a wide range of applications, including: • Digital video recorders • Motherboards (server, SBC, industrial PC) • PC adapter cards (communications, graphics, imaging, and multimedia) • Multifunction printers • Line cards and NICs Camera Camera Camera Camera Video Decoder Video Decoder Video Decoder Video Decoder PCI Bus Tsi381 80E2000_TA002_01 x1 PCIe Figure 2 PC Digital Video Recorder Card Application August 16, 2004August 16, 200 NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. ® CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 2 of 2 for Tech Support: email: ssdhelp@idt.com phone: 408-284-8208 document: 80E2000_FB001_07 August 14, 2009 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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