Titl
IDT Tsi577
Serial RapidIO Switch
Hardware Manual
May 18, 2012
GENERAL DISCLAIMER
Integrated Device Technology, Inc. (“IDT”) reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or
performance. IDT does not assume responsibility for use of any circuitry described herein other than the circuitry embodied in an IDT product. Disclosure of the information
herein does not convey a license or any other right, by implication or otherwise, in any patent, trademark, or other intellectual property right of IDT. IDT products may
contain errata which can affect product performance to a minor or immaterial degree. Current characterized errata will be made available upon request. Items identified
herein as “reserved” or “undefined” are reserved for future definition. IDT does not assume responsibility for conflicts or incompatibilities arising from the future definition
of such items. IDT products have not been designed, tested, or manufactured for use in, and thus are not warranted for, applications where the failure, malfunction, or
any inaccuracy in the application carries a risk of death, serious bodily injury, or damage to tangible property. Code examples provided herein by IDT are for illustrative
purposes only and should not be relied upon for developing applications. Any use of such code examples shall be at the user's sole risk.
Copyright © 2012 Integrated Device Technology, Inc.
All Rights Reserved.
The IDT logo is registered to Integrated Device Technology, Inc. IDT and CPS are trademarks of Integrated Device Technology, Inc.
3
Contents
1.
2.
3.
A.
Signals and Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2
Pinlist and Ballmap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.3
Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.4
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.3
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2
Impedance Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3
Tracking Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.4
Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.5
Decoupling Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.6
Clocking and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.7
Modeling and Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.8
Testing and Debugging Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.9
Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
A.1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
A.2
Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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Tsi577 Hardware Manual
May 18, 2012
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About this Document
This section discusses general document information about the Serial RapidIO Switch. The
following topics are described:
•
“Scope” on page 5
•
“Document Conventions” on page 5
•
“Revision History” on page 7
Scope
The Tsi577 Hardware Manual discusses electrical, physical, and board layout information for
the Tsi577. It is intended for hardware engineers who are designing system interconnect
applications with these devices.
Document Conventions
This document uses a variety of conventions to establish consistency and to help you quickly
locate information of interest. These conventions are briefly discussed in the following sections.
Non-differential Signal Notation
Non-differential signals are either active-low or active-high. An active-low signal has an active
state of logic 0 (or the lower voltage level), and is denoted by a lowercase “b”. An active-high
signal has an active state of logic 1 (or the higher voltage level), and is not denoted by a special
character. The following table illustrates the non-differential signal naming convention.
State
Single-line signal
Multi-line signal
Active low
NAME_b
NAMEn[3]
Active high
NAME
NAME[3]
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Differential Signal Notation
Differential signals consist of pairs of complement positive and negative signals that are
measured at the same time to determine a signal’s active or inactive state (they are denoted by
“_p” and “_n”, respectively). The following table illustrates the differential signal naming
convention.
State
Single-line signal
Multi-line signal
Inactive
NAME_p = 0
NAME_n = 1
NAME_p[3] = 0
NAME_n[3] =1
Active
NAME_p = 1
NAME_n = 0
NAME_p[3] is 1
NAME_n[3] is 0
Symbols
This symbol indicates a basic design concept or information considered helpful.
Ti
p
This symbol indicates important configuration information or suggestions.
This symbol indicates procedures or operating levels that may result in misuse or
damage to the device.
Serial RapidIO Switch
May 18, 2012
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7
Revision History
May 18, 2012, Formal
•
Updated the first paragraph in “Power Sequencing” on page 35
•
Added Figure 38 (Analyzer Probe Footprint)
November 18, 2010, Formal
Added a note to Table 13
August 2009, Formal
There have been no technical changes to this document. The formatting has been updated to
reflect IDT.
June 2009, Formal
There have been changes throughout the document.
September 2008, Advance
•
Updated Table 8 on page 32 with new Tsi577 operating conditions
August 2008, Advance
•
Updated Table 5 on page 29 with new Tsi577 thermal characteristics
•
Updated Table 6 on page 29 with new simulated junction to ambient characteristics
August 2008, Advance
Although changes occurred throughout this document, the majority of changes were in “Signals
and Package” on page 11.
June 2008, Advance
This was the first version of this document.
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Tsi577 Hardware Manual
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8
Bibliography
1
RapidIO Interconnect Specification
(Revision 1.3)
This specification explains RapidIO’s logical layer,
common transport layer, and physical layer protocol and
packet formats. It also describes overall inter-operability
requirements for the RapidIO protocol. For more
information, see www.rapidio.org.
2
Enhancements to the RapidIO AC
Specification
This document contains the AC specifications for the
RapidIO physical layer.
ANSI/TIA/EIA-644-1995,
This documents the LVDS electrical characteristics.
3
Electrical Characteristics of Low
Voltage Differential Signaling
(LVDS) Interface Circuits, March
1996.
4
I2C Specification
This specification defines the standard I2C bus
interface, including specifications for all the
enhancements. For more information, see
www.semiconductors.philips.com
document number: 9398 393 40011
5
High-Speed Digital System
Hall,Stephen H.,Garret W. Hall & James A. McCall,
Design
©2000 John
Wiley & Sons inc.
ISBN 0-471-36090-2
6
High-Speed Digital Design
Johnson, Howard, Martin Graham
©1993 Prentice-Hall inc.
ISBN 0-13-395724-1
7
High Performance Printed
Harper, Charles A.
Circuit Boards
©1999 McGraw-Hill
ISBN 0-07-026713-8
8
Transmission Line
Application Note 905
RAPIDESIGNER©
©1996 National Semiconductor Corp.
Lit # 100905-002 & 633201-001
9
High Speed PCB Design
Ritchey, Lee W., James C. Blankenhorn
©1993 SMT Plus Inc., and Ritch Tech
10
Design Guidelines for Electronic
The Institute for Interconnecting and Packaging
Packaging Utilizing High Speed
Electronic Circuits
Techniques
©1999 IPC
Document # IPC-D-317A
Serial RapidIO Switch
May 18, 2012
Integrated Device Technology
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9
11
High Speed Signal Propagation
Johnson, Howard, Martin Graham
©2003 Prentice-Hall inc.
ISBN 0-13-084408-X
12
High Speed Digital Design and PCB
Layout
Hanson, Robert J.
1-10 GBps Serial Interconnect
Requirements
Solving High Speed Serial Design Challenges
10GBps Serial Backplanes Using
Virtex-II Pro X
Solving High Speed Serial Design Challenges
15
Designing Controlled-impedance Vias
Thomas Neu, EDN magazine, October 2 2003
16
Computer Circuits Electrical Design,
First Edition,
Ron K. Poon
13
14
Integrated Device Technology
www.idt.com
©AmeriCom Test & SMT Technology Inc.
©2004Xilinx
©2004Xilinx
Prentice-Hall, Inc., 1995
Tsi577 Hardware Manual
May 18, 2012
10
Serial RapidIO Switch
May 18, 2012
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11
1.
Signals and Package
This chapter describes the packaging (mechanical) features for the Tsi577. It includes the
following information:
1.1
•
“Signals” on page 11
•
“Pinlist and Ballmap” on page 25
•
“Package Characteristics” on page 26
•
“Thermal Characteristics” on page 29
Signals
The following conventions are used in the signal description table:
•
Signals with the suffix “_p” are the positive half of a differential pair.
•
Signals with the suffix “_n” are the negative half of a differential pair.
•
Signals with the suffix “_b” are active low.
Signals are classified according to the types defined in Table 1.
Table 1: Signal Types
Pin Type
Definition
I
Input
O
Output
I/O
Input/Output
OD
Open Drain
SRIO
Differential driver/receiver defined by RapidIO
Interconnect Specification (Revision 1.3)
PU
Pulled Up internal to the Tsi577
PD
Pulled Down internal to the Tsi577
LVTTL
CMOS I/O with LVTTL thresholds
CML
Current Mode Logic - Defined by RapidIO Interconnect
Specification (Revision 1.3)
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Table 1: Signal Types (Continued)
Pin Type
Definition
Hyst
Hysteresis
Core Power
Core supply
Core Ground
Ground for core logic
I/O Power
I/O supply
N/C
No connect
These signals must be left unconnected.
1.1.1
Endian Ordering
This document follows the bit-numbering convention adopted by RapidIO Interconnect
Specification (Revision 1.3), where [0:7] is used to represent an 8 bit bus with bit 0 as the
most-significant bit.
1.1.2
Signal Grouping
Figure 1 shows two views of the signals: the ball map view and the port view. The ball map
view shows the pins as they are named in the Tsi577 ball map. The port view shows the signals
on the same balls that are configuration dependent.
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13
Figure 1: Signal Groupings
1
TDO
1
TMS
TRST_b
1
4x Mode Signals
SP0_T[A,B,C,D]_[p,n]
SP0_T[A,B,C,D]_[p,n]
SP0_R[A,B,C,D]_[p,n]
SP0_R[A,B,C,D]_[p,n]
1
SP0_REXT
SP0_REXT
1
SP0_MODESEL
SP0_MODESEL
SP{1,8,9}_PWRDN
SP{1,8,9}_PWRDN
8
1
TDI
Port View
4x Mode Signals
8
1
TCK
Ballmap View
JTAG
TAP
3
1
BCE
2
I2C_SCLK
I2C_SD
I2C_DISABLE
I2C_MA
I2C_SEL
I2C_SA[1,0]
1
Ports
4x Mode: 0
1x Mode: 0,1,8,9
1
2
2
1
2
1
2
IC
2
1
2
2
2
2
MCES
1
1
HARD_RST_b
SW_RST_b
INT_b
Multicast Event
Control Symbol
Reset
SP0_MODESEL
SP{1,8,9}_PWRDN
SP{1,8,9}_PWRDN
1
Interrupt
8
2
Ref Clk
Ports
4x Mode: 2
1x Mode: 2,3,10,11
4
Ports{0,2,4,6}
SP_VDD
4
Ports{0,2,4,6}
SP_AVDD
2
1
4x Mode Signals
2
SP2_R[A,B,C,D]_[p,n]
SP2_REXT
SP2_REXT
1
SP2_MODESEL
SP2_MODESEL
SP{2,3,10,11}_PWRDN
SP{2,3,10,11}_PWRDN
1x Mode Signals
1x Mode Signals
SP2_TA _ [p,n]
SP2_ T A _ [p,n]
SP2_RA _ [p,n]
SP2_ RA _ [p,n]
SP2_TB _ [p,n]
SP3_ T A _ [p,n]
SP2_RB _ [p,n]
SP3_ RA _ [p,n]
2
SP10_ T A _ [p,n]
SP10_ T A _ [p,n]
2
SP10_ R A _ [p,n]
SP10_ R A _ [p,n]
SP10_ T B _ [p,n]
SP11 _ T A _ [p,n]
2
SP10_ R B _ [p,n]
SP11 _ R A _ [p,n]
1
SP2_REXT
SP2_REXT
1
SP2_MODESEL
SP2_MODESEL
SP{2,3,10,11}_PWRDN
SP{2,3,10,11}_PWRDN
2
2
Device
Configuration
SP4_T[A,B,C,D]_[p,n]
SP4_T[A,B,C,D]_[p,n]
8
SP4_R[A,B,C,D]_[p,n]
8
SP4_REXT
SP4_REXT
SP4_MODESEL
SP{4,5,12,13}_PWRDN
SP{4,5,12,13}_PWRDN
1x Mode Signals
1x Mode Signals
1
1
SP6_R[A,B,C,D]_[p,n]
SP6_REXT
SP6_REXT
1
SP6_MODESEL
SP6_MODESEL
SP{6,7,14,15}_PWRDN
SP{6,7,14,15}_PWRDN
2
2
2
4
2
2
2
SP4_T A_ [p,n]
SP4_T A _ [p,n]
2
SP4_RA_ [p,n]
SP4_RA _ [p,n]
2
SP5_T A_ [p,n]
SP4_T B _ [p,n]
2
SP5_RA_ [p,n]
SP4_RB _ [p,n]
2
SP12_T A _ [p,n]
SP12_T A _ [p,n]
2
SP12_RA _ [p,n]
SP12_RA _ [p,n]
2
SP13_T A _ [p,n]
SP12_T B _ [p,n]
2
SP13_RA _ [p,n]
SP12_RB _ [p,n]
2
SP4_REXT
SP4_REXT
SP4_MODESEL
SP4_MODESEL
SP{4,5,12,13}_PWRDN
SP{4,5,12,13}_PWRDN
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Ports
4x Mode: 4
1x Mode: 4,5,12,13
1x Mode Signals
1x Mode Signals
SP6_T A _ [p,n]
SP6 _T A _ [p,n]
SP6_RA _ [p,n]
SP6 _RA _ [p,n]
SP6_T B _ [p,n]
SP7 _T A _ [p,n]
SP6_RB _ [p,n]
SP7 _RA _ [p,n]
SP6_T C_ [p,n]
SP14 _T A _ [p,n]
SP6_RC_ [p,n]
SP14 _RA _ [p,n]
SP6_T D_ [p,n]
SP15 _T A _ [p,n]
SP6_RD_ [p,n]
SP15 _RA _ [p,n]
1
SP6_REXT
SP6_REXT
1
SP6_MODESEL
SP6_MODESEL
SP{6,7,14,15}_PWRDN
SP{6,7,14,15}_PWRDN
4
1
4x Mode Lane Swap
4x Mode Signals
SP6_T[A,B,C,D]_[p,n]
SP6_R[A,B,C,D]_[p,n]
2
Ports
4x Mode: 6
1x Mode: 6,7,14,15
4x Mode Signals
SP6_T[A,B,C,D]_[p,n]
1
4
SP4_R[A,B,C,D]_[p,n]
SP4_MODESEL
Tsi576 / Tsi577-Z Compatibility
4x Mode Signals
SP2_T[A,B,C,D]_[p,n]
SP2_R[A,B,C,D]_[p,n]
2
Supply Rails
4x Mode Signals
SP2_T[A,B,C,D]_[p,n]
1
8
4x Mode Signals
SP9 _T A _ [p,n]
SP0_MODESEL
8
Ballmap View
SP8_RA _ [p,n]
SP0_T D_ [p,n]
1
4
Port View
SP8_T A _ [p,n]
SP0_RC_ [p,n]
SP9 _RA _ [p,n]
3
REF _AVDD
COMP_MODE[1:0]
SP1 _RA _ [p,n]
SP0_T C_ [p,n]
SP0_REXT
2
SP_CLK_SEL
SP1 _T A _ [p,n]
SP0_RB _ [p,n]
SP0_REXT
2
SP_IO_SPEED[1:0]
SP0 _RA _ [p,n]
SP0_T B _ [p,n]
1
VSS
VDD
VDD_IO
SP_AVDD
SP0 _T A _ [p,n]
SP0_RA _ [p,n]
SP0_RD_ [p,n]
4
SP_VDD
1x Mode Signals
1
8
S_CLK_[p,n]
1x Mode Signals
SP0_T A _ [p,n]
1
TX_SWAP
RX_SWAP
1
1
4
Tsi577 Hardware Manual
May 18, 2012
14
The signals shown in Table 2 are described using the port view information (4x mode) in
Figure 1. The ball map view in the figure is to show compatibility with the Tsi576 and Tsi577-Z
devices.
Table 2: Signal Descriptions and Recommended Termination
Pin Name
Type
Description
Recommended
Terminationa
PORT n = 1x/4x Mode Serial RapidIO
PORT m = 1x Mode Serial RapidIO
n = 0, 2, 4, 6
m = n+1, n+8, n+9 for each value of n
Serial Port Transmit
SP{n}_TA_p
O, SRIO
Port n Lane A Differential Non-inverting Transmit
Data output (4x mode)
No termination required.
Port n Differential Non-inverting Transmit Data
output (1x mode)
SP{n}_TA_n
O, SRIO
Port n Lane A Differential Inverting Transmit Data
output (4x mode)
No termination required.
Port n Differential Inverting Transmit Data output
(1x mode)
SP{n}_TB_p
O, SRIO
Port n Lane B Differential Non-inverting Transmit
Data output (4x mode)
Port m (=n+1) Differential Non-inverting Transmit
Data output (1x mode)
No termination required.
SP{n}_TB_n
O, SRIO
Port n Lane B Differential Inverting Transmit Data
output (4x mode)
Port m (=n+1) Differential Inverting Transmit Data
output (1x mode)
No termination required.
SP{n}_TC_p
O, SRIO
Port n Lane C Differential Non-inverting Transmit
Data output (4x mode)
Port m (=n+8) Differential Non-inverting Transmit
Data output (1x mode)
No termination required.
SP{n}_TC_n
O, SRIO
Port n Lane C Differential Inverting Transmit Data
output (4x mode)
Port m (=n+8) Differential Inverting Transmit Data
output (1x mode)
No termination required.
SP{n}_TD_p
O, SRIO
Port n Lane D Differential Non-inverting Transmit
Data output (4x mode)
Port m (=n+9) Differential Non-inverting Transmit
Data output (1x mode)
No termination required.
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Table 2: Signal Descriptions and Recommended Termination
Recommended
Terminationa
Pin Name
Type
Description
SP{n}_TD_n
O, SRIO
Port n Lane D Differential Inverting Transmit Data
output (4x mode)
Port m (=n+9) Differential Inverting Transmit Data
output (1x mode)
No termination required.
I, SRIO
Port n Lane A Differential Non-inverting Receive
Data input (4x node)
DC blocking capacitor of
0.1uF in series
Serial Port Receive
SP{n}_RA_p
Port n Differential Non-inverting Receive Data
input (1x mode)
SP{n}_RA_n
I, SRIO
Port n Lane A Differential Inverting Receive Data
input (4x mode)
DC blocking capacitor of
0.1uF in series
Port n Differential Inverting Receive Data input (1x
mode)
SP{n}_RB_p
I, SRIO
Port n Lane B Differential Non-inverting Receive
Data input (4x mode)
Port m (=n+1) Differential Non-inverting Receive
Data input (1x mode)
DC blocking capacitor of
0.1uF in series
SP{n}_RB_n
I, SRIO
Port n Lane B Differential Inverting Receive Data
input (4x mode)
Port m (=n+1) Differential Inverting Receive Data
input (1x mode)
DC blocking capacitor of
0.1uF in series
SP{n}_RC_p
I, SRIO
Port n Lane C Differential Non-inverting Receive
Data input (4x mode)
Port m (=n+8) Differential Non-inverting Receive
Data input (1x mode)
DC blocking capacitor of
0.1uF in series
SP{n}_RC_n
I, SRIO
Port n Lane C Differential Inverting Receive Data
input (4x mode)
Port m (=n+8) Differential Inverting Receive Data
input (1x mode)
DC blocking capacitor of
0.1uF in series
SP{n}_RD_p
I, SRIO
Port n Lane D Differential Non-inverting Receive
Data input (4x mode)
Port m (=n+9) Differential Non-inverting Receive
Data input (1x mode)
DC blocking capacitor of
0.1uF in series
SP{n}_RD_n
I, SRIO
Port n Lane D Differential Inverting Receive Data
input (4x mode)
Port m (=n+9) Differential Inverting Receive Data
input (1x mode)
DC blocking capacitor of
0.1uF in series
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Table 2: Signal Descriptions and Recommended Termination
Pin Name
Recommended
Terminationa
Type
Description
SP{n}_REXT
I
Used to connect a resistor to VSS to provide a
reference current for the driver and equalization
circuits.
Series resistor of 191
(1%) connected to VSS.
SPn_MODESEL
I/O,
LVTTL,
Selects the operating mode for all four serial ports
within a given MAC n (n = {0,2,4,6})
PD
0 = MAC n operating in 4x+0x+0x+0x mode as
described in section “4x + 0x + 0x + 0x
Configuration” on page 77
Pin must be tied off
according to the required
configuration. Either a 10K
pull up to VDD_IO or a
10K pull-down to VSS.
Serial Port Configuration
(PWRUP)
1 = MAC n operating in 1x+1x+1x+1x mode as
described in section “1x + 1x + 1x + 1x
Configuration” on page 77
Internal pull-down may be
used for logic 0.
Note: The MAC_MODE in the “SRIO MAC x
Digital Loopback and Clock Selection Register” on
page 407 overrides and determine the operating
mode for the corresponding ports.
Output capability of this pin is only used in test
mode.
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17
Table 2: Signal Descriptions and Recommended Termination
Pin Name
Type
Description
SP{n}_PWRDN
I/O,
LVTTL,
Port n Transmit and Receive Power Down Control
(where n = {2, 4, 6})
PU
This signal controls the state of Port n inside a
given MAC n.
(PWRUP)
If Port n is in 4X mode, then the SPn_PWRDN
controls the state of all four lanes (A/B/C/D) of
SerDes Macro.
Recommended
Terminationa
Pin must be tied off
according to the required
configuration. Either a 10K
pull up to VDD_IO or a
10K pull-down to VSS.
Internal pull-up may be
used for logic 1.
If Port n is in 1X mode, related port m are
controlled by SPm_PWRDN. If SPn_PWRDN is
set and all three other ports in the same given
MACn have their SPm_PWRDN set, then the
given MACn SERDES is also powered down.
When n=x, the related m ports are (x+1, x+8,
x+9).
0 = Port n Powered Up
1 = Port n Powered Down
Override SP{n}_PWRDN using PWDN_X4 field in
the “SRIO MAC x Digital Loopback and Clock
Selection Register” on page 407.
Output capability of this pin is only used in test
mode.
SP{m}_PWRDN
(PWRUP)
I/O,
LVTTL,
PU
Port m Transmit and Receive Power Down
Control (where m= {1, 3, 5,
7,8,9,10,11,12,13,14,15})
This signal controls the state of Port m. Note that
Port m is never used when 4x mode is selected
for a Serial Rapid I/O MAC, and it can be powered
down.
Pin must be tied off
according to the required
configuration. Either a 10K
pull up to VDD_IO or a
10K pull-down to VSS.
Internal pull-up may be
used for logic 1.
0 = Port m Powered Up
1 = Port m Powered Down
If SPn is in 1X mode and SPn_PWRDN is set and
all three other ports in the same given MACn have
their SPm_PWRDN set, then the given MACn
SERDES is also powered down.
Override SP{m}_PWRDN using PWDN_X1/X4
field in the “SRIO MAC x Digital Loopback and
Clock Selection Register” on page 407.
Output capability of this pin is only used in test
mode.
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18
Table 2: Signal Descriptions and Recommended Termination
Pin Name
Type
Description
COMP_MODE[1:0]
I, LVTTL,
{PU, PD}
Tsi577 Compatibility Modes
(PWRUP)
These signals are for backward compatibility with
existing devices
00 = Tsi577-Z Replacement (16*1X ports)
01 = Tsi576 Replacement (2*4X + 8*1X)
10 = Tsi577 (default)
11 = Reserved
Recommended
Terminationa
Pin must be tied off
according to the required
configuration. Either a 10K
pull up to VDD_IO or a
10K pull-down to VSS.
Internal pull-up/pull-down
may be used for default
setting of 2’b10
For further detail refer to “Tsi577 Compatibility
Modes” on page 25.
Serial Port Speed Select
SP_IO_SPEED[1]
(PWRUP)
I/O,
LVTTL,
PU
Serial Port Transmit and Receive operating
frequency select. SP_IO_SPEED[1:0], these pin
select the power-up serial port frequency for all
ports.
00 = 1.25Gbit/s
Pin must be tied off
according to the required
configuration. Either a 10K
pull-up to VDD_IO or a
10K pull-down to VSS.
01 = 2.5Gbit/s
Internal pull-up may be
used for logic 1.
10 = 3.125Gbit/s (default)
11 = Illegal
Note; The SP_IO_SPEED[1:0] setting is equal to
theIO_SPEED field in the “SRIO MAC x Digital
Loopback and Clock Selection Register” on
page 407.
Output capability of this pin is only used in test
mode.
SP_IO_SPEED[0]
(PWRUP)
I/O,
LVTTL,
PD
See SP_IO_SPEED[1]
Pin must be tied off
according to the required
configuration. Either a 10K
pull-up to VDD_IO or a
10K pull-down to VSS.
Internal pull-down may be
used for logic 0.
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19
Table 2: Signal Descriptions and Recommended Termination
Pin Name
Type
Description
SP_CLK_SEL
I/O,
LVTTL,
PD
Reference clock speed
(PWRUP)
1 = 125-MHz Reference clock
0 = 156.25-MHz Reference clock
This signal configures the MPLL settings for the
RapidIO SerDes.
Output capability of this pin is only used in test
mode.
Recommended
Terminationa
Pin must be tied off
according to the required
configuration. Either a 10K
pull-up to VDD_IO or a
10K pull-down to VSS.
Internal pull-down may be
used for logic 0.
Serial Port Lane Ordering Select
SP_RX_SWAP
(PWRUP)
I, LVTTL,
PD
Configures the order of 4X receive/transmit lanes
on serial ports.
0 = A, B, C, D
1 = D, C, B, A
Override SP_RX(TX)_SWAP
usingSWAP_RX(TX) field in the “SRIO MAC x
Digital Loopback and Clock Selection Register” on
page 407.
This signal is ignored in 1X mode.
No termination required.
Internal pull-down can be
used for logic 0. Pull up to
VDD_IO through 10K if
external pull-up is desired.
Pull down to VSS through
a 10K resistor if an
external pull-down is
desired.
Note: Ports that require the use of lane swapping
for ease of routing will only function as 4x mode
ports. The re-configuration of a swapped port to
dual 1x mode operation results in the inability to
connect to a 1x mode link partner.
SP_TX_SWAP
(PWRUP)
I, LVTTL,
PD
See SP_RX_SWAP
No termination required.
Internal pull-down can be
used for logic 0. Pull up to
VDD_IO through 10K if
external pull-up is desired.
Pull down to VSS through
10K resistor if an external
pull-down is desired.
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Table 2: Signal Descriptions and Recommended Termination
Pin Name
Type
Description
I,
Differential non-inverting reference clock. The
clock is used for following purposes: SERDES
reference clock, serial port system clock, ISF
clock and test clock. The clock frequency is
defined in the Minimum Clock Frequency
Requirements section.
Recommended
Terminationa
Clock and Reset
S_CLK_p
CML
S_CLK_n
I,
CML
AC coupling capacitor of
0.1uF required.
The maximum frequency of this input clock is
156.25 MHz.
HARD_RST_b
I
LVTTL,
Hyst,
Schmidt-triggered hard reset. Asynchronous
active low reset for the entire device.
Connect to a power-up
reset source. See “Reset
Requirements” on page 66
for more detail.
PU
The Tsi577 does not contain a voltage detector to
generate internal reset.
O, OD,
Interrupt signal (open drain output)
External pull-up required.
Pull up to VDD_IO through
a 10K resistor.
Software reset (open drain output): This signal is
asserted when a RapidIO port receives a valid
reset request on a RapidIO link. If self-reset is not
selected, this pin remains asserted until the reset
request is cleared from the status registers. If
self-reset is selected, this pin remains asserted
until the self reset is complete. If the Tsi577 is
reset from the HARD_RST_b pin, this pin is
de-asserted and remains de-asserted after
HARD_RST_b is released.
External pull-up required.
Pull up to VDD_IO through
a 10K resistor.
Interrupts
INT_b
LVTTL,
2mA
SW_RST_b
O, OD,
LVTTL,
2mA
For more information, refer to “Resets” in the
Tsi577 User’s Manual.
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21
Table 2: Signal Descriptions and Recommended Termination
Pin Name
Type
Description
I/O,
LVTTL,
PD
Multicast Event Symbol pin.
Recommended
Terminationa
Miscellaneous
Multicast
MCES
As an input, an edge (rising or falling) will trigger a
Multicast Event Control Symbol to be sent to all
enabled ports.
As an output, this pin will toggle its value every
time an Multicast Event Control Symbol is
received by any port which is enabled for
Multicast event control symbols.
No termination required.
This pin must not be driven
by an external source until
all power supply rails are
stable.
Refer to section “Multicast-Event Control
Symbols” on page 58 for further details.
I2C
I2C_SCLK
I/O, OD,
LVTTL,
PU
I2C clock, up to 100 kHz.
This clock signal must be connected to the clock
of the serial EEPROM on the I2C bus.
8mA
I2C_SD
I/O, OD,
LVTTL,
PU
Pull up to VDD_IO through
a minimum 470 ohms
resistor if higher edge rate
is required.
I2C input and output data bus (bidirectional open
drain)
8mA
I2C_DISABLE
(PWRUP)
I, LVTTL,
PD
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No termination required.
Internal pull-up may be
used for logic 1.
No termination required.
Internal pull-up may be
used for logic 1.
Pull up to VDD_IO through
a minimum 470 ohms
resistor if higher edge rate
required.
Disable I2C register loading after reset. When
asserted, the Tsi577 will not attempt to load
register values from I2C.
No termination
required.Pull up to
VDD_IO through a 10K
resistor if I2C loading is not
required.
Tsi577 Hardware Manual
May 18, 2012
22
Table 2: Signal Descriptions and Recommended Termination
Recommended
Terminationa
Pin Name
Type
Description
I2C_MA
I, LVTTL,
PU
I2C Multibyte Address
(PWRUP)
2C
When driven high, I module expects multi-byte
peripheral addressing; otherwise, when driven
low, single-byte peripheral address is assumed.
The value on this pin, sets the PA_SIZE field in
“I2C Master Configuration Register” on page 476
and PSIZE field in “I2C Boot Control Register” on
page 496.
I2C_SA[1:0]
(PWRUP)
I, LVTTL,
{PU, PU}
I2C Slave Address pins
The values on these two pins represent the
values for the lower 2 bits of the 7-bit address of
Tsi577 when acting as an I2C slave (field
SLV_ADDR in “I2C Slave Configuration Register”
on page 493).
These pins with I2C_SEL is also used to update
the lower 2 bits of the 7-bit address of the
EEPROM address it boots from (field
BOOT_ADDR in “I2C Boot Control Register” on
page 496) and to access an external slave (field
DEV_ADDR in “I2C Master Configuration
Register” on page 476).
I2C_SEL
(PWRUP)
I, LVTTL,
PU
I2C Pin Select
Together with the I2C_SA[1:0] pins, Tsi577
determines the lower 2 bits of the 7-bit address of
the EEPROM address it boots from.
When asserted, the I2C_SA[1:0] values are also
used as the lower 2 bits of the EEPROM address.
When de-asserted, the I2C_SA[1:0] pins are
ignored and the lower 2 bits of the EEPROM
address default to 00.
No termination required.
Internal pull-up may be
used for logic 1.
Pull up to VDD_IO through
10K resistor if an external
pull-up is desired. Pull
down to VSS to change
the logic state.
No termination required.
Internal pull-up may be
used for logic 1.
Pull up to VDD_IO through
10K resistor if an external
pull-up is desired. Pull
down to VSS to change
the logic state.
No termination required.
Internal pull-up may be
used for logic 1.
Pull up to VDD_IO through
10K resistor if an external
pull-up is desired. Pull
down to VSS to change
the logic state.
JTAG TAP Controller
TCK
Tsi577 Hardware Manual
May 18, 2012
I, LVTTL,
PD
IEEE 1149.1 Test Access Port
Clock input
Pull up to VDD_IO through
10K resistor if not used.
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Table 2: Signal Descriptions and Recommended Termination
Recommended
Terminationa
Pin Name
Type
Description
TDI
I, LVTTL,
PU
IEEE 1149.1 Test Access Port
Serial Data Input
Pull up to VDD_IO through
a 10K resistor if the signal
is not used or a if higher
edge rate is required.
TDO
O,
LVTTL,
IEEE 1149.1 Test Access Port
Serial Data Output
No connect if JTAG is not
used.
8mA
Pull up to VDD_IO through
a 10K resistor if used.
TMS
I, LVTTL,
PU
IEEE 1149.1 Test Access Port
Test Mode Select
Pull up to VDD_IO through
a 10K resistor if not used.
TRST_b
I, LVTTL,
PU
IEEE 1149.1 Test Access Port TAP Reset Input
Tie to VSS through a 10K
resistor if not used.
This input must be asserted during the assertion
of HARD-RST_b. Afterwards, it may be left in
either state.
Combine the HARD_RST_b and TRST_b signals
with an AND gate and use the output to drive the
TRST_b pin.
BCE
I, LVTTL,
PU
Boundary Scan compatibility enabled pin. This
input is used to aid 1149.6 testing.
This signal also enables system level diagnostic
capability using features built into the SerDes.
This signal must be tied to VDD_IO during normal
operation of the device, and during JTAG
accesses of the device registers
This signal should have
the capability to be
pulled-up or pulled-low.
• The default setting is to
be pulled-up.
• Pulling the signal low
enables the signal
analyzer functionality on
the SerDes
• A 10K resistor to
VDD_IO should be used.
Power Supplies
SP_AVDD
-
3.3V supply for bias generator circuitry. This is
required to be a low-noise supply.
Refer to “Decoupling
Requirements” on
page 59.
REF_AVDD
-
Analog 1.2V for Reference Clock (S_CLK_P/N).
Refer to “Decoupling
Requirements” on
page 59.
Clock distribution network power supply.
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Table 2: Signal Descriptions and Recommended Termination
Pin Name
Type
Description
Recommended
Terminationa
Common Supply
VDD_IO
-
Common 3.3V supply for LVTTL I/O
Refer to “Decoupling
Requirements” on
page 59.
VSS
-
Common ground supply for digital logic
Refer to “Decoupling
Requirements” on
page 59.
VDD
-
Common 1.2V supply for digital logic
Refer to “Decoupling
Requirements” on
page 59.
SP_VDD
-
1.2V supply for CDR, Tx/Rx, and digital logic for
all RapidIO ports
Refer to “Decoupling
Requirements” on
page 59.
a. Signals for unused serial ports do not require termination and can be left as N/Cs.
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1.1.3
Tsi577 Compatibility Modes
Table 3 lists the different COMP_MODE[1:0] pin configurations which allow backward pin and
software compatibility with the Tsi576 and Tsi577-Z devices.
•
When Tsi577 is placed in a Tsi577-Z socket, COMP_MODE is automatically set to 00. The
device powers up with all ports (0..15) in x1.
•
When Tsi577 is placed in a Tsi576 socket, COMP_MODE is automatically set to 01
— The Tsi577 powers up with ports 0 and 6 in 4x mode and ports 2 -> 5, 10 -> 13 in 1x
mode (2*x4 + 8*x1). In this case, the maximum 1x mode ports is 12.
•
The default mode for Tsi577 is 10.
— Ports 0, 2, 4, 6 can be 4x mode or all 16 ports (0..15) can be 1x mode.
Table 3: Tsi577 Compatibility Modes
Device ID
COMP_MODE[1:0]
0x577
00
0x577
01
0x577
10
0x577
1.2
11
Max Number of Ports
4x mode
0
1x mode
16
4x mode
2
1x mode
12
4x mode
4
1x mode
16
Port Total
Description
16
Tsi577-Z Replacement
16
Tsi576 Replacement
16
Tsi577 Mode (default)
Reserved
Pinlist and Ballmap
The pinlist and ballmap information for the Tsi577 are available by visiting www.IDT.com and
registering. For more information, see the following documents:
•
Tsi577 Pinlist
•
Tsi577 Ballmap
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26
1.3
Package Characteristics
The Tsi577’s package characteristics are summarized in the following table. Figure 2 and
Figure 3 illustrate the Top and Side views of the Tsi577 package. Figure 4 shows the Bottom
view of the device.
Table 4: Package Characteristics
Feature
Description
Package Type
Heat Slug Ball Grid Array (HSBGA)
Package Body Size
21 mm x 21 mm
JEDEC Specification
95-1 Section 14
Pitch
1.00 mm
Ball pad size
500 um
Soldermask opening
400 um
Moisture Sensitivity Level
3
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Figure 2: Package - Top View
Figure 3: Package - Side View
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Figure 4: Package - Bottom View
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1.4
Thermal Characteristics
Heat generated by the packaged IC has to be removed from the package to ensure that the IC is
maintained within its functional and maximum design temperature limits. If heat buildup
becomes excessive, the IC temperature may exceed the temperature limits. A consequence of
this is that the IC may fail to meet the performance specifications and the reliability objectives
may be affected.
Failure mechanisms and failure rate of a device have an exponential dependence of the IC
operating temperatures. Thus, the control of the package temperature, and by extension the
Junction Temperature, is essential to ensure product reliability. The Tsi577 is specified safe for
operation when the Junction Temperature is within the recommended limits.
Table 5 shows the simulated Theta jb and Theta jc thermal characteristics of the Tsi577 HSBGA
package.
Table 5: Thermal Characteristics of Tsi577
1.4.1
Interface
Result
Theta jb (junction to board)
8.3 C/watt
Theta jc (junction to case)
3.8 C/watt
Junction-to-Ambient Thermal Characteristics (Theta ja)
Table 6 shows the simulated Theta ja thermal characteristic of the Tsi577 package. The results
in Table 6 are based on a JEDEC Thermal Test Board configuration (JESD51-9) and do not
factor in system level characteristics. As such, these values are for reference only.
The Theta ja thermal resistance characteristics of a package depend on multiple
system level variables.
Table 6: Simulated Junction to Ambient Characteristics
Theta ja at specified airflow (no Heat Sink)
Package
0 m/s
1 m/s
2 m/s
Tsi577 HSBGA
12.3 C/watt
11.1 C/watt
10.5 C/watt
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1.4.2
System-level Characteristics
In an application, the following system-level characteristics and environmental issues must be
taken into account:
•
Package mounting (vertical / horizontal)
•
System airflow conditions (laminar / turbulent)
•
Heat sink design and thermal characteristics
•
Heat sink attachment method
•
PWB size, layer count and conductor thickness
•
Influence of the heat dissipating components assembled on the PWB (neighboring effects)
Example on Thermal Data Usage
Based on the ThetaJA data and specified conditions, the following formula can be used to derive
the junction temperature (Tj) of the Tsi577 with a 0m/s airflow:
•
Tj = èJA * P + Tamb.
Where: Tj is Junction Temperature, P is the Power consumption, Tamb is the Ambient
Temperature
Assuming a power consumption (P) of 3 W and an ambient temperature (Tamb) of 70C, the
resulting junction temperature (Tj) would be 106.9C.
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2.
Electrical Characteristics
This chapter provides the electrical characteristics for the Tsi577. It includes the following
information:
2.1
•
“Absolute Maximum Ratings” on page 31
•
“Recommended Operating Conditions” on page 32
•
“Power” on page 33
Absolute Maximum Ratings
Operating the device beyond the operating conditions is not recommended. Stressing the Tsi577
beyond the Absolute Maximum Rating can cause permanent damage.
Table 7 lists the absolute maximum ratings.
Table 7: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Tstorage
Storage Temperature
-55
125
C
VDD_IO
3.3 V DC Supply Voltage
-0.5
4.6
V
3.3 V Analog Supply Voltage
-0.5
4.6
V
1.2 V DC Supply Voltage
-0.3
1.7
V
VI_SP{n}-R{A-D}_{p,n}
SERDES Port Receiver Input Voltage
-0.3
3
V
VO_SP{n}-T{A-D}_{p,n}
SERDES Port VM Transmitter Output Voltage
-0.3
3
V
SP_AVDD
VDD, SP_VDD,
REF_AVDD
SP_AVDD
Transient di/dt
-
0.0917
A/nS
SP_VDD
Transient di/dt
-
0.136
A/nS
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32
Table 7: Absolute Maximum Ratings
2.2
Symbol
Parameter
Min
Max
Unit
VO_LVTTL
LVTTL Output or I/O Voltage
-0.5
VDD_IO +0.5
V
VESD_HBM
Maximum ESD Voltage Discharge Tolerance
for Human Body Model (HBM). [Test
Conditions per JEDEC standard JESD22-A114-B]
-
2000
V
VESD_CDM
Maximum ESD Voltage Discharge Tolerance
for Charged Device Model (CDM). Test
Conditions per JEDEC standard JESD22-C101-A
-
500
V
Recommended Operating Conditions
Table 8 lists the recommended operating conditions.
Continued exposure of Tundra's devices to the maximum limits of the specified
junction temperature could affect the device reliability. Subjecting the devices to
temperatures beyond the maximum/minimum limits could result in a permanent
failure of the device.
Table 8: Recommended Operating Conditions
Symbol
Min
Max
Unit
Junction temperature
-40
125
C
3.3 V DC Supply Voltage
2.97
3.63
V
3.3 V Analog Supply Voltage
2.97
3.63
V
VDD,SP_VDD,
REF_AVDD
1.2 V DC Supply Voltage
1.14
1.29
V
IVDD_IO
3.3 V IO Supply Currenta
-
15
mA
ISP_VDD
SerDes Digital Supply Currenta
-
570b
mA
ISP_AVDD
3.3 V SerDes Supply Currenta
-
840b
mA
1.2 V Core Supply Currenta
-
2007b
mA
1.2 V Ref Clock Supply Current
-
12.5
mA
Power Supply ripple for Voltage Supplies:
SP_VDD, VDD and VDD_IO
-
100
mVpp
Tj
VDD_IO
SP_AVDD
IVDD
IREF_AVDD
Vripple1
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33
Table 8: Recommended Operating Conditions
Symbol
Vripple2
IREXT
Parameter
Min
Max
Unit
Power Supply ripple for Voltage Supplies:
SP_AVDD, REF_AVDD
-
50
mVpp
External reference resistor current
-
10
uA
a. The current values provided are maximum values and dependent on device configuration, such as port
usage, traffic, etc.
b. These values are estimates and will be updated in a future revision of the documentation.
2.3
Power
The following sections describe the Tsi577’s power dissipation and power sequencing.
2.3.1
Power Dissipation
The power dissipation values provided are dependent on device configuration. The line rate,
port configuration, traffic all impact the Tsi577’s power consumption.
1x Mode
Table 9: Tsi577 Power Dissipation in 1x Mode, 16 Links in Operation
Line Rate
1.25 GBaud
2.5 GBaud
3.125 GBaud
VDD_CORE
0.768
1.158
1.334
SP_VDD
0.410
0.406
0.483
SP_AVDD
0.832
0.823
0.864
VDD_IO
0.005
0.004
0.004
Power (W)
2.015
2.390
2.685
Secondary Port Power W)
0.043
0.061
0.066
Primary Port Power (W)
0.303
0.342
0.401
Table 9 Notes:
•
Power is provided for typical process and voltage, and 25C ambient temperature
•
VDD_CORE supplies the ISF and other internal digital logic
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34
•
SP_VDD supplies the digital portion of the Serial RapidIO SerDes
•
SP_AVDD supplies the analog portion of the Serial RapidIO SerDes
•
VDD_IO supplies power for all non-Serial RapidIO I/O
•
Power is modeled for link utilization of approximately 25%
•
SerDes I/O drive parameters are set to default values in the SRIO MAC x SerDes
Configuration Channel register (TX_BOOST) and the SRIO MAC x SerDes Configuration
Global register (Tx_LVL)
•
The primary port associated with each SerDes must be enabled before any secondary ports
can be used
4x Mode
Table 10: Tsi577 Power Dissipation in 4x Mode, 4 Links in Operation
Line Rate
1.25 GBaud
2.5 GBaud
3.125 GBaud
VDD_CORE
0.467
0.633
0.717
SP_VDD
0.407
0.433
0534
SP_AVDD
0.837
0.838
0.926
VDD_IO
0.005
0.005
0.005
Power (W)
1.716
1.909
2.182
Port Power (W)
0.357
0.405
0.473
Table 10 Notes:
•
Power is provided for typical process and voltage, and 25C ambient temperature
•
VDD_CORE supplies the ISF and other internal digital logic
•
SP_VDD supplies the digital portion of the Serial RapidIO SerDes
•
SP_AVDD supplies the analog portion of the Serial RapidIO SerDes
•
VDD_IO supplies power for all non-Serial RapidIO I/O
•
Power is modeled for link utilization of approximately 25%
•
SerDes I/O drive parameters (TX_ATTEN, TX_BOOST) are set to default values in the
SRIO MAC x SerDes Configuration Channel register
Tsi577 Hardware Manual
May 18, 2012
Tundra Semiconductor Corporation
www.tundra.com
35
2.3.2
Power Sequencing
Power-up option pins that are controlled by a logic device, in addition to all clocks, must not be
driven until all power supply rails to the Tsi577 are stable. External devices also must not be
permitted to sink current from, or source current to, the device because of the risk of triggering
ESD protection or causing a latch-up condition.
The Tsi577 must have the supplies powered-up in the following order:
•
VDD (1.2 V) must be powered up first
•
SP_VDD (1.2 V) and REF_AVDD (1.2 V) should power up at approximately the same
time as VDD
•
Delays between the powering up of VDD, SP_VDD, and REF_AVDD are acceptable.
•
No more than 50ms after VDD is at a valid level, VDD_IO (3.3 V) should be powered up to
a valid level
•
VDD_IO (3.3V) must not power up before VDD (1.2 V)
•
SP_AVDD (3.3V) should power up at approximately the same time as VDD_IO
•
Delays between powering up VDD_IO and SP_AVDD are acceptable
•
SP_AVDD must not power up before SP_VDD
It is recommended that there is no more than 50ms between ramping of the 1.2 V
and 3.3 V supplies. The power supply ramp rates must be kept between 10 V/s and
1x10E6 V/s to minimize power current spikes during power up.
If it is necessary to sequence the power supplies in a different order than that recommended
above, the following precautions must be taken:
2.3.2.1
•
Any power-up option pins must be current limited with 10 K ohms to VDD_IO or VSS as
required to set the desired logic level.
•
Power-up option pins that are controlled by a logic device must not be driven until all
power supply rails to the Tsi577 are stable.
Power-down
Power down is the reverse sequence of power up:
•
VDD_IO (3.3V) and SP_AVDD
•
VDD (1.2V), SP_VDD and REF_AVDD power-down at the same time, or all rails falling
simultaneously.
•
Or all rails falling simultaneously
Tundra Semiconductor Corporation
www.tundra.com
Tsi577 Hardware Manual
May 18, 2012
36
2.4
Electrical Characteristics
This section describes the AC and DC signal characteristics for the Tsi577.
2.4.1
SerDes Receiver (SP{n}_RD_p/n)
Table 11 lists the electrical characteristics for the SerDes Receiver in the Tsi577.
Table 11: SerDes Receiver Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Notes
ZDI
RX Differential Input
impedance
90
100
110
Ohm
-
VDIFFI
RX Differential Input
Voltage
170
-
1600
mV
-
LCR
RX Common Mode
Return Loss
-
-
6
dB
Over a range 100MHz to 0.8* Baud
Frequency
LDR
RX Differential Return
Loss
-
-
10
dB
Over a range 100MHz to 0.8* Baud
Frequency
VLOS
RX Loss of Input
Differential Level
55
-
-
mV
Port Receiver Input level below which
Low Signal input is detected
-
-
24
ns
Between channels in a given x4 port @
1.25/2.5Gb/s
-
-
22
ns
Between channels in a given x4 port @
3.125Gb/s
-
-
160
ps
Between 20% and 80% levels
TRX_ch_skew
RTR,RTF
RX Channel to
Channel Skew
Tolerance
RX Input Rise/Fall
times
Tsi577 Hardware Manual
May 18, 2012
Tundra Semiconductor Corporation
www.tundra.com
37
2.4.2
SerDes Transmitter (SP{n}_TD_p/n)
Table lists the electrical characteristics for the SerDes transmitter in the Tsi577.
Table 12: SerDes Transmitter Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Notes
ZSEO
TX Single-Ended
Output impedance
45
50
55
Ohm
-
ZDO
TX Differential Output
Impedance
90
100
110
Ohm
-
VSW
TX Output Voltage
Swing (Single-ended)
425
-
600
mVp
-p
VSW (in mV) = ZSEO/2 x Inom x
RIdr/Inom, where Ridr/Inom is the Idr to
Inom ratio.
VDIFFO
TX Differential Output
Voltage Amplitude
-
2*VSW
-
mVp
-p
-
VOL
TX Output Low-level
Voltage
-
1.2 VSW
-
V
-
VOH
TX Output High-level
Voltage
-
1.2
-
V
-
VTCM
TX common-mode
Voltage
-
1.2 VSW/2
-
V
-
LDR1
TX Differential Return
Loss
-
-
10
dB
For (Baud
Frequency)/10
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