ZSC31015
RBicdLite™ Analog Output Sensor Signal
Conditioner with Diagnostic Features
Datasheet
Brief Description
Benefits
The ZSC31015 is adjustable to nearly all piezoresistive bridge sensors. Measured and corrected
bridge values are provided at the SIG™ pin, which
can be configured as an analog voltage output or as
a one-wire serial digital output.
No external trimming components required
Simple PC-controlled configuration and
calibration via one-wire interface
High accuracy: ±0.1% FSO @ -25 to 85°C;
±0.25% FSO @ -50 to 150°C
The digital one-wire interface (OWI) can be used for
a simple PC-controlled calibration procedure to program a set of calibration coefficients into an on-chip
EEPROM. The calibrated ZSC31015 and a specific
sensor are mated digitally: fast, precise, and without
the cost overhead associated with trimming by
external devices or laser. Integrated diagnostics
functions make the ZSC31015 particularly well
suited for automotive applications.*
Single-pass calibration – quick and precise
Available Support
Evaluation Kit available
Mass Calibration System available
Support for industrial mass calibration available
Quick circuit customization possible for large
production volumes
Features
Physical Characteristics
Digital compensation of sensor offset, sensitivity,
temperature drift, and non-linearity
Programmable analog gain and digital gain;
accommodates bridges with spans < 1mV/V
and high offset
Many diagnostic features on chip (e.g., EEPROM
signature, bridge connection checks, bridge short
detection, power loss detection)
Independently programmable high and low
clipping levels
24-bit customer ID field for module traceability
Internal temperature compensation reference
(no external components)
Option for external temperature compensation
with addition of single diode
Output options: rail-to-rail ratiometric analog
voltage (12-bit resolution), absolute analog
voltage, digital one-wire interface
Fast power-up to data out response; output
available 5ms after power-up
Current consumption depends on programmed
sample rate: 1mA down to 250A (typical)
Fast response time: 1ms (typical)
High voltage protection up to 30V with
external JFET
© 2016 Integrated Device Technology, Inc
Wide operation temperature: –50°C to +150°C
Supply voltage 2.7 to 5.5V; with external JFET,
5.5 to 30V
Small SOP8 package
ZSC31015 Application Circuit
Vsupply
+2.7 to +5.5 V
VDD
SIG™
OUT/OWI
ZSC31015
VBP
Vgate
VBN
VSS
0.1 F
Ground
* Not AEC-Q100-qualified.
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November 14, 2016
ZSC31015
RBicdLite™ Analog Output Sensor Signal
Conditioner with Diagnostic Features
ZSC31015 Block Diagram
Datasheet
JFET1
(Optional if supply is 2.7 to 5.5 V)
S
0.1 F
Highly Versatile Applications
in Many Markets Including
Industrial
Building Automation
Office Automation
White Goods
Automotive *
Portable Devices
Your Innovative Designs
Vgate
VDD (2.7 to 5.5 V)
Sensor
Diagnostics
RBicdLite
PTAT
Temperature
Reference
VDD
Regulator
VBP
INMUX
PREAMP
Power Save
EEPROM
with Charge
Pump
Ext Temp
(Optional)
Bsink
POR/Oscillator
12-Bit
DAC
ZSC31015
A
VBN
Optional
Ext. Diode
for Temp
5.5 V to 30 V
VSUPPLY
D
_
D
14-Bit ADC
Digital
Core
SIGTM
+
0 V to 1 V
Ratiometric
Rail-to-Rail
OWI/ZACwireTM
OUTBUF1
ZACwireTM
Interface
Power Lost
Diagnostic
Analog Block
Digital Block
VSS
* Not AEC-Q100-qualified.
Rail-to-Rail Ratiometric Voltage Output Applications
Absolute Analog Voltage Output Applications
BSS169
Vsupply
S
+2.7 to +5.5 V
1 Bsink
VSS 8
2 VBP
SigTM 7
3 ExtTemp
4 VBN
Optional Bsink
OUT
VSS 8
2 VBP
SigTM 7
3 ExtTemp
VDD 6
Vgate 5
ZSC31015
1 Bsink
4 VBN
0.1 F
Optional Bsink
D
Vsupply
+5.5 to +30 V
OUT
VDD 6
Vgate 5
0.1 F
ZSC31015
Ground
Ground
Ordering Examples (See section 11 of the data sheet for additional temperature range options.)
Sales Code
Description
Package
ZSC31015EEB
ZSC31015 Die — Temperature range: -50°C to +150°C
Unsawn on Wafer
ZSC31015EEC
ZSC31015 Die — Temperature range: -50°C to +150°C
Sawn on Wafer Frame
ZSC31015EEG1
ZSC31015 SOP8 (150 mil) — Temperature range: -50°C to +150°C
Tube: add “-T” to sales code. Reel: add “-R”
ZSC31015KIT
ZSC31015 ZACwire™ SSC Evaluation Kit: Communication Board, SSC Board, Sensor
Replacement Board, USB Cable, 5 IC Samples (SOP8 150mil)
Kit
(ZACwire™ SSC Evaluation Software can be downloaded from www.IDT.com/ZSC31015)
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ZSC31015 Datasheet
Contents
1
Electrical Characteristics ................................................................................................................... 7
1.1. Absolute Maximum Ratings ........................................................................................................ 7
1.2. Recommended Operating Conditions ......................................................................................... 7
1.3. Electrical Parameters .................................................................................................................. 8
1.3.1. Supply/Regulation Characteristics ........................................................................................ 8
1.3.2. Parameters for Analog Front-End (AFE) ............................................................................... 8
1.3.3. Parameters for EEPROM ...................................................................................................... 8
1.3.4. Parameters for A/D Converter ............................................................................................... 8
1.3.5. Parameters for Analog Output (DAC and Buffer) .................................................................. 8
1.3.6. Diagnostics ............................................................................................................................ 9
1.3.7. External Temperature Measurement..................................................................................... 9
1.3.8. Parameters for ZACwire™ Serial Interface ........................................................................... 9
1.3.9. Parameters for System Response ........................................................................................ 9
1.4. Analog Inputs versus Output Resolution ................................................................................... 10
2 Circuit Description ........................................................................................................................... 13
2.1. Signal Flow and Block Diagram ................................................................................................ 13
2.2. Analog Front End ...................................................................................................................... 14
2.2.1. Bandgap/PTAT and PTAT Amplifier.................................................................................... 14
2.2.2. Bridge Supply ...................................................................................................................... 14
2.2.3. PREAMP Block ................................................................................................................... 14
2.2.4. Analog-to-Digital Converter (ADC) ...................................................................................... 15
2.3. Digital Signal Processor ............................................................................................................ 15
2.3.1. EEPROM ............................................................................................................................. 17
2.3.2. One-Wire Interface – ZACwire™......................................................................................... 17
2.4. Output Stage ............................................................................................................................. 17
2.4.1. Digital to Analog Converter (Output DAC) with Programmable Clipping Limits .................. 17
2.4.2. Output Buffer ....................................................................................................................... 18
2.4.3. Voltage Reference Block ..................................................................................................... 18
2.5. Clock Generator / Power-On Reset (CLKPOR) ........................................................................ 20
2.5.1. Trimming the Oscillator ....................................................................................................... 20
2.6. Diagnostic Features .................................................................................................................. 20
2.6.1. EEPROM Integrity ............................................................................................................... 21
2.6.2. Sensor Connection Check................................................................................................... 21
2.6.3. Sensor Short Check ............................................................................................................ 22
2.6.4. Power Loss Detection ......................................................................................................... 22
2.6.5. ExtTemp Connection Checks .............................................................................................. 22
3 Functional Description ..................................................................................................................... 23
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ZSC31015 Datasheet
3.1. General Working Mode ............................................................................................................. 23
3.2. ZACwire™ Communication Interface ........................................................................................ 25
3.2.1. Properties and Parameters ................................................................................................. 25
3.2.2. Bit Encoding ........................................................................................................................ 25
3.2.3. Write Operation from Master to ZSC31015 ......................................................................... 26
3.2.4. ZSC31015 Read Operations ............................................................................................... 26
3.2.5. High Level Protocol ............................................................................................................. 29
3.3. Command/Data Bytes Encoding ............................................................................................... 30
3.4. Calibration Sequence ................................................................................................................ 31
3.5. EEPROM Bits............................................................................................................................ 33
3.6. Calibration Math ........................................................................................................................ 37
3.6.1. Correction Coefficients ........................................................................................................ 37
3.6.2. Interpretation of Binary Numbers for Correction Coefficients .............................................. 37
3.7. Reading EEPROM Contents ..................................................................................................... 41
4 Application Circuit Examples ........................................................................................................... 42
4.1. Three-Wire Rail-to-Rail Ratiometric Output .............................................................................. 42
4.2. Absolute Analog Voltage Output ............................................................................................... 43
4.3. Three-Wire Ratiometric Output with Over-Voltage Protection .................................................. 44
4.4. Digital Output ............................................................................................................................ 44
4.5. Output Resistor/Capacitor Limits .............................................................................................. 44
5 EEPROM Restoration ..................................................................................................................... 45
5.1. Default EEPROM Contents ....................................................................................................... 45
5.1.1. Osc_Trim ............................................................................................................................. 45
5.1.2. 1V_Trim/JFET_Trim ............................................................................................................ 45
5.2. EEPROM Restoration Procedure .............................................................................................. 45
6 Pin Configuration and Package ....................................................................................................... 47
7 ESD/Latch-Up-Protection ................................................................................................................ 48
8 Test ................................................................................................................................................. 48
9 Quality and Reliability ...................................................................................................................... 48
10 Customization ................................................................................................................................. 48
11 Part Ordering Codes ....................................................................................................................... 49
12 Related Documents ......................................................................................................................... 49
13 Definitions of Acronyms................................................................................................................... 50
14 Document Revision History ............................................................................................................. 51
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ZSC31015 Datasheet
List of Figures
Figure 2.1
Figure 2.2
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Figure 3.5
Figure 3.6
Figure 3.7
Figure 3.8
Figure 3.9
Figure 4.1
Figure 4.2
Figure 4.3
Figure 5.1
Figure 6.1
ZSC31015 Block Diagram ..................................................................................................................13
DAC Output Timing for Highest Update Rate .....................................................................................18
General Working Mode .......................................................................................................................24
Manchester Duty Cycle.......................................................................................................................25
19-Bit Write Frame ..............................................................................................................................26
Read Acknowledge .............................................................................................................................26
Digital Output (NOM) Bridge Readings ..............................................................................................27
Digital Output (NOM) Bridge Readings with Temperature .................................................................27
Read EEPROM Contents ...................................................................................................................28
Transmission of a Number of Data Packets .......................................................................................28
ZACwire™ Output Timing for Lower Update Rates............................................................................29
Rail-to-Rail Ratiometric Voltage Output – Temperature Compensation via External Diode ..............42
Absolute Analog Voltage Output – Temperature Compensation via Internal Temperature PTAT with
External JFET Regulation ...................................................................................................................43
Ratiometric Output, Temperature Compensation via Internal Diode..................................................44
EEPROM Validation and Restoration Procedure ...............................................................................46
ZSC31015 Pin-Out Diagram ...............................................................................................................47
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ZSC31015 Datasheet
List of Tables
Table 1.1
Table 1.2
Table 1.3
Table 1.4
Table 2.1
Table 2.2
Table 2.3
Table 3.1
Table 3.2
Table 3.3
Table 3.4
Table 3.5
Table 3.6
Table 3.7
Table 3.8
Table 3.9
Table 3.10
Table 3.11
Table 6.1
Table 6.2
ADC Resolution Characteristics for an Analog Gain of 6 ...................................................................10
ADC Resolution Characteristics for an Analog Gain of 24 .................................................................11
ADC Resolution Characteristics for an Analog Gain of 48 .................................................................11
ADC Resolution Characteristics for an Analog Gain of 96 .................................................................12
1V Reference Trim (1V vs. Trim for Nominal Process Run) ...............................................................19
Oscillator Trimming .............................................................................................................................20
Summary of Diagnostic Features .......................................................................................................21
Pin Configuration and Latch-Up Conditions .......................................................................................25
Special Measurement/Idle Time between Packets versus Update Rate ...........................................28
Total Transmission Time for Different Update Rate Settings and Output Configuration....................29
Command/Data Bytes Encoding.........................................................................................................30
ZSC31015 EEPROM Bits ...................................................................................................................33
Correction Coefficients .......................................................................................................................37
Gain_B [13:0] Weightings ...................................................................................................................38
Offset_B Weightings ...........................................................................................................................38
Gain_T Weightings .............................................................................................................................39
Offset_T Weightings ...........................................................................................................................39
EEPROM Read Order ........................................................................................................................41
Storage and Soldering Conditions for SOP-8 Package ......................................................................47
ZSC31015 Pin Configuration ..............................................................................................................47
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ZSC31015 Datasheet
1
Electrical Characteristics
1.1.
Absolute Maximum Ratings
Note: The absolute maximum ratings are stress ratings only. The device might not function or be operable above
the operating conditions given in section 1.2. Stresses exceeding the absolute maximum ratings might also
damage the device. In addition, extended exposure to stresses above the recommended operating conditions
might affect device reliability. IDT does not recommend designing to the “Absolute Maximum Ratings.”
Parameter
Symbol
Min
Max
Unit
Analog Supply Voltage
VDD
Voltages at Analog I/O – In Pin
VINA
-0.3
6.0
V
-0.3
VDD+0.3
V
Voltages at Analog I/O – Out Pin
VOUTA
-0.3
VDD+0.3
V
Storage Temperature Range (10 hours)
TSTOR
-50
150
°C
Storage Temperature Range ( Start the Command Mode; used to enter Command Interpret Mode.
60HEX
YYHEX
Program SOT (2nd Order Term)
70HEX
YYHEX
Program TSETL (Set the MSB to 0.)
For more details, refer to section 3.7.
For more details, refer to section 3.5.
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ZSC31015 Datasheet
Command
Byte
Data
Description
80HEX
YYHEX
Program Gain_B upper 7-bits (Set the MSB to 0.)
90HEX
YYHEX
Program Gain_B lower 8-bits
A0HEX
YYHEX
Program Offset_B upper 6-bits (Set the two MSBs to 0.)
B0HEX
YYHEX
Program Offset_B lower 8-bits
C0HEX
YYHEX
Program Gain_T
D0HEX
YYHEX
Program Offset_T
E0HEX
YYHEX
Program Tco
F0HEX
YYHEX
Program Tcg
08HEX
YYHEX
Program Upper Clipping Limit (Set the MSB to 0.)
18HEX
YYHEX
Program Lower Clipping Limit (Set the MSB to 0.)
28HEX
YYHEX
Program Cust_ID0
38HEX
YYHEX
Program Cust_ID1
48HEX
YYHEX
Program Cust_ID2
3.4.
Calibration Sequence
Although the ZSC31015 can work with many different types of resistive bridges, assume a pressure bridge is
being used for the following discussion on calibration.
Calibration essentially involves collecting raw bridge and temperature data from the ZSC31015 for different known
pressures and temperatures. This raw data can then be processed by the calibration master (typically a PC) to
compute the coefficients, and the calculated coefficients can then be written to the ZSC31015.
IDT can provide software and hardware with samples to perform the calibration.
There are three main steps to calibration:
1.
Assigning a unique identification to the ZSC31015. This identification is programmed in EEPROM and
can be used as an index into the database stored on the calibration PC. This database will contain all the
raw values of bridge readings and temperature readings for that part, as well as the known pressure (for
this application) and temperature the bridge was exposed to. This unique identification can be stored in a
concatenation of the following EEPROM registers: Cust_ID0, Cust_ID1, Cust_ID2. These registers can
also form a permanent serial number.
2. Data collection. Data collection involves getting raw data from the bridge at different known pressures and
temperatures. This data is then stored on the calibration PC using the unique identification of the
ZSC31015 as the index to the database.
3. Coefficient calculation and write. Once enough data points have been collected to calculate all the
desired coefficients then the coefficients can be calculated by the calibrating PC and written to the
ZSC31015.
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ZSC31015 Datasheet
Step 1 – Assigning Unique Identification
Assigning a unique identification number is as simple as using the commands Program Cust_ID0, Program
Cust_ID1 and Program Cust_ID2. These three 8-bit registers allow for more than 16 million unique devices.
Gain_B must be programmed to 800HEX (unity) and Gain_T must be programmed to 80HEX (unity).
Step 2 – Data Collection
The number of unique (pressure, temperature) points that calibration must be performed at depends on the user’s
needs. The minimum is a 2-point calibration, and the maximum is a 5-point calibration. To acquire raw data from
the part, set the ZSC31015 to enter Raw Mode. This is done by issuing a Start_CM (Start Command Mode
5090HEX) command/data pair to the ZSC31015 followed by a Start_RM (Start Raw Mode 4010HEX) command/data
pair with the LSB of the upper data nibble set. Now if the Gain_B term has been set to unity (800 HEX) and the
Gain_T term has also been set to unity (80HEX), then the part will be in the Raw Mode and will output raw data on
its SIGTM pin instead of corrected bridge and temperature. Capture several of these data points with the user’s
calibration system (16 each of bridge and temperature is recommended) and average them. Store these raw
bridge and temperature settings in the database along with the known pressure and temperature.
The output format during Raw Mode is Bridge_High, Bridge_Low, Temp. Each of these is an 8-bit quantity. The
upper 2-bits of Bridge_High are zero-filled. The Temp data (8-bits only) would not be enough information for
accurate temperature calibration. Therefore the upper three bits of temperature information are not given, but
rather assumed known. Therefore effectively 11-bits of temperature information are provided in this mode.
Step 3 – Coefficient Calculations
The math to perform the coefficient calculation is very complicated and will not be discussed in detail. There is a
rough overview in section 3.6. IDT will provide software to perform the coefficient calculation. IDT can also
provide source code for the algorithms in a C code format. After the coefficients are calculated, the final step is to
write them to the EEPROM of the ZSC31015.
The number of calibration points required can be as few as two or as many as five. This depends on the precision
desired and the behavior of the resistive bridge in use.
1. 2-point calibration can be used if only a gain and offset term are needed for a bridge with no temperature
compensation for either term.
2. 3-point calibration would be used to obtain 1st order compensation for either a Tco or Tcg term but not
both.
3. 3-point calibration could also be used to obtain 2nd order correction for the bridge but no temperature
compensation of the bridge output.
4. 4-point calibration would be used to obtain 1st order compensation for both Tco and Tcg.
5. 4-point calibration could also be used to obtain 1st order compensation for Tco and a 2nd order correction
for the bridge measurement.
6. 5-point calibration would be used to obtain both 1st order Tco correction and 1st order Tcg correction, plus
a 2nd order correction that could be applied to one and only one of the following: 2nd order Tco, 2nd order
Tcg, or 2nd order bridge.
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ZSC31015 Datasheet
3.5.
EEPROM Bits
Table 3.5 shows the bit order and default settings for the EEPROM, which are programmed through the serial
interface. See section 5 for important information for die/wafer customers.
Table 3.5
EEPROM
Range
2:0
ZSC31015 EEPROM Bits
Description
Osc_Trim
Default
Settings
As of ww08/2009
Notes
0HEX
See section 2.5 for details on oscillator trim.
This default setting
minimizes risk of
communication
failure on start-up.
100 => Fastest
101 => 3 clicks faster than nominal
110 => 2 clicks faster than nominal
111 => 1 click faster than nominal
000 => Nominal
001 => 1 click slower than nominal
010 => 2 clicks slower than nominal
011 => Slowest
(Actual part-specific
factory values for
Osc_Trim are
initially stored in bits
in CUST_ID1 and
CUST_ID2 for applications requiring optimal response time.
See section 5 for
important notes.)
6:3
1V_Trim/JFET_Trim
ssssBIN
See Table 2.1 in the “Voltage Reference Block” section.
where “s” is the partspecific factory bit
setting for the
reference voltage
trim value.
(Back-up copies are
stored in CUST_ID0
for applications requiring accurate
references. See
section 5 for important notes.)
10:7
A2D_Offset
© 2016 Integrated Device Technology, Inc
3HEX
The upper two bits are flip polarity and invert bridge input
(negative gain) respectively. If both are used in conjunction,
negative offset modes can be achieved.
00 => normal polarity, positive gain
01 => normal polarity, negative gain
10 => flip polarity, positive gain
11 => flip polarity, negative gain
The lower two bits form the ADC offset selection.
Offset selection:
11 => [-1/2,1/2] mode bridge inputs
10 => [-1/4,3/4] mode bridge inputs
01 => [-1/8,7/8] mode bridge inputs
00 => [-1/16,15/16] mode bridge inputs
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ZSC31015 Datasheet
EEPROM
Range
Description
Default
Settings
As of ww08/2009
Notes
12:11
Output_Select
2HEX
00 => Digital (3 bytes with parity)
Bridge High {00,[5:0]}
Bridge Low [7:0]
Temp [7:0]
01 => 0-1V Analog
10 => Rail-to-Rail Ratiometric
11 => Digital (2 bytes with parity) (No Temp)
Bridge High {00,[5:0]}
Bridge Low [7:0]
14:13
Update_Rate
2HEX
00 => 1 msec (1kHz)
01 => 5 msec (200Hz)
10 => 25 msec (40Hz)
11 => 125 msec (8 Hz)
16:15
JFET_cfg
3HEX
00 => No JFET regulation (lower power)
01 => No JFET regulation (lower power)
10 => JFET regulation centered around 5.0V
11 => JFET regulation centered around 5.5V (i.e., over-voltage
protection)
31:17
Gain_B
198HEX
Bridge Gain (also see bits 10:7):
Gain_B[14] => multiply x 8
Gain_B[13:0] => 14-bit unsigned number representing a
number in the range [0,8)
45:32
Offset_B
0HEX
Unsigned 14-bit offset for bridge correction
53:46
Gain_T
80HEX
Temperature gain coefficient used to correct PTAT
or ExtTemp reading
61:54
Offset_T
0HEX
Temperature offset coefficient used to correct PTAT
or ExtTemp reading
68:62
TSETL
0HEX
Stores Raw PTAT or ExtTemp reading at temperature in which
low calibration points were taken
76:69
Tcg
0HEX
Coefficient for temperature correction of bridge gain term:
Tcg = 8-bit magnitude of Tcg term. Sign is determined by Tc_cfg
(bits 87:85).
84:77
Tco
0HEX
Coefficient for temperature correction of bridge offset term.
Tco = 8-bit magnitude of Tco term. Sign and scaling are
determined by Tc_cfg (bits 87:85)
87:85
Tc_cfg
0HEX
This 3-bit term determines options for temperature compensation
of the bridge.
Tc_cfg[2] => If set, Tcg is negative
Tc_cfg[1] => Scale magnitude of Tco term by 8, and if SOT
applies to Tco, scale SOT by 8
Tc_cfg[0] => If set, Tco is negative
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ZSC31015 Datasheet
EEPROM
Range
Description
Default
Settings
As of ww08/2009
Notes
95:88
SOT
0HEX
2nd Order Term. This term is a 7-bit magnitude with sign.
SOT[7] = 1 negative
SOT[7] = 0 positive
SOT[6:0] = magnitude [0-127]
This term can apply to a 2nd order Tcg, Tco or bridge correction.
(See Tc_cfg above.)
99:96
{SOT_cfg,
Pamp_Gain}
5HEX
Bits [99:98] = SOT_cfg
00 = SOT applies to Bridge
01 = SOT applies to Tcg
10 = SOT applies to Tco
11 = Prohibited
Bits [97:96] = Pre-Amp Gain
00 => 6
01 => 24 (default setting)
10 => 48
11 => 96
102:100
Diag_cfg
7HEX
This 3-bit term applies to diagnostic features
Diag_cfg[2] enable output short circuit protection.
Diag _cfg[1] enable sensor short checking.
Diag_cfg[0] enables sensor connection checking.
105:103
Lock_ExtTemp
0HEX
EEPROM lock
011 or 110 => locked
All other
=> unlocked
When EEPROM is locked, the internal charge pump is disabled
and the EEPROM can never be programmed again.
Bit 105 (the MSB of this field) is also used for selecting external
temperature measurement.
000,001,010,011=>Internal PTAT used for temp
100,101,110,111=>External diode used for temp
112:106
Up_Clip_Lim
7FHEX
7-bit value used to select an upper clipping limit for the output. It
affects both analog and digital output. The 14-bit upper clipping
limit value is comprised of {11,Up_Clip_Lim[6:0],11111}. 127
different clipping levels are selectable between 75.19% and
100% of VDD.
119:113
Low_Clip_Lim
0HEX
7-bit value used to select a lower clipping limit for the output. It
affects both analog and digital output. The 14-bit lower clipping
limit value is comprised of {00,Low_Clip_Lim[6:0],00000}. 127
different clipping levels are selectable between 0% and 24.8%
of VDD.
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ZSC31015 Datasheet
EEPROM
Range
127:120
Description
Cust_ID0
Default
Settings
As of ww08/2009
ssBIN
where “s” is a partspecific factory bit
setting.
During factory testing, two back-up
copies of the optimal
setting for the
1V_Trim/JFET_Trim
bits are stored in
[123:120] and in
[127:124]. See important notes in
section 5.
135:128
Cust_ID1
xsss xsssBIN
where “s” is a partspecific factory bit
setting and x is
“don’t care.”
During factory testing, two copies of
the optimal setting
for the Osc_Trim
bits are stored in
[130:128] and in
[134:132]. (Also in
Cust_ID2.) See important notes in
section 5.
143:136
Cust_ID2
xxxx xsssBIN
where “s” is a partspecific factory bit
setting and X is
“don’t care.”
During factory testing, a copy of the
optimal setting for
the Osc_Trim bits is
stored in [138:136].
(Also in Cust_ID1.)
See important notes
in section 5.
151:144
**
Signature
Notes
Customer ID byte 0
Can be used to store a customer part identification number.
Caution: If the application requires accurate voltage references,
do not overwrite this byte until completing the procedures in
section 5.
Customer ID byte 1
Can be used to store a customer part identification number.
Caution: If the application requires optimal response time, do not
overwrite this byte until completing the procedures in section 5.
Customer ID byte 2
Can be used to store a customer part identification number.
Caution: If the application requires optimal response time, do not
overwrite this byte until completing the procedures in section 5.
8-bit EEPROM signature. Generated through a LFSR**. This
signature is checked on power-on to ensure integrity of EEPROM
contents.
Linear feedback shift register
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3.6.
Calibration Math
3.6.1.
Correction Coefficients
All terms are calculated external to the ZSC31015 and then programmed to the EEPROM through the serial
interface.
Table 3.6
Correction Coefficients
Coefficient
Gain_B
Offset_B
Gain_T
Offset_T
Description
Gain term used to compensate span of Bridge reading
Offset term used to compensate offset of Bridge reading
Gain term used to compensate span of Temp reading
Offset term used to compensate offset of Temp reading
SOT
Second Order Term. The SOT can be applied as a second order correction term for one of the following:
- Bridge measurement
- Temperature coefficient of offset (Tco)
- Temperature coefficient of gain (Tcg)
The EEPROM bits 99:98 determine what SOT applies to.
TSETL
RAW_PTAT or ExtTemp reading (upper 7-bits) at low temperature at which calibration was performed
(typically room temperature)
Tcg
Temperature correction coefficient of bridge gain term. This term has an 8-bit magnitude and a sign bit
(Tc_cfg[2].
Tco
Temperature correction coefficient of bridge offset term. This term has an 8-bit magnitude, a sign bit
(Tc_cfg[0]), and a scaling bit (Tc_cfg[1]), which can multiply its magnitude by 8.
3.6.2.
Interpretation of Binary Numbers for Correction Coefficients
BR_Raw should be interpreted as an unsigned number in the set [0, 16383] with a resolution of 1.
T_Raw should be interpreted as an unsigned number in the set [0, 16383], with a resolution of 4.
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ZSC31015 Datasheet
3.6.2.1. Gain_B Interpretation
Gain_B should be interpreted as a number in the set [0, 64]. The MSB (bit 14) is a scaling bit that will multiply the
effect of the Gain_B[13:0] term by 8. The remaining bits Gain_B[13:0] represent a number in the range of [0,8)
with Gain_B[13] having a weighting of 4, and each subsequent bit has a weighting of ½ the previous bit.
Table 3.7
Gain_B [13:0] Weightings
Bit Position
Weighting
13
22 = 4
12
21 = 2
11
20 = 1
10
2-1
…
…
3
2-8
2
2-9
1
2-10
0
2-11
Examples:
The binary number: 010010100110001B = 4.6489; Gain_B[14] is 0BIN, so the number represented by
Gain_B[13:0] is not multiplied by 8.
The binary number: 101100010010110B = 24.586; Gain_B[14] is 1BIN, so the number represented by
Gain_B[13:0] is multiplied by 8.
3.6.2.2. Offset_B Interpretation
Offset_B is a 14-bit unsigned binary number. The MSB has a weighting of 8192. The following bits then have a
weighting of: 4096, 2048, 1024 …
Table 3.8
Offset_B Weightings
Bit Position
Weighting
13
8192
12
4096
11
2048
.
.
.
1
21 = 2
0
20 = 1
For example, the binary number 1111 1111 1100 = 4092.
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ZSC31015 Datasheet
3.6.2.3. Gain_T Interpretation
Gain_T should be interpreted as a number in the set [0,2]. Gain_T[7] has a weighting of 1, and each subsequent
bit has a weighting of ½ the previous bit.
Table 3.9
Gain_T Weightings
Bit Position
Weighting
7
20 = 1
6
2-1 = 0.5
5
2-2 = 0.25
4
2-3
3
2-4
2
2-5
1
2-6
0
2-7
3.6.2.4. Offset_T Interpretation
Offset_T is an 8-bit signed binary number in two’s complement form. The MSB has a weighting of -128.
The following bits then have a weighting of 64, 32, 16 …
Table 3.10 Offset_T Weightings
Bit Position
Weighting
7
-128
6
26 = 64
5
25 = 32
4
24 = 16
3
23 = 8
2
22= 4
1
21 = 2
0
20 = 1
For example, the binary number 00101001B = 41.
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ZSC31015 Datasheet
3.6.2.5. Tco Interpretation
Tco is specified as having an 8-bit magnitude with an additional sign bit and a scalar bit (Tc_cfg). When the scalar
bit is set, the signed Tco is multiplied by 8.
Tco Resolution:
Tco Range:
0.175 μV/V/oC
± 44.6 μV/V/oC
(input referred)
(input referred)
If the scaling bit is used, then the above resolution and range are scaled by 8 to give the following results:
Tco Scaled Resolution:
Tco Scaled Range:
1.40 μV/V/oC (input referred)
± 357 μV/V/oC (input referred)
3.6.2.6. Tcg Interpretation
Tcg is specified as an 8-bit magnitude with an additional sign bit (Tc_cfg).
Tcg Resolution:
Tcg Range:
17.0 ppm/oC
±4335 ppm/oC
3.6.2.7. SOT Interpretation
SOT is a 2nd order term that can apply to one and only one of the following: bridge non-linearity correction,
Tco non-linearity correction, or Tcg non-linearity correction.
As it applies to bridge non-linearity correction:
Resolution: 0.25% @ full scale
Range:
+25% @ full scale to -25% @ full scale
(Saturation in internal arithmetic will occur at greater negative nonlinearities.)
As it applies to Tcg:
Resolution: 0.3 ppm/(oC)2
Range:
+/- 38ppm/(oC)2
As it applies to Tco:
2 settings are possible. It is possible to scale the effect of SOT by 8. If Tc_cfg[1] is set, then both Tco and
SOT’s contribution to Tco are multiplied by 8.
Resolution at unity scaling: 1.51nV/V/(oC)2 (input referred)
Range: +/- 0.192V/V/(oC)2 (input referred)
Resolution at 8x scaling: 12.1nV/V/(oC)2 (input referred)
Range: +/- 1.54V/V/(oC)2 (input referred)
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ZSC31015 Datasheet
3.7.
Reading EEPROM Contents
The contents of the entire EEPROM memory can be read out using the Read EEPROM command (00HEX). This
command causes the ZSC31015 to output consecutive bytes on the ZACwire™. After each transmission, the
EEPROM contents are shifted by 8 bits. The bit order of these bytes is given in Table 3.11.
Table 3.11 EEPROM Read Order
Bit 7
Bit 6
Bit 5
Bit 4
Byte 1
Bit 3
Bit 2
Bit 1
Offset_B[7:0]
Byte 2
Gain_T[1:0]
Offset_B[13:8]
Byte 3
Offset_T[1:0]
Gain_T[7:2]
Byte 4
TSETL[1:0]
Offset_T[7:2]
Byte 5
Tcg[2:0]
TSETL[6:2]
Byte 6
Tco[2:0]
Tcg[7:3]
Byte 7
Tc_cfg[2:0]
Tco[7:3]
Byte 8
Byte 9
Bit 0
SOT[7:0]
Lock[0]
Diag_cfg[2:0]
Byte 10
SOT_cfg[3:0]
Up_Clip_Lim[5:0]
Byte 11
Lock[2 :1]
Low_Clip_Lim[6:0]
Byte 12
Cust_ID0[7:0]
Byte 13
Cust_ID1[7:0]
Byte 14
Cust_ID2[7:0]
Byte 15
Signature[7:0]
Byte 16
A2D_Offset[0]
Byte 17
JFET_cfg[0]
1V_Trim[3:0] **
Update_Rate[1:0]
Byte 18
Up_Clip_Lim[6]
Osc_Trim[2:0] **
Output Select[1:0]
Gain_B[6:0]
A2D_Offset[3:1]
JFET_cfg[1]
Byte 19
Gain_B[14:7]
Byte 20
A5HEX
* SOT_cfg/Pamp_Gain
** 1V_Trim/JFET_Trim
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4
Application Circuit Examples
The minimum output analog load resistor is RL= 5k. This optional load resistor can be configured as a pull-up or
pull-down. If it is configured as a pull-down, it cannot be part of the module to be calibrated because this would
prevent proper operation of the ZACwireTM. If a pull-down load is desired, it must be added to system after module
calibration.
There is no output load capacitance needed.
EEPROM contents: OUTPUT_select, Config_JFET_Regulation, 1V_Trim/JFET-Trim.
4.1.
Three-Wire Rail-to-Rail Ratiometric Output
This example shows an application circuit for rail-to-rail ratiometric voltage output configuration with temperature
compensation via an external diode. The same circuitry is applicable for a 0 to 1V absolute analog output.
Figure 4.1 Rail-to-Rail Ratiometric Voltage Output – Temperature Compensation via External Diode
Vsupply
+2.7 to +5.5 V
1 Bsink
VSS 8
2 VBP
SigTM 7
3 ExtTemp
4 VBN
Optional Bsink
OUT
VDD 6
Vgate 5
ZSC31015
0.1 F
Ground
The optional bridge sink allows a power savings of bridge current. The output voltage can be either
Rail-to-rail ratiometric analog output VDD(=Vsupply).
0 to 1V absolute analog output. The absolute voltage output reference is trimmable 1V (+/-3mV) in the
1V Output Mode via a 4-bit EEPROM field. See section 2.4.3).
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4.2.
Absolute Analog Voltage Output
The figure below shows an application circuit for an absolute voltage output configuration with temperature compensation via internal temperature PTAT and external JFET regulation for all industry standard applications.
Figure 4.2 Absolute Analog Voltage Output – Temperature Compensation
via Internal Temperature PTAT with External JFET Regulation
BSS169
S
1 Bsink
VSS 8
2 VBP
SigTM 7
3 ExtTemp
4 VBN
Optional Bsink
D
Vsupply
+5.5 to +30 V
OUT
VDD 6
Vgate 5
ZSC31015
0.1 F
Ground
The output signal range can be one of the following options:
0 to 1 V analog output. The absolute voltage output reference is trimmable: 1 V (+/-3 mV) in the 1 V Output
Mode via a 4-bit EEPROM field (see section 2.4.3).
Rail-to-rail analog output. The on-chip reference for the JFET regulator block is trimmable: 5 V (±15 mV) in
the Ratiometric Output Mode via a 4-bit EEPROM field. (See section 2.4.3).
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ZSC31015 Datasheet
4.3.
Three-Wire Ratiometric Output with Over-Voltage Protection
The figure below shows an application circuit for a ratiometric output configuration with temperature compensation
via an internal diode. In this application, the JFET is used for voltage protection. JFET_cfg (16:15) in the
EEPROM are configured to 5.5V. There is an additional maximum error of 8mV caused by the non-zero rds(on) of
the limiter JFET.
Figure 4.3 Ratiometric Output, Temperature Compensation via Internal Diode
J107 Vishay
S
1 Bsink
VSS 8
2 VBP
SigTM 7
3 ExtTemp
4 VBN
Optional Bsink
D
Vsupply
+5.0 to +5.5 V
OUT
VDD 6
Vgate 5
ZSC31015
0.1 F
Ground
4.4.
Digital Output
For all three circuits, the output signal can also be digital. Depending on the output select bits, the bridge signal or
the bridge signal and temperature signal are sent. For the digital output, no load resistor or load capacity is
necessary. No pull down resistor is allowed. If a line resistor or pull-up resistor is used, the requirement for the
rise time must be met (< 5 s). The ZSC31015 output includes an internal pull up resistor of about 30 k. The
digital output can easily be read by firmware from a microcontroller, and IDT can provide the customer with
software for developing the interface.
4.5.
Output Resistor/Capacitor Limits
The limits for external components depend on the programmed output mode:
Pure Analog Output Mode (calibration is done before): The only limit is the minimum load resistance of 5 k.
Pure Digital Output Mode with end-of-line calibration: The RC time constant of the ZACwire™ line must have
a rise time < 5 µs.
Analog output with digital communication during calibration: The RC time constant of the ZACwire™ line must
have a rise time < 5 µs.
Warning: Any series line resistance forms a voltage divider in conjunction with the pull-up load device. If a series
line resistance is needed, choose a low value relative to the pull-up load device.
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ZSC31015 Datasheet
5
EEPROM Restoration
If needed, the default settings for the ZSC31015 (see Table 3.5) can be reprogrammed as described in section 3.
The following sections describe EEPROM content validation and handling during and/or after system assembly.
Important: During the sawing and dicing process, there is a possibility of the EEPROM contents flipping, and
prevention cannot be guaranteed. This is primarily a concern for the factory trim settings, which are customized to
each part.
The EEPROM default values programmed during the different test levels have been selected so that customer
has the option to refresh/reprogram trim bits that might have flipped during sawing or dicing.
Important: The EEPROM lock is stored in the bit range 105:103. A value of 6HEX or 3HEX will lock the EEPROM
forever by disabling the charge pump needed for EEPROM writing. The complete contents can also be validated
using the EEPROM signature stored in bits [151:144], (see “Signature” in Table 3.5).
5.1.
Default EEPROM Contents
During the wafer level test (wafer/dice delivery) and during final test for SOP8 packaged parts, the EEPROM is
programmed with the default values listed in the Table 3.5. During the wafer level test, the Osc_trim bits [2:0] and
1V_Trim/JFET_Trim trim bits [6:3] are set to die-specific values.
5.1.1.
Osc_Trim
The oscillator frequency is trimmed to a value of 512kHz±20% using the Osc_Trim bit setting. The 3-bit setting is
copied twice to Cust_ID1[134:132] and [130:128] and then a third time to Cust_ID2[138:136] to ensure the factory
settings are retained so that the customer can reprogram these values in the Osc_Trim bit if needed. Based on
the most probable trimming, the default values for the Osc_Trim bits are always set to 0HEX during factory testing
to guarantee communication even if bits have flipped.
5.1.2.
1V_Trim/JFET_Trim
The 5V reference for the JFET regulation is factory trimmed during the final test to 5V±15mV using the 1V_Trim/
JFET_Trim bit setting. The 4-bit setting stored in EEPROM bits [6:3] is copied twice to the Cust_ID0 bits [127:124]
and [123:120] to ensure the factory settings are retained so that the customer can reprogram these values in the
1V_Trim/JFET_Trim bits if needed.
5.2.
EEPROM Restoration Procedure
After module assembly, the EEPROM content should be refreshed. If JFET regulation is not used for the user’s
application and optimized response time is not an important criterion, write the default values shown in Table 3.5
to the EEPROM bit range [143:7] and retain the existing values in the bit range [6:0]. If JFET regulation or
optimized response time is required, the bit restoration procedure shown in the flow chart in Figure 5.1 must be
used to keep the factory settings programmed during the testing. If customer oscillator trimming is required, see
ZSC31015_Tech_Notes_JFET_and_Osc_Trimming_revX.X .pdf for instructions.)
Note: The EEPROM signature is re-calculated and updated after every EEPROM writing.
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ZSC31015 Datasheet
Figure 5.1 EEPROM Validation and Restoration Procedure
Start CM
Restore Factory Trimming?
N
Y
Read EEPROM
Check Osc_Trim bits
[130:128]=[138:136]
Check Osc_Trim bits
[134:132]=[130:128]
Check Osc_Trim bits
[134:132]=[138:136]
N
N
Y
Y
Y
Write
[130:128] to [2:0]
Write
[134:132] to [2:0]
Write
[134:132] to [2:0]
Check JFET_Trim bits
[123:120]=[127:124]
Check JFET_Trim bits
[6:3]=[127:124]
Check JFET_Trim bits
[6:3]=[123:120]
N
Y
Keep bits [6:3]
N
N
Y
Perform New
Osc_Trim
N
Y
Write
[123:120] to[6:3]
Keep bits [6:3]
Perform New
JFET_Trim
Write EEPROM
default values
[143:7]
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ZSC31015 Datasheet
6
Pin Configuration and Package
The standard package of the ZSC31015 is an SOP-8 (3.81 mm / 150 mil body) with a lead-pitch 1.27 mm / 50 mil.
Table 6.1
Storage and Soldering Conditions for SOP-8 Package
Parameter
Symbol
Conditions
Maximum Storage Temperature
Tmax_storage
Less than 10hrs, before mounting
Minimum Storage Temperature:
Tmin_storage
Store in original packing only
Tdrybake
Less than100 hrs total, before
mounting
125
C
Less than 30s
(IPC/JEDEC-STD-020 Standard)
260
C
Maximum Dry-Bake Temperature
Soldering Peak Temperature
Tpeak
Min
Typical
Max
Units
150
C
C
-50
Figure 6.1 ZSC31015 Pin-Out Diagram
Table 6.2
Bsink
1
8
VSS
VBP
2
7
SigTM
ExtTemp
3
6
VDD
VBN
4
5
Vgate
ZSC31015 Pin Configuration
Pin No.
Name
Description
1
Bsink
Optional ground connection for bridge ground; used for power savings
2
VBP
Positive bridge connection
3
ExtTemp
External diode connection
4
VBN
Negative bridge connection
5
Vgate
Gate control for external JFET regulation/over-voltage protection
6
VDD
Supply voltage (2.7 to 5.5 V)
7
Sig™
ZACwire™ interface (analog out, digital out, calibration interface)
8
VSS
Ground supply
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7
ESD/Latch-Up-Protection
All pins have an ESD protection of >4000V and a latch-up protection of 100 mA or of +8V/ –4V (to VSS/VSSA).
ESD protection referenced to the Human Body Model is tested with devices in SOP-8 packages during product
qualification. The ESD test follows the Human Body Model with 1.5kΩ/100pF based on MIL 883, Method 3015.7.
8
Test
The test program is based on this datasheet. The final parameters that are tested during series production are
listed in the tables of section 1.
The digital part of the IC includes a scan path, which can be activated and controlled during wafer test. Further
test support for testing of the analog parts on wafer level is included in the DSP.
9
Quality and Reliability
A reliability investigation according to the in-house non-automotive standard has been performed.
10
Customization
For high-volume applications, which require an upgraded or downgraded functionality compared to the
ZSC31015, IDT can customize the circuit design by adding or removing certain functional blocks.
For this customization, IDT has a considerable library of sensor-dedicated circuitry blocks, which enable IDT to
provide a custom solution quickly. Please contact IDT for further information.
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11
Part Ordering Codes
Please contact IDT Sales for additional information.
Sales Code
Description
Package
ZSC31015EEB
ZSC31015 Die — Temperature range: -50°C to +150°C
Unsawn on Wafer
ZSC31015EEC
ZSC31015 Die— Temperature range: -50°C to +150°C
Sawn on Wafer Frame
ZSC31015EEG1-R
ZSC31015 SOP8 (150 mil) — Temperature range: -50°C to +150°C
Reel
ZSC31015EEG1-T
ZSC31015 SOP8 (150 mil) — Temperature range: -50°C to +150°C
Tube
ZSC31015EAB
ZSC31015 Die — Temperature range: -40°C to +125°C
Unsawn on Wafer
ZSC31015EAC
ZSC31015 Die— Temperature range: -40°C to +125°C
Sawn on Wafer Frame
ZSC31015EAG1-R
ZSC31015 SOP8 (150 mil) — Temperature range: -40°C to +125°C
Reel
ZSC31015EAG1-T
ZSC31015 SOP8 (150 mil) — Temperature range: -40°C to +125°C
Tube
ZSC31015EIB
ZSC31015 Die— Temperature range: -25°C to +85°C
Unsawn on Wafer
ZSC31015EIC
ZSC31015 Die — Temperature range: -25°C to +85°C
Sawn on Wafer Frame
ZSC31015EIG1-R
ZSC31015 SOP8 (150 mil) — Temperature range: -25°C to +85°C
Reel
ZSC31015EIG1-T
ZSC31015 SOP8 (150 mil) — Temperature range: -25°C to +85°C
Tube
ZSC31015KIT
ZSC31015 ZACwire™ SSC Evaluation Kit: Communication Board, SSC Board, Sensor Replacement
Board, USB Cable, 5 IC Samples (SOP8)
Kit
(ZACwire™ SSC Evaluation Software can be downloaded from www.IDT.com/ZSC31015)
Contact IDT Sales for support and sales of IDT’s ZSC31015 Mass Calibration System.
12
Related Documents
Document
ZACwire™ SSC Evaluation Kit Description
ZSC31015 Die Dimensions and Pad Coordinates**
SSC Evaluation Kits Feature Sheet *
(includes ordering codes)
ZSC31010/31015/31050 Application Note – External
Protection Circuitry
IDT Wafer Dicing Guidelines
Visit the ZSC31015 product page (www.IDT.com/ZSC31015) or contact your nearest sales office for the latest version of these
documents.
* Documents marked with an asterisk (*) can be found on the Evaluation Tools page (www.IDT.com).
** Documents marked with two asterisks (**) are available on request.
© 2016 Integrated Device Technology, Inc
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ZSC31015 Datasheet
13
Definitions of Acronyms
Term
Description
ADC
Analog-to-Digital Converter
AFE
Analog Front-End
BUF
Buffer
CM
Command Mode
CMC
Calibration Microcontroller
DAC
Digital-to-Digital Converter
DNL
Differential Nonlinearity
DSP
Digital Signal Processor
DUT
Device Under Test
ESD
Electrostatic Discharge
FSO
Full-Scale Output
INL
Integrated Nonlinearity
LSB
Least Significant Bit
MUX
Multiplexer
NOM
Normal Operation Mode
OWI
One-Wire Interface
POC
Power-On Clear
POR
Power-On Reset Level
PSRR
Power Supply Rejection Ratio
PTAT
Proportional To Absolute Temperature
RM
Raw Mode
SOT
Second Order Term
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14
Document Revision History
Revision Date
Description
1.40
February 24, 2009
Revision to Byte 16 in Table 3.11.
Revision to add an explanation for default setting in Table 3.5.
Revision to “Lower Output Voltage Limit” specification in section 1.3.5.
Revisions in sections 2.4.3 and 2.5.1 to text regarding regulator set point and optimal
reference trim, including text about methods for preserving factory settings.
Revision to caption for Figure 3.2 to clarify that timing is typical.
Revision to text below Table 3.2 regarding minimum and maximum baud rate.
Added note below Table 3.3 clarifying that timing is typical.
Revisions to the default settings column and explanations for the Cust_ID0 and Cust_ID1
EEPROM words in Table 3.5.
Addition of section 5 to explain methods for restoration of EEPROM settings.
1.50
May 14, 2009
Revised conditions for “Overall Ratiometricity Error” and “Overall Accuracy – Analog”
specifications in section 1.3.9.
1.60
June 10, 2009
Added “Document Revision History” table.
1.70
March 29, 2010
Corrected start-up window time 1.5 to 3ms. This change applies only to rev C1 Silicon
(marked as ZSC31015Cxx.) and higher. Stop bit definition is replaced by stop time
definition. Relocated specs from Table 1.9 and deleted Table 1.9.
1.73
May 11, 2010
Added footnote to pages 2, 3, and 14 clarifying that the ZSC31015 is not AEC-Q100qualified.
1.74
July 19, 2010
Added special measurement information to Table 3.2; revised precondition for equation (1).
1.80
July 27, 2010
Revised product name from ZMD31015 to ZSC31015.
1.90
March 24, 2011
Added EEPROM specifications to section 1.3 “Electrical Parameters.” Added table 6.1
“Storage and Soldering Conditions” to section 6 “Pin Configuration and Package.” Updated
trim tolerances in sections 4.1and 4.2. Updated ZMDI contact information.
1.91
October 8, 2011
Revisions in section 1.3.4. Addition of part ordering numbers for all available temperature
ranges to section 11. Update for sales contact information to add ZMDI’s Korea office.
Revision of product title.
1.92
January 12, 2012
Removed requirement of fastest update rate for analog output mode (applied to previous IC
revision). Updated contact information for the USA.
2.00
October 28, 2012
Updates to contact information and part ordering numbers.
2.10
October 9, 2013
Update to section 1.2 to add new minimum specification for output load capacitance.
Update to section 1.3.9 for tSTA maximum specification.
Updates to contact information and imagery for cover and headers.
Updates to part order options.
Updates to related documents.
2.11
December 11, 2013 Update for part ordering tables: kit no longer includes DVD of software. Software is now
downloaded from www.IDT.com/ZSC31015 to ensure user has the latest version of
software.
2.12
June 3, 2014
Update to section 1.2 regarding minimum bridge resistance values. Update to section 2.6.3
regarding minimum bridge resistance values.
Update for “Related Documents” section and ZMDI contact information.
April 22, 2016
Changed to IDT branding. Release date is now the revision number.
November 14, 2016 Correction of error in title regarding the product name.
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ZSC31015 Datasheet
Corporate Headquarters
Sales
Tech Support
6024 Silver Creek Valley Road
San Jose, CA 95138
www.IDT.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
www.IDT.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance
specifications and operating parameters of the described products are determined in an independent state and are not guarante ed to perform the same way when installed in customer products. The
information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but no t limited to, the suitability of IDT's products for any particular purpose,
an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any licens e under intellectual
property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT p roduct can be
reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a mann er does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the
property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of
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© 2016 Integrated Device Technology, Inc
52
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