Advanced Differential
Sensor Signal Conditioner
Description
Features
ZSC31050 is a CMOS integrated circuit for highly accurate amplification and sensor-specific correction of bridge sensor and
temperature sensor signals. The device provides digital compensation of sensor offset, sensitivity, temperature drift, and nonlinearity via a 16-bit RISC microcontroller running a polynomial
correction algorithm.
The ZSC31050 accommodates virtually any bridge sensor type
(e.g., piezo-resistive, ceramic thick-film, or steel membrane
based). In addition, it can interface to a separate temperature
sensor. The bi-directional digital interfaces (I2C, SPI, and
ZACwire™) can be used for a simple PC-controlled one-pass
calibration procedure to program a set of calibration coefficients
into an on-chip EEPROM. A specific sensor and a ZSC31050 can
be mated digitally: fast, precise, and without the cost overhead
associated with trimming by external devices or laser. The
ZACwire™ interface enables an end-of-line calibration of the
sensor module.
Typical applications for the ZSC31050 include industrial, medical,
and consumer products. It is specifically engineered for most
resistive bridge sensors; e.g., sensors for measuring pressure,
force, torque, acceleration, angle, position, and revolution.
ZSC31050
Datasheet
Digital compensation of sensor offset, sensitivity, temperature
drift, and nonlinearity
Accommodates nearly all resistive bridge sensor types (signal
spans from 1mV/V up to 275mV/V)
Digital one-pass calibration: quick and precise
Selectable compensation temperature source: bridge,
thermistor, or internal or external diode
Output options: voltage (0 to 5V), current (4 to 20mA), PWM,
I2C, SPI, ZACwire™ (one-wire interface), alarm
Adjustable output resolution (up to 15 bits) versus sampling
rate (up to 3.9kHz)
Current consumption: 2.5mA (typical)
Selectable bridge excitation: ratiometric voltage, constant
voltage, or constant current
Input channel for separate temperature sensor
Sensor connection and common mode check (sensor aging
detection)
AEC-Q100 qualification (temperature grade 0)
Physical Characteristics
Benefits
Operation temperature -40°C to +125°C (-40°C to +150°C
de-rated, depending on product version)
Supply voltage: 2.7V to 5.5V;
with external JFET: 5V to 48 V
Available in 16-SSOP package or as die
No external trimming components required
PC-controlled configuration and calibration via digital bus
interface – simple, low cost
High accuracy (±0.1% FSO @ –25 to 85°C;
±0.25% FSO @ –40 to 125°C) *
Basic Circuit Diagram
Available Support
VCC
Evaluation kit available
Support for industrial mass calibration available
Quick circuit customization possible for large production
volumes
Sensor
Module
ZSC31050
OUT
GND
* Digital output signal.
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ZSC31050 Datasheet
Block Diagram
Ext. Temp. Sens.
IR_TEMP
+
Gain
Factor
VINP
ϑ
VINN
ADC Mode
Offset
Shift
Temp. Sens.
Select
PGA
MUX
ADC
Int. Temp. Sensor
DAC
FIO1
OUT /
OWI
PWM
FIO2
IO1
IO2
PCOMP
Sensor Bridge
EEPROM
Digital Section
Interfaces
IN3
Analog
Typical Applications:
SCL
SDA
RAM
CMC
Analog Front-End (AFE)
External
Temperature
Sensor
SIF
CTRL-REGS
VBR
Consumer Goods
Weight scales
Flow meters
Strain gauges
Load meters
HVAC
© 2020 Renesas Electronics Corporation
Industrial Applications
4-20mA transmitters
Intelligent sensor networks
Process automation
Factory automation
2
Digital
Portable Devices
Altimeters
Blood pressure
monitors
Interface
Automotive Sensors *
Oil pressure
Temperature sensing
Strain gauges
* AEC-Q100 qualified
March 18, 2020
ZSC31050 Datasheet
Contents
1.
Electrical Characteristics ..............................................................................................................................................................................5
1.1
Absolute Maximum Ratings ...............................................................................................................................................................5
1.2
Operating Conditions .........................................................................................................................................................................5
1.3
Inherent Characteristics .....................................................................................................................................................................7
1.4
1.5
2.
1.3.1
Cycle Rate versus ADC Resolution ....................................................................................................................................8
1.3.2
PWM Frequency .................................................................................................................................................................8
Electrical Parameters .........................................................................................................................................................................9
1.4.1
Supply / Regulation ..............................................................................................................................................................9
1.4.2
Analog Front End ................................................................................................................................................................9
1.4.3
DAC and Analog Output (OUT Pin) ....................................................................................................................................9
1.4.4
PWM Output (OUT Pin, IO1 Pin) ........................................................................................................................................9
1.4.5
Temperature Sensors (IR_TEMP Pin) ................................................................................................................................9
1.4.6
Digital Outputs (IO1, IO2, OUT Pins in Digital Mode) .......................................................................................................10
1.4.7
System Response .............................................................................................................................................................10
Interface Characteristics ..................................................................................................................................................................11
1.5.1
Multiport Serial Interfaces (I2C, SPI) .................................................................................................................................11
1.5.2
One-Wire Serial Interface (ZACwire™) .............................................................................................................................11
Circuit Description ......................................................................................................................................................................................12
2.1
Signal Flow ......................................................................................................................................................................................12
2.2
Application Modes ............................................................................................................................................................................13
2.3
Analog Front-End (AFE)...................................................................................................................................................................14
2.3.1
Programmable Gain Amplifier (PGA) ................................................................................................................................14
2.3.2
Extended Zero Point Compensation (XZC).......................................................................................................................14
2.3.3
Measurement Cycle Performed by Multiplexer .................................................................................................................16
2.3.4
Analog-to-Digital Converter ...............................................................................................................................................16
2.4
System Control ................................................................................................................................................................................18
2.5
Output Stage ....................................................................................................................................................................................18
2.5.1
Analog Output ...................................................................................................................................................................20
2.5.2
Comparator Module (ALARM Output) ...............................................................................................................................20
2.5.3
Serial Digital Interface .......................................................................................................................................................20
2.6
Voltage Regulator ............................................................................................................................................................................21
2.7
Watchdog and Error Detection .........................................................................................................................................................21
3.
Application Circuit Examples ......................................................................................................................................................................22
4.
ESD/Latch-Up-Protection ...........................................................................................................................................................................23
5.
Pin Configuration and Package ..................................................................................................................................................................24
6.
Reliability ....................................................................................................................................................................................................25
7.
Customization .............................................................................................................................................................................................25
8.
Ordering Information...................................................................................................................................................................................26
9.
Related Documents ....................................................................................................................................................................................26
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ZSC31050 Datasheet
10. Glossary .....................................................................................................................................................................................................27
11. Revision History..........................................................................................................................................................................................28
List of Figures
Figure 1. Block Diagram of the ZSC31050 .......................................................................................................................................................12
Figure 2. Measurement Cycle ZSC31050 ........................................................................................................................................................16
Figure 3. Application Example 1 .......................................................................................................................................................................22
Figure 4. Application Example 2 .......................................................................................................................................................................22
Figure 5. Application Example 3 .......................................................................................................................................................................22
Figure 6. Application Example 4 .......................................................................................................................................................................22
Figure 7. Application Example 5 .......................................................................................................................................................................23
Figure 8. Pin Configuration ...............................................................................................................................................................................25
List of Tables
Table 1.
Adjustable Gains, Resulting Sensor Signal Spans, and Common Mode Ranges .............................................................................14
Table 2.
Extended Zero Point Compensation (XZC) Range............................................................................................................................15
Table 3.
Output Resolution versus Sample Rate.............................................................................................................................................17
Table 4.
Output Configurations Overview........................................................................................................................................................18
Table 5.
Analog Output Configuration .............................................................................................................................................................20
Table 6.
Pin Configuration ...............................................................................................................................................................................24
© 2020 Renesas Electronics Corporation
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ZSC31050 Datasheet
1.
Electrical Characteristics
1.1 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. The ZSC31050 might not function or be operable above the recommended operating
conditions. Stresses exceeding the absolute maximum ratings might also damage the device. In addition, extended exposure to stresses
above the recommended operating conditions might affect device reliability. Renesas does not recommend designing to the “Absolute
Maximum Ratings.”
No.
1.1.1
Digital supply voltage
VDDMAX
1.1.2
Analog supply voltage
VDDAMAX
1.1.3
Voltage at all analog and digital I/O
pins except FBP, SDA, SCL (see
1.1.4, 1.1.5, and 1.1.6)
1.1.4
Voltage at FBP pin
VFBP_MAX
1.1.5
Voltage at SDA pin
1.1.6
Voltage at SCL pin
1.1.7
Storage temperature
1.2
Parameter
Symbol
Conditions
Min
Max
Unit
To VSS
-0.3
6.5
V DC
To VSS
-0.3
6.5
V DC
-0.3
VDDA+0.3
V DC
4mA to 20mA – Interface
-1.2
VDDA+0.3
V DC
VSDA_MAX
I2C mode only
-0.3
5.5
V DC
VSCL_MAX
I2C mode only
-0.3
5.5
V DC
-45
150
°C
VA_I/O,
VD_I/O
TSTG
Operating Conditions
Unless otherwise noted, voltages are relative to VSS and analog-to-digital conversion = 2nd order, resolution = 13 bits, gain ≥ 210,
fclk ≤ 2.25MHz.
For specifications marked with an asterisk (*), there is no measurement in mass production—the parameter is guaranteed by design and/or
quality observations.
Note: See important notes at the end of the table.
No.
1.2.1
1.2.2
Parameter
1.2.1.1 TQE ambient
temperature range for part
numbers ZSC31050xExx
1.2.1.2 TQA ambient
temperature range for part
numbers ZSC31050xAxx
1.2.1.3 TQI ambient
temperature range for part
numbers ZSC31050xIxx
Ambient temperature
EEPROM programming
1.2.3
EEPROM programming
cycles
1.2.4
Data retention (EEPROM)
© 2020 Renesas Electronics Corporation
Symbol
Conditions
Min
TAMB_TQE
Operation life time < 1000h
@ 125°C to 150°C
Typical
Max
Unit
-40
150
°C
TAMB_TQA
-40
125
°C
TAMB_TQI
-25
85
°C
TAMB_EEP
-25
85
°C
100
Average temp. < 85°C
5
15
years
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ZSC31050 Datasheet
No.
1.2.5
Parameter
Symbol
Conditions
Min
Typical
Max
Unit
Analog supply voltage
VDDA
Ratiometric mode
2.7
5.5
V DC
1.2.6
Analog supply voltage
advanced performance
VDDAADV
Ratiometric mode
4.5
5.5
V DC
1.2.7
Digital supply voltage
VDD
Externally powered
1.05
VDDA
2.7
V DC
V DC
1.2.8
External supply voltage
VSUPP
Voltage Regulator Mode
with external JFET [a]
VDDA +
2V
1.2.9
Common mode input range [b]
VIN_CM
Depends on gain adjust;
refer to section 2.3.1
0.21
0.76
VADC_REF
1.2.10
Input voltage FBP pin
VIN_FBP
-1
VDDA
V DC
1.2.11
Sensor bridge resistance [c]
(over full temperature range)
RBR
3.0
25.0
kΩ
25.0
kΩ
RBR_CL
Current loop interface,
4 to 20mA
5.0
RBR_REF
Bridge current
IBR = VDDA / (16·RBR_REF)
0.07
1.2.12
Reference resistor for bridge
current source *
1.2.13
Stabilization capacitor *
CVDDA
External capacitor between
VDDA and VSS
50
100
470
nF
1.2.14
VDD stabilization capacitor*, [d]
CVDD
Between VDD and VSS,
external
0
100
470
nF
1.2.15
Maximum load capacitance
allowed at OUT [e]
CL_OUT
Output Voltage Mode
50
nF
1.2.16
Minimum load resistance
allowed
RL_OUT
Output Voltage Mode
1.2.17
Maximum load capacitance
allowed at VGATE
CL_VGATE
Total capacitance relative to
all potentials
RBR
2
kΩ
10
nF
[a] Maximum depends on the breakdown voltage of the external JFET; refer to the application recommendations in the ZSC31050 Application
Note—0-10V Output.
[b] VADC_REF: reference voltage of the analog-to-digital converter (VBR or VDDA).
[c] No minimum limitation with an external connection between VDDA and VBR.
[d] Lower stabilization capacitors can increase noise level at the output.
[e] If the maximum is used, take into consideration the special requirements of the ZACwire™ interface stated in the ZSC31050 Functional
Description, section 4.3.
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ZSC31050 Datasheet
1.3 Inherent Characteristics
For specifications marked with an asterisk (*), there is no measurement in mass production—the parameter is guaranteed by design and/or
quality observations.
No.
1.3.1
1.3.2
Parameter
Symbol
Selectable input span, bridge
sensor measurement
VIN_SP
Analog offset comp range
(6 bit setting)
Conditions
Refer to section 2.3.1.
Maximum bias current [a]
Min
Max
Unit
2
280
mV/V
-20
20
Counts
-25
25
Counts
9
15
Bits
10
90
%VDDA
1.3.3
Analog-to-digital conversion
(ADC) resolution
1.3.4
ADC input range
1.3.5
Digital-to-analog conversion
(DAC) resolution
rDAC
1.3.6
PWM resolution
rPWM
9
1.3.7
Bias current for external
temperature diodes
ITS
8
1.3.8
Sensitivity internal temperature
diode [c]
1.3.9
Clock frequency*
rADC
3-bit setting [b]
Range
STT_SI
fCLK
At analog output
Raw values without conditioning
Guaranteed adjustment range
Typ
11
Bits
12
Bits
18
40
µA
2800
3200
3600
ppm
FS/K
1
2
4
MHz
[a] Set configuration word ADJREF:BCUR ( bits 4-6) to 111 (for details, see the ZSC31050 Functional Description).
[b] 15-bit resolution is not applicable for 1st order ADC and not recommended for sensors with high nonlinearity behavior.
[c] FS = Full scale.
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ZSC31050 Datasheet
1.3.1 Cycle Rate versus ADC Resolution
The following specifications are guaranteed by design and/or quality observations.
Important note: Combining first-order configuration of the ADC with 15-bit resolution is not allowed.
ADC Order
(OADC)
Conversion Cycle fCYC
Resolution
rADC
fCLK=2MHz
fCLK=2.25MHz
[Bit]
[Hz]
[Hz]
9
1302
1465
10
781
879
11
434
488
12
230
259
13
115
129
14
59
67
11
3906
4395
12
3906
4395
13
1953
2197
14
1953
2197
15
977
1099
1
2
1.3.2 PWM Frequency
The following specifications are not measured in mass production; they are guaranteed by design and/or quality observations.
PWM Frequency in Hz at 2MHz Clock [a]
PWM Frequency in Hz at 2.25MHz Clock [b]
Clock Divider
Clock Divider
PWM
Resolution
rPWM [Bit]
1
0.5
0.25
0.125
1
0.5
0.25
0.125
9
3906
1953
977
488
4395
2197
1099
549
10
1953
977
488
244
2197
1099
549
275
11
977
488
244
122
1099
549
275
137
12
488
244
122
61
549
275
137
69
[a] Internal RC oscillator: coarse adjustment to 1MHz, 2MHz, and 4MHz, fine-tuning +/- 25%; external clock is also possible.
[b] Internal RC oscillator: coarse adjustment to 1.125MHz, 2.25MHz, and 4.5MHz, fine-tuning +/- 25%; external clock is also possible.
© 2020 Renesas Electronics Corporation
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ZSC31050 Datasheet
Electrical Parameters
1.4
Unless otherwise noted, voltages are relative to VSS and analog-to-digital conversion = 2nd order, resolution = 13 bits, gain ≥210,
fclk≤2.25MHz.
Note: See important notes at the end of the table.
No.
Parameter
Symbol
1.4.1
Supply / Regulation
1.4.1.1
Supply current
1.4.1.2
Supply current for current
loop
ISUPP_CL
1.4.1.3
Temperature coefficient
voltage reference *
TCREF
1.4.2
1.4.2.1
1.4.3
ISUPP
Conditions
Min
Typ
Max
Unit
Without bridge and load current,
bias adjustment ≤ 4, fCLK ≤ 2.4MHz
2.5
4
mA
Without bridge current,
fCLK ≤ 1.2MHz,
bias [a] adjustment ≤ 1
2.0
2.75
mA
±50
200
ppm/K
-2 to -10
2 to 10
nA
0.025
0.975
VDDA
0.95
LSB
4
LSB
-200
Analog Front End
Parasitic differential input
offset current *
IIN_OFF
Temperature range =
TAMB_TQI (-40 to 85°C)
DAC and Analog Output (OUT Pin)
1.4.3.1
Output signal range [b]
VOUT_SR
Voltage Mode, RLOAD > 2KΩ
VDDAADV
Temperature range = TAMB_TQI
1.4.3.2
Output DNL
DNLOUT
VDDAADV
Temperature range = TAMB_TQI
1.4.3.3
Output INL [c]
INLOUT
1.4.3.4
Output slew rate *
SROUT
1.4.3.5
Short circuit current *
IOUT_max
1.4.3.6
Addressable output signal
range *
VOUT_ADR
2048 steps
1.4.4
PWM Output (OUT Pin, IO1 Pin)
Voltage Mode
Load capacitance < 20nF
Using conditions of 1.4.3.1
0.1
5
0
1.4.4.1
PWM high voltage
VPWM_H
Load resistance > 10kΩ
1.4.4.2
PWM low voltage
VPWM_L
Load resistance > 10kΩ
1.4.4.3
PWM output slew rate *
SRPWM
Load capacitance < 1nF
15
At rADC = 13 bits
75
1.4.5
1.4.5.1
V/µs
10
20
mA
1
VDDA
0.9
VDDA
0.1
VDDA
V/µs
Temperature Sensors (IR_TEMP Pin)
Sensitivity external diode /
resistor measurement
© 2020 Renesas Electronics Corporation
STTS_E
9
210
µV/LSB
March 18, 2020
ZSC31050 Datasheet
No.
1.4.6
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Digital Outputs (IO1, IO2, OUT Pins in Digital Mode)
1.4.6.1
Output high level
VDOUT_H
Load resistance > 1 kΩ
1.4.6.2
Output low level
VDOUT_L
Load resistance > 1 kΩ
1.4.6.3
Output current *
IDOUT
0.9
VDDA
0.1
4
1.4.7
System Response
1.4.7.1
Startup time [d]
tSTA
Power-on to 1st measurement result at
output
1.4.7.2
Response time *
tRESP
66% change in input signal; refer to
Table 3 for fCON
1.4.7.3
Overall accuracy
(deviation from ideal line
including INL, gain, and
offset errors) *, [e]
ACOUT
VDDA
mA
2
5
ms
3.66
1/fCON
TAMB_TQI (-25 to 85 °C) & VDDAADV
0.10
%
TAMB_TQA (-40 to 125 °C) & VDDAADV
0.25
%
TAMB_TQE (-40 to 150 °C) & VDDAADV
0.50
%
1.66
2.66
1.4.7.4
Analog output noise:
peak-to-peak *
VNOISE, PP
Shorted inputs, gain ≤ 210
bandwidth ≤ 10kHz
10
mV
1.4.7.5
Analog output noise:
RMS *
VNOISE, RMS
Shorted inputs, gain ≤ 210
bandwidth ≤ 10kHz
3
mV
1.4.7.6
Ratiometricity error
REOUT_5V
±5% respectively 1000ppm ±10% (5V)
500
ppm
REOUT_3V
±5% respectively 200ppm ±10% (3V)
1000
ppm
[a] Recommended bias adjustment ≤ 4; note the application recommendations and power consumption adjustment constraints given in the
ZSC31050 Application Note—Current Loop.
[b] De-rated performance in lower part of supply voltage range (2.7 to 3.3V): 2.5 to 5 %VDDA and 95 to 97.5%VDDA.
[c] Output linearity and accuracy can be enhanced by an additional analog output stage calibration.
[d] OWI, start window disabled (depending on resolution and configuration, start routine begins approximately 0.8ms after power-on).
[e] Accuracy better than 0.5% requires offset and gain calibration for the analog output stage; parameter only for ratiometric output. The current
loop application is verified and validated for 5V operation only and external supply > 7V (upper limit is dependent on the external components
used). Accuracy and temperature range should be validated based on the schematic design used. Refer to the ZSC31050 Application Note—
Current Loop for more information.
*
For specifications marked with an asterisk (*), there is no measurement in mass production—the parameter is guaranteed by design and/or quality observations.
© 2020 Renesas Electronics Corporation
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ZSC31050 Datasheet
1.5 Interface Characteristics
No.
1.5.1
1.5.1.1
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
0.7
1
VDDA
-
5.5
V DC
0
0.3
VDDA
Multiport Serial Interfaces (I2C, SPI)
Input high level [a]
VI2C_IN_H
1.5.1.2
Input low level
VI2C_IN_L
1.5.1.3
Output low level
VI2C_OUT_L
0.1
VDDA
1.5.1.4
Load capacitance at the
SDA pin
CSDA
400
pF
1.5.1.5
Clock frequency at the
SCL pin [b]
fSCL
400
kHz
1.5.1.6
Pull-up resistor
RI2C_PU
1.5.1.7
Input capacitance
(each pin)
CI2C_IN
1.5.2
fCLK ≥ 2MHz
500
Ω
Also valid for SPI.
10
pF
One-Wire Serial Interface (ZACwire™)
1.5.2.1
OWI start window
tOWI_start
1.5.2.2
Pull-up resistance master
ROWI_PU
1.5.2.3
OWI load capacitance
1.5.2.4
Voltage level low
VOWI_L
1.5.2.5
Voltage level high
VOWI_H
COWI_LOAD
20
ms
330
20µs < tOWI_BIT < 100µs
0.75
Ω
0.08
tOWI_BIT /
ROWI_PU
0.2
VDDA
VDDA
[a] The maximum value in V DC is independent from VDDA in I2C Mode.
[b] Internal clock frequency fCLK must be at least 5 times higher than the communication clock frequency.
© 2020 Renesas Electronics Corporation
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ZSC31050 Datasheet
2.
Circuit Description
Note: This data sheet provides specifications and a general overview of ZSC31050 operation. For details of operation, including configuration
settings and related EEPROM registers, refer to the ZSC31050 Functional Description.
2.1 Signal Flow
The ZSC31050’s signal path includes both analog (shown in pink in Figure 1) and digital (blue) sections. The analog path is differential; i.e.,
the differential bridge sensor signal is handled internally via two signal lines that are symmetrical around a common mode potential (analog
ground = VDDA/2), which improves noise rejection.
Therefore it is possible to amplify positive and negative input signals, which are located in the common mode range of the signal input.
Figure 1.
Block Diagram of the ZSC31050
Ext. Temp. Sens.
IR_TEMP
+
Gain
Factor
VINP
ϑ
VINN
SCL
SDA
PGA
MUX
DAC
FIO1
OUT /
OWI
PWM
FIO2
IO1
IO2
PCOMP
ADC Mode
Offset
Shift
Temp. Sens.
Select
RAM
ADC
CMC
Analog Front-End (AFE)
EEPROM
Int. Temp. Sensor
External
Temperature
Sensor
SIF
CTRL-REGS
VBR
Digital Section
Sensor Bridge
Interfaces
IN3
Analog
Digital
Interface
PGA
Programmable Gain Amplifier
MUX
Multiplexer
ADC
Analog-to-Digital Converter
CMC
Calibration Microcontroller
DAC
Digital-to-Analog Converter
FIO1
Flexible I/O 1: Analog Out (voltage/current), PWM2, ZACwire™ (one-wire-interface)
FIO2
Flexible I/O 2: PWM1, SPI Data Out, SPI Slave Select, Alarm1, Alarm2
SIF
Serial interface: I2C Data I/O, SPI Data In, Clock
PCOMP
Programmable Comparator
EEPROM
Nonvolatile Memory for Calibration Parameters and Configuration
TS
On-Chip Temperature Sensor (pn-junction)
ROM
Memory for Correction Formula and Algorithm
PWM
PWM Module
The differential signal from the bridge sensor is pre-amplified by the programmable gain amplifier (PGA). The multiplexer (MUX) transmits the
signals from the bridge sensor, external diode, or separate temperature sensor to the ADC in a specific sequence (the internal pn-junction
(TS) can be used instead of the external temperature diode). Next, the ADC converts these signals into digital values.
© 2020 Renesas Electronics Corporation
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ZSC31050 Datasheet
The digital signal correction takes place in the calibration microcontroller (CMC). It is based on a special correction formula located in the
ROM and sensor-specific coefficients (stored in the EEPROM during calibration). Depending on the programmed output configuration, the
corrected sensor signal is output as an analog value, a PWM signal, or a digital value in the format of SPI, I2C, or ZACwire™. The output
signal is provided at two flexible I/O modules (FIO) and at the serial interface (SIF). The configuration data and the correction parameters can
be programmed into the EEPROM via the digital interfaces.
The modular circuit concept used in the design of the ZSC31050 allows fast customization of the IC for high-volume applications if needed.
Circuit blocks and functions can be added or removed, which can reduce the die size (see section 7 for more details).
2.2 Application Modes
For each application, a configuration set must be established (generally prior to calibration) by programming the on-chip EEPROM regarding
to the following modes:
Sensor channel
— Sensor mode: ratiometric voltage or current supply mode.
— Input range: the gain of the analog front end must be chosen with respect to the maximum sensor signal span, which also requires
adjusting the zero point of the ADC.
— Additional offset compensation, the Extended Zero-Point Compensation (XZC), must be enabled if required; e.g., if the sensor offset
voltage is close to or larger than the sensor span.
— Resolution/response time: The ADC must be configured for resolution and conversion settings (1st or 2nd order). These settings
influence the sampling rate, signal integration time, and, as a result, the noise immunity.
— Polarity of the sensor bridge inputs: this allows inverting the sensor bridge inputs
Analog output
— Choice of output type (voltage value, current loop, or PWM) for output register 1.
— Optional additional output register 2: PWM via IO1 pin or alarm out module via IO1 or IO2 pin.
Digital communication: The protocol and its parameters must be selected.
Temperature
— The temperature sensor type for the temperature correction must be chosen (only main channel (T1) is usable for correction).
— Optional: a secondary temperature sensor (T2) can be chosen as a second sensor output.
Supply voltage: For non-ratiometric output, the voltage regulation must be configured.
Note:
Not all possible combinations of settings are allowed (see section 2.5).
The calibration procedure must include establishing the coefficients for calibration calculation and the following steps depending on
configuration:
Adjustment of the extended offset compensation
Zero compensation of temperature measurement
Adjustment of the bridge current
Settings for the reference voltage if using the reference voltage
Settings for the thresholds and delays for the alarms if using the alarms
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2.3 Analog Front-End (AFE)
The analog front-end consists of the programmable gain amplifier (PGA), the multiplexer (MUX), and the analog-to-digital converter (ADC).
2.3.1 Programmable Gain Amplifier (PGA)
The following tables show the adjustable gains, the sensor signal spans that can be processed, and the common mode range allowed.
Table 1.
Adjustable Gains, Resulting Sensor Signal Spans, and Common Mode Ranges
No.
PGA Gain aIN
Gain Amp1
Gain Amp2
Gain Amp3
Max. Span
VIN_SP in mV/V
Input Range
VIN_CM in % VDDA ‡
1
420
30
7
2
2
43 to 57
2
280
30
4.66
2
3
40 to 59
3
210
15
7
2
4
43 to 57
4
140
15
4.66
2
6
40 to 59
5
105
15
3.5
2
8
38 to 62
6
70
7.5
4.66
2
12
40 to 59
7
52.5
7.5
3.5
2
16
38 to 62
8
35
3.75
4.66
2
24
40 to 59
9
26.3
3.75
3.5
2
32
38 to 62
10
14
1
7
2
50
43 to 57
11
9.3
1
4.66
2
80
40 to 59
12
7
1
3.5
2
100
38 to 62
13
2.8
1
1.4
2
280
21 to 76
2.3.2 Extended Zero Point Compensation (XZC)
The ZSC31050 supports two methods of sensor offset cancellation (zero shift):
Digital offset correction
XZC – an analog cancellation for large offset values (up to approximately 300% of span)
The digital sensor offset correction is processed at the digital signal correction/conditioning by the CMC. The XZC analog sensor offset precompensation is needed for compensation of large offset values, which would overdrive the analog signal path due to uncompensated
amplification. For analog sensor offset pre-compensation, a compensation voltage is added in the analog pre-gaining signal path (coarse
offset removal). The analog offset compensation in the AFE can be adjusted by six EEPROM bits as described in the ZSC31050 Functional
Description. It allows an analog zero-point shift of up to 300% of the segment of the signal span that can be processed.
‡
Bridge in voltage mode; refer to the ZSC31050 Functional Description for the usable input signal / common mode range at the bridge in current mode.
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The zero-point shift ZXZC is calculated by equation (1):
V XZC
k ⋅ Z XZC
=
VDDBR
20 ⋅ aIN
(1)
Where
VXZC
= Extended zero compensation voltage
VDDBR = Bridge voltage
k
= Calculation factor
aIN
= Input gain
Table 2.
Extended Zero Point Compensation (XZC) Range
PGA Gain
aIN
Max. Span
VIN_SP
(mV/V)
Calculation
Factor k
Offset Shift per Step
(% Full Span)
Approx. Maximum
Offset Shift
(mV/V)
Approx. Maximum Shift
(% VIN_SP)
(@ ± 20 Steps)
420
2
3.0
15%
+/- 7
330
280
3
1.833
9%
+/- 6
200
210
4
3.0
15%
+/- 14
330
140
6
1.833
9%
+/- 12
200
105
8
1.25
6%
+/- 12
140
70
12
1.833
9%
+/- 24
200
52.5
16
1.25
6%
+/- 22
140
35
24
1.833
9%
+/-48
200
26.3
32
1.25
6%
+/- 45
140
14
50
3.0
15%
+/- 180
330
9.3
80
1.833
9%
+/- 160
200
7
100
1.25
6%
+/- 140
140
2.8
280
0.2
1%
+/- 60
22
Note: ZXZC can be adjusted in the range of –31 to 31; however, parameters are guaranteed only for -20 to 20.
© 2020 Renesas Electronics Corporation
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ZSC31050 Datasheet
2.3.3 Measurement Cycle Performed by Multiplexer
Depending on EEPROM settings, the multiplexer selects the following inputs in a set sequence as shown in Figure 2.
Refer to the ZSC31050 Functional Description for EEPROM details.
Internal offset of the input channel (auto-zero) measured by short circuiting
the input
Bridge temperature signal measured by external and internal diode (pnjunction)
Bridge temperature signal measured by bridge resistors
Temperature measured by external thermistor
Pre-amplified bridge sensor signal
The complete measurement cycle is controlled by the CMC. The cycle
diagram at the right shows its principle structure.
The EEPROM adjustable parameters are
Measurement count n (bits 9:7 in configuration word CFGCYC):
n =
Temperature 2 measurement enable, T2E=
After power-on, the start routine is called. It includes the bridge sensor and
auto-zero measurement. It also measures the main temperature channel and
its auto-zero if enabled.
Figure 2.
Measurement Cycle ZSC31050
Start Routine
n
Bridge sensor measurement
1
Temp 1 auto-zero
n
Bridge sensor measurement
1
Temp 1 measurement
n
Bridge sensor measurement
1
Bridge sensor auto-zero
n * T2E
Bridge sensor measurement
T2E
Temp 2 auto-zero
n * T2E
Bridge sensor measurement
T2E
Temp 2 measurement
n
Bridge sensor measurement
1
Common mode voltage
2.3.4 Analog-to-Digital Converter
The ADC is a charge-balancing converter using full differential switched capacitor technique. It can be used as a first or second order
converter:
In the first order mode, the ADC is inherently monotone and insensitive against short and long term instability of the clock frequency. The
conversion cycle time depends on the desired resolution and can be roughly calculated by equation (2):
t CYC _ 1 = 2 rADC [µs]
(2)
The available ADC resolutions are rADC = .
In the second order mode, two conversions are stacked with the advantage of a much shorter conversion cycle time but with the drawback of
a lower noise immunity caused by the shorter signal integration period. The conversion cycle time in this mode is roughly calculated by
equation (3):
rADC + 3
2
t CYC _ 2 = 2
(3)
[µs]
The available ADC resolutions are rADC = .
© 2020 Renesas Electronics Corporation
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The result of the AD conversion is a relative counter result corresponding to equation (4):
VADC_DIFF + VADC_OFF
Z ADC = 2 rADC ⋅
+ 1 − RS ADC
VADC_REF
(4)
ZADC
Number of counts; i.e., the result of the conversion)
VADC_DIFF
Differential input voltage of ADC: (aIN * VIN_DIFF)
VADC_REF
Reference voltage of ADC: (VBR or VDDA)
VADC_OFF
Residual offset voltage of analog front-end to ADC
RSADC
Digital ADC range shift (RSADC = 1/2, 3/4, 7/8, 15/16, controlled by EEPROM setting)
A sensor input signal can be shifted via the RSADC value into the optimal input range of the ADC.
The potential at the VBR pin is used as the ADC’s reference voltage VADC_REF in “VADC_REF = VBR” mode. The mode is determined by the
CFGAPP:ADCREF configuration register in EPPROM as described in the ZSC31050 Functional Description. Sensor bridges with no
ratiometric behavior (e.g., temperature-compensated bridges) that are supplied by a constant current, require the VDDA potential as VADC_REF
and this can be adjusted in the configuration. If this mode is enabled, XZC cannot be used (adjustment=0), but it must be enabled (refer to the
calculation spreadsheet ZSC31050_Bridge_Current_Excitation_Rev*.xls for details).
Note:
The AD conversion time (sample rate) is only part of the complete signal conditioning cycle.
Table 3.
ADC
Order
(OADC)
1
2
§
Output Resolution versus Sample Rate
Maximum Output Resolution
Sample Rate fCON
rADC §
Digital OUT
Analog OUT
rPWM
fCLK=2MHz
fCLK =2.25MHz
(Bit)
(Bit)
(Bit)
(Bit)
(Hz)
(Hz)
9
9
9
9
1302
1465
10
10
10
10
781
879
11
11
11
11
434
488
12
12
11
12
230
259
13
13
11
12
115
129
14
14
11
12
59
67
10
10
10
10
3906
4395
11
11
11
11
3906
4395
12
12
11
12
3906
4395
13
13
11
12
1953
2197
14
14
11
12
1953
2197
15
15
11
12
977
1099
ADC resolution should be 1 to 2 bits higher than applied output resolution
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ZSC31050 Datasheet
2.4 System Control
The system control is started by the internal power-on reset (POR) using the internal clock generator or an external clock. It has the following
features:
Control of the I/O functions and the measurement cycle using the EEPROM-stored configuration settings.
16-bit correction calculation for each measurement signal using the EEPROM-stored calibration coefficients and ROM-based algorithms.
Error checking: To increase safety, the EEPROM data are verified via an EEPROM signature during the initialization procedure and the
registers of the CMC are continuously observed with a parity check. If an error is detected, the error flag of the CMC is set and the outputs
are driven to a diagnostic value. See section 2.7.
Note: Conditioning options include up to third-order sensor input correction (de-rated). The available adjustment ranges depend on the
specific calibration parameters; basically, offset compensation and linear correction are only limited by the loss of resolution the compensation
will cause. The second-order correction is possible up to approximately 20% of the full-scale difference from a straight line; third-order is
possible up to approximately 10% (ADC resolution = 13 bits). The temperature calibration includes first and second order correction, which
should be sufficient in almost all applications. ADC resolution also affects calibration options – each additional bit of resolution reduces the
calibration range by approximately 50%.
2.5 Output Stage
The ZSC31050 provides the following I/O pins: OUT, IO1, IO2, and SDA. The signal formats listed in Table 4 can be output via these pins:
analog (voltage or current), PWM, data (SPI/I2C), alarm. The following values can be provided at the I/O pins: bridge sensor signal,
temperature signal 1, temperature signal 2, and alarms.
Note: The alarm signals (Alarm 1 and Alarm 2) only apply to the bridge sensor signal; they cannot be used as an alarm for the temperature
signal.
Because some pins are dual-purpose, there are restrictions on the possible combinations for outputs and interface connections. Table 4 gives
an overview of valid combinations. For some combinations in the SPI Mode, pin assignments depend on whether the ZSC31050 is in the
Command Mode (CM) or the Normal Operation Mode (NOM) as indicated in the “Mode” column (refer to the ZSC31050 Functional
Description for more details).
Note: In the SPI Mode, the IO2 pin is used as the Slave Select, so no Alarm 2 can be output in this mode.
Table 4.
Output Configurations Overview
SIF
I/O Pins Used
Configuration
Number
I2C
1
2
3
4
ALARM1
5
PWM1
6
PWM1
7
Analog
8
Analog
9
Analog
10
Analog
ALARM1
11
Analog
PWM1
SPI
© 2020 Renesas Electronics Corporation
OUT
IO1
IO2
SDA
Mode
Data I/O
ALARM1
Data I/O
ALARM2
Data I/O
ALARM2
Data I/O
Data I/O
ALARM2
Data I/O
Data I/O
ALARM1
18
Data I/O
ALARM2
Data I/O
ALARM2
Data I/O
Data I/O
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ZSC31050 Datasheet
SIF
Configuration
Number
I2C
12
I/O Pins Used
SPI
Mode
OUT
IO1
IO2
SDA
Analog
PWM1
ALARM2
Data I/O
13
PWM2
14
PWM2
15
PWM2
16
PWM2
ALARM1
17
PWM2
PWM1
18
PWM2
PWM1
ALARM2
Data I/O
Data out
(SDO)
Slave select
Data in
Data out
(SDO)
Slave select
Data in
CM
ALARM1
-
-
NOM
Data out
Slave select
Data in
CM
PWM1
-
-
NOM
Data out
Slave select
Data in
Data out
Slave select
Data in
CM
ALARM1
-
-
NOM
Data out
Slave select
Data in
CM
PWM1
-
-
NOM
Data out
Slave select
Data in
Data out
Slave select
Data in
CM
ALARM1
-
-
NOM
Data out
Slave select
Data in
CM
PWM1
-
-
NOM
19
20
21
22
Analog
23
Analog
24
Analog
25
PWM2
26
PWM2
27
PWM2
© 2020 Renesas Electronics Corporation
Data I/O
ALARM1
19
Data I/O
ALARM2
Data I/O
ALARM2
Data I/O
Data I/O
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ZSC31050 Datasheet
2.5.1 Analog Output
For analog output, three 15-bit registers store the compensated measurement results for the bridge sensor signal and temperature measurements 1 and 2. Each register can be independently switched to either the digital-to-analog converter module (DAC) or the PWM module (see
Figure 1) and then output via the FIO1 or FIO2 output module connected to the OUT or IO1 pin respectively according to Table 5. Refer to the
ZSC31050 Functional Description for details.
Table 5.
Analog Output Configuration
Output Module
OUT
Voltage (DAC)
PWM
IO1
The voltage output module consists of an 11-bit resistor string DAC with a buffered output and a subsequent inverting amplifier with a class
AB rail-to-rail operational amplifier. The two internal feedback networks are connected to the FBN and FBP pins. This structure offers wide
flexibility for the output configuration; for example, voltage output, and 4mA to 20mA current loop output. Accidentally short-circuiting the
analog output to VSS or VDDA does not damage the ZSC31050.
The PWM module outputs the analog measurement value via a stream of pulses with a duty cycle that is determined by the analog value. The
PWM frequency depends on the resolution and clock divider settings. The maximum analog output resolution is 12 bits; however the
maximum PWM frequency is 4kHz (9 bits). If both PWM2 and SPI protocol are activated (configuration numbers 25, 26, and 27 in Table 4),
the output IO1 pin is shared between the PWM output and the SPI SDO output of the serial interface, and SPI interface communication
(Command Mode) interrupts the PWM output.
2.5.2 Comparator Module (ALARM Output)
The comparator module consists of two comparator channels that can be connected to IO1 and IO2. Each can be independently programmed
for threshold, hysteresis, switching direction, and on/off delay. A window comparator mode is also available.
2.5.3 Serial Digital Interface
The ZSC31050 includes a serial digital interface that is able to communicate in three different communication protocols: I2C, SPI, and
ZACwire™ (one-wire communication). In SPI mode, the IO2 pin operates as the slave-select input, and the IO1 pin is the data output (SDO).
Initializing Communication
After power-on for approximately 20ms (the start window), the ZSC31050 interface is in the ZACwire™ mode, which allows communication
via the one-wire interface (the OUT pin).
If a proper communication request is detected during the start window, the interface stays in the ZACwire™ mode (the Command Mode). This
state can be left by set commands or a new power-on.
If no request is received during the start window, then the serial interface switches to communication via either I2C or SPI mode depending on
EEPROM settings. The OUT pin can be used as an analog output or as a PWM output depending on EEPROM settings. The start window
can be disabled (or enabled) by a special EEPROM setting.
For a detailed description of the serial interfaces, see the ZSC31050 Functional Description.
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2.6 Voltage Regulator
For 3V to 5V (±10%) ratiometric output applications, the external supply voltage can be used for sensor element biasing. If an absolute
analog output is required, then the internal voltage regulator with an external power regulation element (JFET) can be used. The regulation is
bandgap-reference-based and designed for an external supply voltage VSUPP in the range of 7V to 48V DC. The internal supply and sensor
bridge voltage can be varied between 3V and 5.5V in four steps with the voltage regulator as determined by a configuration word in
EEPROM.
2.7 Watchdog and Error Detection
The ZSC31050 detects various possible errors. A detected error is signaled by changing to a diagnostic mode. In this case, the analog output
is set to the high or low level (maximum or minimum possible output value) depending on the error and the output registers of the digital serial
interface are set to a correlated error code.
A watchdog continuously monitors the operation of the CMC and the progress of the measurement loop.
A continuous check of the sensor bridge for broken wires is done by two comparators monitoring the input voltage of each input [(VSSA +
0.5V) to (VDDA – 0.5V)]. The common mode voltage of the sensor is continuously monitored to detect sensor aging.
Different functions and blocks in the digital section are continuously monitored, including the RAM, ROM, EEPROM, and register contents.
See section 1.3.4 in the ZSC31050 Functional Description for a detailed description of all monitored blocks and methods of indicating errors.
© 2020 Renesas Electronics Corporation
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3.
Application Circuit Examples
Figure 3.
Application Example 1
Figure 4.
Typical ratiometric measurement with voltage output, temperature
compensation via external diode, internal VDD regulator, and active
sensor connection check (bridge must not be at VDDA)
Application Example 2
0V to 10V output configuration with supply regulator (external
JFET), temperature compensation via internal diode, and bridge
in voltage mode
VDDA = 5V
+2.7V to +5.5V
+7V to +48V
VSUPP
VSUPP
C1
0.1µF
C2
0.1µF
VDD 8
10 OUT
SDA 7
C2
0.1µF
SDA
C3
0.1µF
11 FBP
12 IR_TEMP
13 VBR
14 VINP
ZSC31050
Serial Interface
15 VSS
SCL 6
VDD 8
SDA 7
SDA
11 FBP
SCL 6
SCL
IO2 5
IO1
IO1 4
IO2
Out: 0 to 10V
SCL
IO2 5
IO2
IO1 4
IO1
ZD
6.8V
12 IR_TEMP
Flexible I/Os
13 VBR
VGATE 3
14 VINP
IN3 2
16 VINN
9 FBN
10 OUT
ZSC31050
9 FBN
R3
390Ω
C2
< 15nF
Sensor Bridge
C1
0.1µF
VGATE 3
15 VSS
VDDA 1
R1
2.2kΩ
IN3 2
16 VINN
R4
1kΩ
R2
2kΩ
VDDA 1
Sensor Bridge
Out / OWI
GND
Figure 5.
GND
Figure 6.
Application Example 3
Absolute voltage output, supply regulator (external JFET), constant
current excitation of the sensor bridge, temperature compensation
by bridge voltage drop measurement, internal VDD regulator
without external capacitor
VDDA = 5V
Application Example 4
Ratiometric bridge differential signal measurement, 3–wire
connection for end-of-line calibration at OUT pin (ZACwire™),
additional temperature measurement with external thermistor,
and PWM output at IO1 pin
+7V to +48V
+2.7V to +5.5V
VSUPP
C2
0.1µF
RBR_REF
C1
0.1µF
C2
0.1µF
RT
9 FBN
VDD 8
10 OUT
SDA 7
SDA
11 FBP
SCL 6
9 FBN
VDD 8
10 OUT
SDA 7
SDA
SCL
11 FBP
SCL 6
SCL
IO2 5
IO1
12 IR_TEMP
IO1 4
IO2
VSUPP
C1
0.1µF
ZD
6.8V
13 VBR
14 VINP
15 VSS
16 VINN
Flexible I/Os
13 VBR
14 VINP
VGATE 3
PTC
IN3 2
15 VSS
16 VINN
VDDA 1
Sensor Bridge
© 2020 Renesas Electronics Corporation
C2
< 15nF
Sensor Bridge
ZSC31050
12 IR_TEMP
ZSC31050
Serial Interface
IO2 5
IO1 4
PWM OUT
VGATE 3
IN3 2
VDDA 1
C2
< 15nF
Out / OWI
Out / OWI
GND
GND
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ZSC31050 Datasheet
Figure 7.
Application Example 5
Two-wire 4mA to 20mA configuration (7 to 48 V), temperature compensation via internal diode
VDDA = 5V
+7V to +48V
VSUPP
ZD
7.5V
(Current Loop+)
C1
0.1µF
C2
0.1µF
9 FBN
VDD 8
10 OUT
SDA 7
SDA
11 FBP
SCL 6
SCL
IO2 5
IO2
IO1 4
IO1
C3
10nF
12 IR_TEMP
13 VBR
14 VINP
15 VSS
16 VINN
ZSC31050
Serial Interface
Flexible I/Os
VGATE 3
IN3 2
C4
220pF
Re
VDDA 1
Sensor Bridge
RB
2.2kΩ
150Ω
Rsens
50Ω
(Current Loop)
GND
Note: It is possible to combine or separate connectivity of different application examples. For VDD generation, Renesas recommends using
the internal supply voltage regulator with an external capacitor. Refer the ZSC31050 Application Note—Current Loop for use of supply voltage
regulation features (non-ratiometric mode) and current loop output mode.
4. ESD/Latch-Up-Protection
All pins have an ESD protection of >2000V, except the VINN, VINP, and FBP pins, which have an ESD protection >1200V. All pins have a
latch-up protection of ±100mA or +8V/ –4V (relative to VSS/VSSA). Refer to section 5 for details and restrictions. ESD protection referenced
to the Human Body Model is tested with devices in 16-SSOP packages during product qualification. The ESD test follows the Human Body
Model with 1.5kOhm/100pF based on MIL 883, method 3015.7.
© 2020 Renesas Electronics Corporation
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ZSC31050 Datasheet
5. Pin Configuration and Package
Table 6.
Pin Configuration
Pin
Name
1
VDDA
2
IN3
3
Description
Remarks
Latch-up Related Application Circuit
Restrictions and/or Remarks
Positive analog supply voltage
Supply
Resistive temperature sensor IN and
external clock IN
Analog IN
Freely accessible by application (vulnerable to latchup if specifications in section 4 are exceeded)
VGATE
Gate voltage for external regulator
FET
Analog OUT
Only connection to external JFET
4
IO1
SPI data out or ALARM1 or PWM1
Output
Digital IO
Freely accessible by application
5
IO2
SPI slave select or ALARM2
Digital IO
Freely accessible by application
6
SCL
I2C clock or SPI clock
Digital IN, pull-up
Freely accessible by application
7
SDA
Data I/O for I2C or data IN for SPI
Digital I/O, pull-up
Freely accessible by application
8
VDD
Positive digital supply voltage
Supply
Only capacitor to VSS is allowed; otherwise no
application access
9
FBN
Negative feedback connection
output stage
Analog I/O
Freely accessible by application
10
OUT
Analog output or PWM2 output or
one-wire interface I/O
Analog OUT or
Digital I/O
Freely accessible by application
11
FBP
Positive feedback connection output
stage
Analog I/O
Freely accessible by application
12
IR_TEMP
Current source resistor I/O and
temperature diode in
Analog I/O
Circuitry secures potential is within VSS-VDDA
range; otherwise no application access
13
VBR
Bridge top sensing in bridge current
out
Analog I/O
Only short to VDDA or connection to sensor bridge;
otherwise no application access
14
VINP
Positive input from sensor bridge
Analog IN
Freely accessible by application
15
VSS
Negative supply voltage
Ground
16
VINN
Negative input from sensor bridge
Analog IN
© 2020 Renesas Electronics Corporation
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ZSC31050 Datasheet
The standard package for the ZSC31050 is a 16-SSOP (5.3mm body width) with lead-pitch 0.65mm:
Figure 8.
Pin Configuration
Pin Name
FBN
OUT
FBP
IR_TEMP
VBR
VINP
VSS
VINN
Pin Name
9
10
11
12
13
14
15
16
8
7
6
5
4
3
2
1
VDD
SDA
SCL
IO2
IO1
VGATE
IN3
VDDA
6. Reliability
The ZSC31050 is qualified according to the AEC-Q100 standard, operating temperature grade 0. A fit rate < 5fit (temp=55°C, S=60%) is
guaranteed. A typical fit rate of the C7A technology that is used for the ZSC31050 is 2.5fit.
7. Customization
For high-volume applications that require an upgraded or downgraded functionality compared to the ZSC31050, Renesas can customize the
circuit design by adding or removing certain functional blocks.
Renesas has a considerable library of sensor-dedicated circuitry blocks that enables Renesas to provide a custom solution quickly. Please
contact Renesas for further information.
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ZSC31050 Datasheet
8. Ordering Information
Product Code
Description
Package
ZSC31050FEB
ZSC31050 Die — Temperature range: -40°C to +150°C
Unsawn on Wafer
ZSC31050FEC
ZSC31050 Die — Temperature range: -40°C to +150°C
Sawn on Wafer Frame
ZSC31050FEG1
ZSC31050 16-SSOP — Temperature range: -40°C to +150°C
Tube: add “-T” to sales code
Reel: add “-R”
ZSC31050FAB
ZSC31050 Die — Temperature range: -40°C to +125°C
Unsawn on Wafer
ZSC31050FAC
ZSC31050 Die — Temperature range: -40°C to +125°C
Sawn on Wafer Frame
ZSC31050FAG1
ZSC31050 16-SSOP — Temperature range: -40°C to +125°C
Tube: add “-T” to sales code
Reel: add “-R”
ZSC31050FIB
ZSC31050 Die — Temperature range: -25°C to +85°C
Unsawn on Wafer
ZSC31050FIC
ZSC31050 Die — Temperature range: -25°C to +85°C
Sawn on Wafer Frame
ZSC31050FIG1
ZSC31050 16-SSOP — Temperature range: -25°C to +85°C
Tube: add “-T” to sales code
Reel: add “-R”
ZSC31050KITV3P1
ZSC31050 SSC Evaluation Kit V3.1: ZSC31050 Evaluation Board, SSC Communication Board, SSC Sensor
Replacement Board, five ZSC31050 16-SSOP samples. Software is downloadable.
ZSC31050MCSV1P1
Modular Mass Calibration System (MSC) V1.1 for ZSC31050: Four Mass Calibration Boards; SSC
Communication Board; four ZSC31050 Mass Calibration Reference Boards, each with a ZSC31050 sample
mounted; 30m 10-wire flat cable; 100 connectors. Software is downloadable.
9. Related Documents
Visit the ZSC31050 product page (www.IDT.com/ZSC31050) or contact your nearest sales office for the latest version of this document and
related documents.
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ZSC31050 Datasheet
10. Glossary
Term
Description
ADC
Analog-to-Digital Converter
AFE
Analog Front-End
CMC
Calibration Microcontroller
CMOS
Complementary Metal Oxide Semiconductor
DNL
Differential Nonlinearity
ESD
Electrostatic Device
FIO
Flexible Input/Output
FSO
Full Scale Output
IC
Integrated Circuit
INL
Integral Nonlinearity
MUX
Multiplexer
PGA
Programmable Gain Amplifier
POC
Power On Control
PWM
Pulse Width Modulation
PTC
Positive Temperature Coefficient
SIF
Serial Interface
T2E
Temperature 2 Measurement
TS
Temperature Sensor
XZC
Extended Zero-Point Compensation
© 2020 Renesas Electronics Corporation
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ZSC31050 Datasheet
11. Revision History
Date
Description
March 18, 2020
February 13, 2017
January 20, 2016
Changed to IDT branding.
July 27, 2015
(Rev. 1.21)
May 11, 2014
(Rev. 1.20)
April 7, 2014
(Rev. 1.15)
Related documents updated.
December 11, 2013
(Rev. 1.14)
Update for part ordering tables: Mass Calibration Kit no longer includes DVD of software. Software is now
downloaded from website to ensure user has the latest version of the software.
October 14, 2013
(Rev. 1.13)
Revision of maximum voltage supply range with external JFET from original 40V to revised specification 48V.
Updates for part codes.
Minor edits and formatting changes.
Update for order codes for ZSC31050 SSC Evaluation Kit.
Update for contact information.
Product has passed AEC-Q100 at temperature grade 0 (-40°C to 150°C). Related updates to page 2 and
section 6.
Update for contact information.
July 7, 2013
(Rev. 1.12)
July 29, 2010
(Rev. 1.11)
February 18, 2010
(Rev. 1.10)
Updated the paragraph before formula 1 in section 2.3.2.
Specification 1.2.4 for data retention for EEPROM changed to minimum 15 years.
Specification 1.3.4 added for ADC input range.
Added note to section 1.3.1 that first-order configuration of the ADC cannot be used with 15-bit resolution.
Specification 1.4.7.3 updated to remove condition of current-loop output, etc.
Minor edits for clarity.
Addition of RB and C4 in to the current loop application circuit (Figure 7).
Changed absolute maximum ratings for I2C interface.
Updated contact information and imagery for cover and headers.
Correction of equation (4).
Removal of ZSC31050FCxx part numbers.
Minor edits.
Changed “Application Circuit Examples” in Figure 3 and Figure 7.
Addition of current consumption in feature sheet area.
New style for equation in section 2.3.2 and 2.3.4.
Correction of calculation formula for ZADC in section 2.3.4.
Minor edits to RSADC formula in section 2.3.4.
Update of product name from ZMD31050 to ZSC31050.
Changed CD to DVD in ordering code.
Removed die/package option “F.”
Minor edits.
© 2020 Renesas Electronics Corporation
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ZSC31050 Datasheet
Date
February 16, 2010
(Rev. 1.08-1.09)
Description
Addition of units for 1.4.1.2 and change in symbol for 1.5.2.1.
Addition of new design for block diagram and all application schematics.
Update for glossary. Addition of CM/nom information’s in Table 4.
Update for phone number for ZMD Far East, Ltd.
Update for ordering codes description.
Minor edits.
November 30, 2009
(Rev. 1.07)
Reformatted for new ZMDI template.
Addition of “ZSC31050 Feature Sheet” section on pages 2 and 3.
Addition of ordering codes for ZSC31050 and Evaluation Kits.
October 2009
(Rev. 1.05-1.06)
September 2009
(Rev. 1.04)
Reformatted with new ZMDI template.
1.03
Update to “Related Documents” and “Document Revision History.”
Update of company references for ZMDI.
New format for revision numbering in footer.
Note 4 “Default Configuration” added in 5.4.
Overall accuracy / values and conditions for current loop output added in 5.4.7.3.
Reliability / fit rate values added in section 6.
1.01-1.02
Headlines and footnotes at all pages updated.
Input capacitance of digital interface pins added in 5.5.1.7.
1.00
First release of document.
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