810525AGILF

VCXO-TO-LVCMOS/LVTTL OUTPUT ICS810525I GENERAL DESCRIPTION The ICS810525I is a high performance, low jitIC S t e r / l o w p h a s e n o i s e V C X O f r o m I D T. T h e HiPerClockS™ ICS810525I works in conjunction with a 25MHz pullable crystal to generate an LVCMOS/LVTTL output clock of 25MHz from an input clock of 5MHz. The frequency of the VCXO is adjusted by the VC control voltage input. The output range is ±100ppm around the nominal crystal frequency. The LF1 control voltage range is 0 – V DD. The device is packaged in a small 16 TSSOP package and is ideal for use on space constrained boards. FEATURES • One single-ended LVCMOS/LVTTL output • One single-ended clock accepts the following input types: LVCMOS, LVTTL • Accepts input frequency of 5MHz • Absolute pull range: 100ppm • Proprietary multiplier provides low jitter, high frequency output • RMS phase jitter @ 25MHz, using a 25MHz crystal (1kHz – 1MHz): 0.27ps (typical) • Full 3.3V supply, or 3.3V core/2.5V output supply • -40°C to 85°C ambient operating temperature • Available in lead-free (RoHS 6) package BLOCK DIAGRAM XTAL_OUT (External Loop Filter Inputs) PIN ASSIGNMENT nc GND Q VDDO nc nc VDDA VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD CLK GND LF1 LF0 XTAL_IN XTAL_OUT GND XTAL_IN 25MHz LF0 LF1 ICS810525I CLK Pulldown 5MHz x5 VCXO PLL Q 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View IDT ™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT 1 ICS810525AGI REV. B FEBRUARY 24, 2009 ICS810525I VCXO-TO-LVCMOS/LVTTL OUTPUT TABLE 1. PIN DESCRIPTIONS Number 1, 5, 6 2, 9, 14 3 4 7 8, 16 10 , 11 12, 13 15 Name nc GND Q VDDO VDDA VDD XTAL_OUT, XTAL_IN LF0, LF1 CLK Power Output Power Power Power Input Analog Input/Output Input Type Unused Description No connect. Power supply ground. Single-ended clock output. LVCMOS/LVTTL interface levels. Output power supply pin. Analog supply pin. Core power supply pins. VCXO crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Loop filter connection node pins. Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN CPD RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance Input Pulldown Resistor Output Impedance VDDO = 3.3V VDDO = 2.5V VDDO = 3.465V VDDO = 2.625V Test Conditions Minimum Typical 4 8 5 51 15 20 Maximum Units pF pF pF kΩ Ω Ω IDT ™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT 2 ICS810525AGI REV. B FEBRUARY 24, 2009 ICS810525I VCXO-TO-LVCMOS/LVTTL OUTPUT ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, VO 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 92.4°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol VDD VDDA VDDO IDD IDDA Parameter Power Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 VDD – 0.05 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 VDD 3.465 35 5 Units V V V mA mA TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter V DD VDDA VDDO I DD IDDA Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 VDD – 0.05 2.375 Typical 3.3 3.3 2.5 Maximum 3.465 VDD 2.625 35 5 Units V V V mA mA TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol VIH VIL VLF1 IIH IIL II VOH VOL Parameter Input High Voltage Input Low Voltage VCXO Control Voltage Input High Current Input Low Current Input Current of VLF1 pin Output High Voltage Output Low Voltage VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V VDD = 3.465V or 2.625V VDDO = 3.3V ± 5%, IOH = -12mA VDDO = 2.5V ± 5%, IOH = -12mA VDDO = 3.3V or 2.5V ± 5% IOL = 12mA -5 -100 2.6 1.8 0. 5 100 Test Conditions Minimum 2 -0.3 0 Typical Maximum VDD + 0.3 0.8 VDD 15 0 Units V V V µA µA µA V V V IDT ™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT 3 ICS810525AGI REV. B FEBRUARY 24, 2009 ICS810525I VCXO-TO-LVCMOS/LVTTL OUTPUT TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol fOUT Parameter Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time Test Conditions Integration Range: 1kHz – 1MHz 20% to 80% Minimum Typical Maximum 25 0.27 500 1200 Units MH z ps ps tjit(Ø) t R / tF odc Output Duty Cycle 48 52 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. Characterized using a 3kHz bandwidth filter. NOTE 1: Please refer to the Phase Noise Plot. TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol fOUT Parameter Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time Test Conditions Integration Range: 1kHz – 1MHz 20% to 80% Minimum Typical Maximum 25 0.26 600 2100 Units MH z ps ps tjit(Ø) t R / tF odc Output Duty Cycle 44 56 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. Characterized using a 3kHz bandwidth filter. NOTE 1: Please refer to the Phase Noise Plot. IDT ™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT 4 ICS810525AGI REV. B FEBRUARY 24, 2009 ICS810525I VCXO-TO-LVCMOS/LVTTL OUTPUT ➤ TYPICAL PHASE NOISE AT 25MHZ @ 3.3V/3.3V 25MHz Filter RMS Phase Jitter (Random) 1kHz to 1MHz = 0.27ps (typical) NOISE POWER dBc Hz Raw Phase Noise Data ➤ Phase Noise Result by adding a Filter to raw data OFFSET FREQUENCY (HZ) ➤ TYPICAL PHASE NOISE AT 25MHZ @ 3.3V/2.5V 25MHz Filter RMS Phase Jitter (Random) 1kHz to 1MHz = 0.26ps (typical) NOISE POWER dBc Hz ➤ Phase Noise Result by adding a Filter to raw data OFFSET FREQUENCY (HZ) IDT ™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT 5 ➤ Raw Phase Noise Data ➤ ICS810525AGI REV. B FEBRUARY 24, 2009 ICS810525I VCXO-TO-LVCMOS/LVTTL OUTPUT PARAMETER MEASUREMENT INFORMATION 1.65V±5% 1.65V±5% VDD, VDDO VDDA LVCMOS GND Qx 2.05V±5% 1.25V±5% SCOPE VDD VDDO 2.05V±5% SCOPE VDDA Qx LVCMOS GND -1.65V±5% -1.25V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT Phase Noise Plot V DD Noise Power Q t PW Phase Noise Mask t 2 PERIOD f1 Offset Frequency odc = f2 t PW t PERIOD x 100% RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 80% 20% tR 80% 20% tF Q OUTPUT RISE/FALL TIME IDT ™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT 6 ICS810525AGI REV. B FEBRUARY 24, 2009 ICS810525I VCXO-TO-LVCMOS/LVTTL OUTPUT APPLICATION INFORMATION SCHEMATIC EXAMPLE Figure 1 s hows an example of the ICS810525I application schematic. In this example, the device is operated at VDD = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by a 3.3V LVCMOS driver. A 2-pole filter loop filter with Low LBW setting is used in this example. It is recommended to refer to the ICS810525I datasheet for more detail on loop filter values. VDD Q1 R1 Zo = 50 33 Driv er_LVCMOS 16 15 14 13 12 11 10 9 U2 1 2 3 4 5 6 7 8 VDD ICS810525I C5 0.1u C3 0.01u C4 10u VDDO C6 0.1u R2 Q 33 Receiv er Zo = 50 VDD = VDDO = 3.3V 2-pole loop filter with low LBW Setting LF0 Rs 1k Cs 10uF Cp 10nF LF1 LF0 VDD CLK GND LF1 LF0 XTAL_IN XTAL_OUT GND nc GND Q VDDO nc nc VDDA VDD C7 0.1u VDD VDDA R3 10 XTAL_IN C1 TUNE X1 XTAL_OUT C2 TUNE FIGURE 1. ICS810525I SCHEMATIC EXAMPLE IDT ™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT 7 ICS810525AGI REV. B FEBRUARY 24, 2009 ICS810525I VCXO-TO-LVCMOS/LVTTL OUTPUT VCXO-PLL EXTERNAL COMPONENTS Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (C L ). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a cr ystal also var ies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. The crystal’s load capacitance CL characteristic determines its resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (CTUNE). If the crystal’s CL is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specification. If the crystal’s C L is lower than the total external capacitance, the VCXO will oscillate at a lower frequency than the crystal specification. In either case, the absolute tuning range is reduced. The correct value of CL is dependent on the characteristics of the VCXO. The recommended CL in the Crystal Parameter Table balances the tuning range by centering the tuning curve. The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS and C P v alues for recommended high, mid and low loop bandwidth configurations. The device has been characterized using these parameters. For other configurations, refer to the Loop Filter Component Selection for VCXO Based PLLs Application Note. The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. LF0 LF1 RS CP CS XTAL_IN CTUNE 25MHz CTUNE XTAL_OUT VCXO CHARACTERISTICS TABLE Symbol kVCXO CV_LOW CV_HIGH Parameter VCXO Gain Low Varactor Capacitance High Varactor Capacitance Typical 15 9.8 22.7 Unit kHz/V pF pF VCXO-PLL APPROXIMATE LOOP BANDWIDTH SELECTION TABLE Bandwidth 125Hz (Low) 1.5kHz (Mid) 3kHz (High) Crystal Frequency (MHz) 25MHz 25MHz 25MHz RS (kΩ ) 1 12 25 CS (µF) 10 0. 1 0. 1 CP (pF) 10000 10 0 10 0 CRYSTAL CHARACTERISTICS Symbol fN fT fS CL CO CO /C1 ESR Parameter Mode of Operation Frequency Frequency Tolerance Frequency Stability Operating Temperature Range Load Capacitance Shunt Capacitance Pullability Ratio Equivalent Series Resistance Drive Level Aging @ 25°C -40 10 4 22 0 24 0 40 1 ±3 per year Ω mW ppm Minimum Typical 25 ±20 ±20 85 Maximum Units MHz ppm ppm °C pF pF Fundamental IDT ™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT 8 ICS810525AGI REV. B FEBRUARY 24, 2009 ICS810525I VCXO-TO-LVCMOS/LVTTL OUTPUT RELIABILITY INFORMATION TABLE 5. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP θJA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards 92.4°C/W 1 88.0°C/W 2.5 85.9°C/W TRANSISTOR COUNT The transistor count for ICS810525I is: 635 PACKAGE OUTLINE & PACKAGE DIMENSIONS PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP TABLE 6. PACKAGE DIMENSIONS SYMBOL N A A1 A2 b c D E E1 e L α aaa 0.45 0° -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8° 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT 9 ICS810525AGI REV. B FEBRUARY 24, 2009 ICS810525I VCXO-TO-LVCMOS/LVTTL OUTPUT TABLE 7. ORDERING INFORMATION Part/Order Number 810525AGILF 810525AGILFT Marking 10525AIL 10525AIL Package 16 Lead "Lead-Free" TSSOP 16 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT 10 ICS810525AGI REV. B FEBRUARY 24, 2009 ICS810525I VCXO-TO-LVCMOS/LVTTL OUTPUT REVISION HISTORY SHEET Rev B Table T3C Page 3 Description of Change LVCMOS DC Characteristics - added to VOH/VOL test conditions. Date 2/24/09 IDT ™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT 11 ICS810525AGI REV. B FEBRUARY 24, 2009 ICS810525I VCXO-TO-LVCMOS/LVTTL OUTPUT Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT For Tech Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA