813N252AKI-02LF

Jitter Attenuator & FemtoClock NG Multiplier ® ICS813N252I-02 DATA SHEET General Description The ICS813N252I-02 device uses IDT's fourth generation FemtoClock® NG technology for optimal high clock frequency and low phase noise performance, combined with a low power consumption and high power supply noise rejection. The ICS813N252I-02 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. TheICS813N252I-02 is a fully integrated Phase Locked loop utilizing a FemtoClock NG Digital VCXO that provides the low jitter, high frequency SONET/PDH output clock that easily meets OC-48 jitter requirements. This VCXO technology simplifies PLL design by replacing the pullable crystal requirement of analog VCXOs with a fixed 27MHz generator crystal. Jitter attenuation down to 10Hz is provided by an external loop filter. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET and Ethernet applications. The device requires the use of an external, inexpensive fundamental mode 27MHz crystal. The device is packaged in a space-saving 32-VFQFN package and supports industrial temperature range. Features • • • • • • • • • • • • • • • • • VEE Fourth generation FemtoClock® NG technology Two LVPECL output pairs Each output supports independent frequency selection at 25MHz, 125MHz, 156.25MHz and 312.5MHz Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL Accepts input frequencies from 8kHz to 155.52MHz including 8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz, 125MHz and 155.52MHz Crystal interface optimized for a 27MHz, 10pF parallel resonant crystal Attenuates the phase jitter of the input clock by using a low-cost fundamental mode crystal Customized settings for jitter attenuation and reference tracking using an external loop filter connection FemtoClock NG frequency multiplier provides low jitter, high frequency output Absolute pull range: ±100ppm Power supply noise rejection (PSNR): -95dB (typical) FemtoClock NG VCXO frequency: 2500MHz RMS phase jitter @ 156.25MHz, using a 27MHz crystal (12kHz – 20MHz): 0.6ps (typical) RMS phase jitter @ 125MHz, using a 27MHz crystal (12kHz – 20MHz): 0.63ps (typical) 3.3V supply voltage -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment XTAL_OUT XTAL_IN nCLK0 CLK0 nCLK1 CLK1 VCCX 32 31 30 29 28 27 26 25 LF1 LF0 1 2 24 VCC 23 nQB 22 21 QB VCCO ISET 3 VEE 4 CLK_SEL VCC 5 6 20 nQA 19 QA 18 17 9 PDSEL_2 RESERVED 7 VEE 8 10 11 12 13 14 15 16 ODBSEL_1 ODBSEL_0 ODASEL_1 PDSEL_1 PDSEL_0 VCC VCCA VEE ODASEL_0 ICS813N252I-02 32 Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View ICS813N252AKI-02 REVISION B MAY 27, 2011 1 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Block Diagram 27MHz Pulldown 2 ODASEL _[1:0] Xtal Osc. Pullup 3 DIGITAL VCXO ÷NA QA, nQA PDSEL _[2:0] CLK_SEL Pulldown PD + LF FemtoClock NG VCO ÷NB Pulldown QB, nQB CLK0 , nCLK 0 Pullup / Pulldown Pulldown 0 ÷P Fractional Feedback Divider Phase Detector + Charge Pump Pulldown 2 ODBSEL _[1:0] CLK1 , nCLK 1 1 A/ D Control Block Pullup / Pulldown ÷M ISET LF0 LF1 *** Dashed lines indicates external components ICS813N252AKI-02 REVISION B MAY 27, 2011 2 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Table 1. Pin Descriptions Number 1, 2 3 4, 8, 18, 24 5 6, 12, 27 7 9, 10, 11 13 14, 15 16, 17 19, 20 21 22, 23 25 26 28 29 30, 31 32 Name LF1, LF0 ISET VEE CLK_SEL VCC RESERVED PDSEL_2, PDSEL_1, PDSEL_0 VCCA ODBSEL_1, ODBSEL_0 ODASEL_1, ODASEL_0 QA, nQA VCCO QB, nQB nCLK1 CLK1 nCLK0 CLK0 XTAL_OUT, XTAL_IN VCCX Type Analog Input/Output Analog Input/Output Power Input Power Reserve Input Power Input Input Output Power Output Input Input Input Input Input Power Pullup/ Pulldown Pulldown Pullup/ Pulldown Pulldown Pulldown Pulldown Pullup Pulldown Description Loop filter connection node pins. LF0 is the output. LF1 is the input. Charge pump current setting pin. Negative supply pins. Input clock select. When HIGH selects CLK1, nCLK1. When LOW, selects CLK0, nCLK0. LVCMOS / LVTTL interface levels. Core supply pins. Reserved pin. Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A. Analog supply pin. Frequency select pins for Bank B output. See Table 3B. LVCMOS/LVTTL interface levels. Frequency select pins for Bank A output. See Table 3B. LVCMOS/LVTTL interface levels. Differential Bank A clock outputs. LVPECL interface levels. Output supply pin. Differential Bank B clock outputs. LVPECL interface levels. Inverting differential clock input. VCC/2 bias voltage when left floating. Non-inverting differential clock input. Inverting differential clock input. VCC/2 bias voltage when left floating. Non-inverting differential clock input. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Power supply pin for the crystal oscillator. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 2 51 51 Maximum Units pF kΩ kΩ ICS813N252AKI-02 REVISION B MAY 27, 2011 3 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Function Tables Table 3A. Pre-Divider Selection Function Table Inputs PDSEL_2 0 0 0 0 1 1 1 1 PDSEL_1 0 0 1 1 0 0 1 1 PDSEL_0 0 1 0 1 0 1 0 1 ÷P Value 1 193 256 1944 2500 7776 12500 15552 (default) Table 3B. Output Divider Function Table Inputs ODxSEL_1 0 0 1 1 ODxSEL_0 0 1 0 1 ÷Nx Value 100 (default) 20 16 8 NOTE: x denotes A or B. ICS813N252AKI-02 REVISION B MAY 27, 2011 4 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Table 3C. Frequency Function Table Input Frequency (MHz) 0.008 0.008 0.008 0.008 1.544 1.544 1.544 1.544 2.048 2.048 2.048 2.048 19.44 19.44 19.44 19.44 25 25 25 25 77.76 77.76 77.76 77.76 125 125 125 125 155.52 155.52 155.52 155.52 ÷P Value 1 1 1 1 193 193 193 193 256 256 256 256 1944 1944 1944 1944 2500 2500 2500 2500 7776 7776 7776 7776 12500 12500 12500 12500 15552 15552 15552 15552 FemtoClock NG VCXO Center Frequency (MHz) 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 ÷Nx Value 100 20 16 8 100 20 16 8 100 20 16 8 100 20 16 8 100 20 16 8 100 20 16 8 100 20 16 8 100 20 16 8 Output Frequency (MHz) 25 125 156.25 312.5 25 125 156.25 312.5 25 125 156.25 312.5 25 125 156.25 312.5 25 125 156.25 312.5 25 125 156.25 312.5 25 125 156.25 312.5 25 125 156.25 312.5 NOTE: x denotes A or B. ICS813N252AKI-02 REVISION B MAY 27, 2011 5 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VCC Inputs, VI XTAL_IN Other Inputs Outputs, IO Continuous Current Surge Current Package Thermal Impedance, θJA Storage Temperature, TSTG Rating 3.63V 0V to 2V -0.5V to VCC+ 0.5V 50mA 100mA 33.1°C/W (0 mps) -65°C to 150°C DC Electrical Characteristics Table 4A. LVPECL Power Supply DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol VCC VCCA VCCO VCCX IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Crystal Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 VCC – 0.30 3.135 3.135 Typical 3.3 3.3 3.3 3.3 Maximum 3.465 VCC 3.465 3.465 273 30 Units V V V V mA mA Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, TA = -40°C to 85°C Symbol VIH VIL Parameter Input High Voltage Input Low Voltage CLK_SEL, ODASEL_[1:0], ODBSEL_[1:0] PDSEL_[2:0] CLK_SEL, ODASEL_[1:0], ODBSEL_[1:0] PDSEL_[2:0] VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465, VIN = 0V -10 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 10 Units V V µA µA µA µA IIH Input High Current IIL Input Low Current ICS813N252AKI-02 REVISION B MAY 27, 2011 6 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Table 4C. Differential DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, TA = -40°C to 85°C Symbol IIH IIL VPP VCMR Parameter Input High Current CLK0, nCLK0, CLK1, nCLK1 CLK0, CLK1 Input Low Current nCLK0, nCLK1 Peak-to-Peak Input Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1, 2 Test Conditions VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -10 -150 0.15 VEE 1.3 VCC – 0.85 Minimum Typical Maximum 150 Units µA µA µA V V NOTE 1: VIL should not be less than -0.3V. NOTE 2. Common mode voltage is defined at the crosspoint. Table 4D. LVPECL DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO – 1.10 VCCO – 2.0 0.6 Typical Maximum VCCO – 0.75 VCCO – 1.6 1.0 Units V V V NOTE 1: Outputs terminated with 50Ω to VCCO – 2V. See Parameter Measurement Information section, 3.3V Output Load Test Circuit. ICS813N252AKI-02 REVISION B MAY 27, 2011 7 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER AC Electrical Characteristics Table 5. AC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, TA = -40°C to 85°C Symbol fIN fOUT Parameter Input Frequency Output Frequency RMS Phase Jitter, (Random), NOTE 1 Power Supply Noise Rejection; NOTE 2 Output Skew; NOTE 3, 4 Output Rise/Fall Time Output Duty Cycle Output-to-Input Phase Lock Time; NOTE 5 Reference Clock Input is ±100ppm from Nominal Frequency 20% to 80% 150 48 4 125MHz fOUT, 27MHz crystal, Integration Range: 12kHz – 20MHz 156.25MHz fOUT, 27MHz crystal, Integration Range: 12kHz – 20MHz VPP = 50mV Sine Wave, Range: 10kHz – 10MHz Test Conditions Minimum 0.008 25 0.63 0.6 -95 80 450 52 Typical Maximum 155.52 312.5 Units MHz MHz ps ps dB ps ps % s tjit(Ø) PSNR tsk(o) tR / tF odc tLOCK NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized with outputs at the same frequency using the loop filter components for the 35Hz loop bandwidth. Refer to Jitter Attenuator Loop Bandwidth Selection Table. NOTE 1: Refer to the Phase Noise Plot. NOTE 2: PSNR results achieved by injecting noise on VCCA supply pin with no external filter network. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 5: Lock Time measured from power-up to stable output frequency. ICS813N252AKI-02 REVISION B MAY 27, 2011 8 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Typical Phase Noise at 125MHz Noise Power dBc Hz Offset Frequency (Hz) ICS813N252AKI-02 REVISION B MAY 27, 2011 9 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Parameter Measurement Information 2V 2V VCC VCC, VCCO, VCCX Qx VCCA SCOPE nCLK[0:1] V PP Cross Points LVPECL nQx VEE CLK[0:1] V CMR VEE -1.3V ± 0.165V 3.3V LVPECL Output Load AC Test Circuit Differential Input Level VCC Noise Power Phase Noise Plot Supply Voltage VEE 60% of VCC Output-to-Input Phase Lock Output f1 Lock Time Offset Frequency f2 Not to Scale RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers Output-to-Input Phase Lock Time RMS Phase Jitter nQx Qx nQy Qy nQA, nQB 80% 80% VSW I N G QA, QB 20% tR tF 20% t sk(o) Output Skew LVPECL Output Rise/Fall Time nQA, nQB QA, QB t PW t PERIOD odc = t PW t PERIOD x 100% Output Duty Cycle/Pulse Width/Period ICS813N252AKI-02 REVISION B MAY 27, 2011 10 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Applications Information Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50Ω applications, R3 and R4 can be 100Ω. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS813N252AKI-02 REVISION B MAY 27, 2011 11 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 2A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK Zo = 50Ω nCLK Zo = 50Ω nCLK CLK LVPECL Differential Input R1 50Ω R2 50Ω Differential Input LVHSTL IDT LVHSTL Driver R1 50Ω R2 50Ω R2 50Ω Figure 2A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver Figure 2B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V Zo = 50Ω CLK CLK Zo = 50Ω nCLK R1 100Ω 3.3V R3 125Ω R4 125Ω 3.3V Zo = 50Ω LVPECL R1 84Ω R2 84Ω Differential Input Zo = 50Ω nCLK LVDS Receiver Figure 2C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2D. CLK/nCLK Input Driven by a 3.3V LVDS Driver 3.3V 3.3V 2.5V 3.3V 2.5V *R3 33Ω Zo = 50Ω CLK Zo = 50Ω nCLK Zo = 60Ω R3 120Ω R4 120Ω CLK Zo = 60Ω nCLK HCSL *R4 33Ω R1 50Ω R2 50Ω Differential Input SSTL R1 120Ω R2 120Ω Differential Input *Optional – R3 and R4 can be 0Ω Figure 2E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS813N252AKI-02 REVISION B MAY 27, 2011 12 Figure 2F. CLK/nCLK Input Driven by a 2.5V SSTL Driver ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Recommendations for Unused Input and Output Pins Inputs: CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. 3.3V 3.3V Zo = 50Ω + 3.3V R3 125Ω Zo = 50Ω 3.3V R4 125Ω 3.3V + _ LVPECL Zo = 50Ω R1 50Ω RTT = 1 * Zo ((VOH + VOL) / (VCC – 2)) – 2 R2 50Ω VCC - 2V RTT Input LVPECL Zo = 50Ω R1 84Ω R2 84Ω _ Input Figure 3A. 3.3V LVPECL Output Termination Figure 3B. 3.3V LVPECL Output Termination ICS813N252AKI-02 REVISION B MAY 27, 2011 13 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Jitter Attenuator EXTERNAL COMPONENTS Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the Jitter Attenuator. In choosing a crystal, special precaution must be taken with load capacitance (CL), frequency accuracy and temperature range. The crystal’s CL characteristic determines its resonating frequency and is closely related to the center tuning of the crystal. The total external capacitance seen by the crystal when installed on a PCB is the sum of the stray board capacitance, IC package lead capacitance, internal device capacitance and any installed tuning capacitors (CTUNE). The recommended CLin the Crystal Parameter Table balances the tuning range by centering the tuning curve for a typical PCB. If the crystal CL is greater than the total external capacitance, the crystal will oscillate at a higher frequency than the specification. If the crystal CL is lower than the total external capacitance, the crystal will oscillate at a lower frequency than the specification. Tuning adjustments might be required depending on the PCB parasitics or if using a crystal with a higher CL specification. In addition, the frequency accuracy specification in the crystal characteristics table are used to calculate the APR (Absolute Pull Range). LF0 LF1 ISET RS CP CS RSET XTAL_IN CTUNE 27MHz CTUNE XTAL_OUT Crystal Characteristics Symbol fN fT fS CL CO ESR Parameter Mode of Oscillation Frequency Frequency Tolerance Frequency Stability Operating Temperature Range Load Capacitance Shunt Capacitance Equivalent Series Resistance Drive Level Aging @ 25 0C First Year -40 10 4 40 1 ±3 Test Conditions Minimum Typical Fundamental 27 ±20 ±20 +85 MHz ppm ppm 0C Maximum Units pF pF Ω mW ppm The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS,CP and RSET values for recommended high, mid and low loop bandwidth configurations. The device has been characterized using these parameters. In addition, the digital VCXO gain (KVCXO) has been provided for additional loop filter requirements. Jitter Attenuator Characteristics Table Symbol kVCXO Parameter VCXO Gain Typical 2.76 Units kHz/V Jitter Attenuator Loop Bandwidth Selection Table Bandwidth 7Hz (Low) 35Hz (Mid) 45Hz (High) Crystal Frequency 27MHz 27MHz 27MHz RS (kΩ) 110 365 470 CS (µF) 10 1 1 CP (µF) 0.01 0.002 0.0005 RSET (kΩ) 2.21 1.5 1.5 The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. ICS813N252AKI-02 REVISION B MAY 27, 2011 14 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. PIN SOLDER EXPOSED HEAT SLUG SOLDER PIN PIN PAD GROUND PLANE THERMAL VIA LAND PATTERN (GROUND PAD) PIN PAD Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ICS813N252AKI-02 REVISION B MAY 27, 2011 15 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Schematic Example Figure 5 (on next page) shows an example of ICS813N252I-02 application schematic. In this example, the device is operated at VCC = VCCX = VCCO = 3.3V. A 10pF parallel resonant 27MHz crystal is used. Spare placement pads for the load capacitance C1 and C2 are recommended for frequency accuracy. Depending on the parasitics of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. This will required adjusting C1 and C2. An Optional 3-pole filter can also be used for additional spur reduction. It is recommended that the loop filter components be laid out for the 3-pole option. This will allow the flexibility for the 2-pole filter to be used. As with any high speed analog circuitry, the power supply pins are vulnerable to noise. To achieve optimum jitter performance, power supply isolation is required. The ICS813N252I-02 provides separate power supplies to isolate from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uF capacitor in each power pin filter should be placed on the device side of the PCB and the other components can be placed on the opposite side. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. ICS813N252AKI-02 REVISION B MAY 27, 2011 16 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER VCC R1 125 VCC R2 125 Logic Control Input Examples VCC Zo = 50 CLK1 R5 125 R6 125 Set Logic Input to '1' RU1 1K VCC Set Logic Input to '0' RU2 Not Install Zo = 50 LVPECL Driv er nCLK1 Zo = 50 CLK0 nCLK0 R20 84 R4 84 To Logic Input pins RD1 Not Install To Logic Input pins RD2 1K Zo = 50 LVPECL Driv er R7 84 R8 85 3-pole loop filter example - (optional) R3 LF Rs 365k LF 3.3V XTAL_OUT 820k C1 TUNE 1 3.3V BLM18BB221SN1 2 C LK1 nC LK1 C2 TUNE C LK0 nC LK0 R11 10 VCC VCCX C4 0.1u U1 32 31 30 29 28 27 26 25 C5 10u 2-pole loop filter for Mid Bandwidth setting LF Rs 365k VCC Cs 1uF Cp 0.002uF VC C X XT AL_IN XT AL_OU T C LK0 nC LK0 VC C C LK1 nC LK1 LF 1 2 3 4 5 6 7 8 LF1 LF0 ISET VEE CLK_SEL VCC RESERVED VEE CLK_SEL C7 0.1u R14 1.5K PD SEL2 PD SEL_1 PD SEL_0 VC C VC C A OD BSEL_1 OD BSEL_0 OD ASEL_1 3.3V 1 9 10 11 12 13 OD BSEL_1 14 OD BSEL_0 15 OD ASEL_1 16 PD SEL_2 PD SEL_1 PD SEL_0 BLM18BB221SN1 2 VCC Ferrite Bead C6 C5 0.1uF 10uF Figure 5. ICS813N252I-02 Schematic Example ICS813N252AKI-02 REVISION B MAY 27, 2011 Fp01 XTAL_IN C8 0.1u C9 0.1u Cs 1uF Cp 0.002uF C3 220pF 27MHz X1 Ferrite Bead C6 C5 0.1uF R9 133 Zo = 50 Ohm 10uF R10 133 + VCC Zo = 50 Ohm C11 0.1u R12 82.5 - R13 82.5 VCCO 0.1u C6 LVPECL Termination VEE nQB QB VCCO nQA QA VEE ODASEL_0 24 23 22 21 20 19 18 17 nQB QB nQA QA ODASEL_0 Zo = 50 Ohm + Zo = 50 Ohm R15 50 R16 50 LVPECL Optional Y-Termination VCCA R19 10 R18 50 VCC C10 10u 17 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Power Considerations This section provides information on power dissipation and junction temperature for the ICS813N252I-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS813N252I-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCCO = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCCO_MAX * IEE_MAX = 3.465V * 273mA = 945.945mW Power (outputs)MAX = 31.55mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 31.55mW = 63.1mW Total Power_MAX (3.3V, with all outputs switching) = 945.945mW + 63.1mW = 1009.045mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 33.1°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C +1.009W * 33.1°C/W = 118.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 33.1°C/W 1 28.1°C/W 3 25.4°C/W ICS813N252AKI-02 REVISION B MAY 27, 2011 18 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50Ω VCCO - 2V Figure 6. LVPECL Driver Circuit and Termination o calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO – 2V. • • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.75V (VCC_MAX – VOH_MAX) = 0.75V For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.6V (VCC_MAX – VOL_MAX) = 1.6V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V– (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) = [(2V– 0.75V)/50Ω] * 0.75V = 18.75mW Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – 1.6V)/50Ω] * 1.6V = 12.80mW Total Power Dissipation per output pair = Pd_H + Pd_L = 31.55mW ICS813N252AKI-02 REVISION B MAY 27, 2011 19 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Reliability Information Table 7. θJA vs. Air Flow Table for a 32 Lead VFQFN θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 33.1°C/W 1 28.1°C/W 3 25.4°C/W Transistor Count The transistor count for ICS813N252I-02 is: 44,832 ICS813N252AKI-02 REVISION B MAY 27, 2011 20 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Package Outline and Package Dimensions Package Outline - K Suffix for 32 Lead VFQFN S eating Plan e Ind ex Area N A1 A3 L N 1 2 E2 (N -1)x e E2 2 (Re f.) (Ref.) (N -1)x e (R ef.) N &N Even e (Ty p.) 2 If N & N Anvil Anvil Singulation Singula tion are Even OR To p View b A D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C (Ref.) e D2 2 D2 N &N Odd Th er mal Ba se Bottom View w/Type A ID Bottom View w/Type C ID 2 1 CHAMFER 2 1 RADIUS 4 N N-1 4 N N-1 There are 2 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) Table 8. Package Dimensions JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 ND & NE 8 D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS813N252AKI-02 REVISION B MAY 27, 2011 21 NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8. ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Ordering Information Table 9. Ordering Information Part/Order Number 813N252AKI-02LF 813N252AKI-02LFT Marking ICS252AI02L ICS252AI02L Package “Lead-Free” 32 Lead VFQFN “Lead-Free” 32 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS813N252AKI-02 REVISION B MAY 27, 2011 22 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Revision History Sheet Rev A 16 - 17 A A B 16 - 17 6 2 Table Page 11 Description of Change Deleted Power Supply Filtering Technique application section (included in schematic application). Updated schematic application. Updated schematic application with 10pF from 12pF. Supply Voltage, VCC. Rating changed from 4.5V min. to 3.63V per Errata NEN-11-03. Correct typo in block diagram from /2 to /3 for PDSEL[2:0] Date 1/14/11 2/8/11 5/20/11 5/27/11 ICS813N252AKI-02 REVISION B MAY 27, 2011 23 ©2011 Integrated Device Technology, Inc. ICS813N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2011. All rights reserved.