814S208BKILFT

FemtoClock® Crystal-to-LVDS 8-Output Clock Synthesizer ICS814S208I DATA SHEET General Description The ICS814S208I is an eight LVDS output clock synthesizer designed for wireless infrastructure applications. The device generates eight copies of a selectable 122.88MHz or 153.6MHz clock signal with excellent phase jitter performance. The PLL is optimized for a reference frequency of 30.72MHz. Both a crystal interface and a differential system clock input are supported for the reference frequency. An extra LVDS output duplicates the reference frequency and is provided for clock tree cascading. The device uses IDT’s third generation FemtoClock® technology for an optimum of high clock frequency and low phase noise performance, combined with a low power consumption. A PLL lock status output is provided for monitoring and diagnosis purpose. The device supports a 3.3V voltage supply and is packaged in a small, lead-free (RoHS 6) 48-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. Features • • • • • • • • • • • • Third generation FemtoClock® technology Selectable 122.88MHz or 153.6MHz output clock synthesized from a 30.72MHz fundamental mode crystal Eight differential LVDS clock outputs Differential reference clock input pair PLL lock indicator output Crystal interface designed for a 30.72MHz, parallel resonant crystal RMS phase jitter @ 122.88MHz, using a 30.72MHz crystal (12kHz - 20MHz): 0.650ps (typical) RMS phase jitter @ 153.6MHz, using a 30.72MHz crystal (12kHz - 20MHz): 0.642ps (typical) LVCMOS interface levels for the control input Full 3.3V supply voltage Available in Lead-free (RoHS 6) 48-lead VFQFN package -40°C to 85°C ambient operating temperature Block Diagram nOE_A XTAL_IN OSC XTAL_OUT REF_CLK nREF_CLK REF_SEL BW[1:0] BYPASS N_SEL nOE_B0 nOE_B1 nOE_B2 Pulldown Pullup/ Pulldown Pulldown Pulldown (2) Pulldown Pulldown Pulldown Pulldown Pulldown 1 0 Pulldown QLOCK 1 fREF QA nQA QB0 nQB0 QB1 nQB1 QB2 nQB2 QB3 nQB3 QB4 nQB4 QB5 nQB5 QB6 nQB6 QB7 nQB7 PFD & LPF FemtoClock® VCO 570MHz - 640MHz ÷20 ÷20 0 N ÷5, ÷4 2 ICS814S208BKILF REVISION B OCTOBER 13, 2011 1 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER Pin Assignment REF_SEL BYPASS nOE_B0 nOE_B1 nOE_B2 48 47 46 45 44 43 42 41 40 39 38 37 XTAL_IN XTAL_OUT VDD REF_CLK nREF_CLK GND VDDOL QLOCK GND QA nQA VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 VDD nQB7 QB7 nQB6 QB6 GND VDD nQB5 QB5 nQB4 QB4 GND GND GND VDD nQB0 nQB1 nQB2 ICS814S208I 48-lead VFQFN 7.0mm x 7.0mm x 0.925mm, package body K Package Top View ICS814S208BKILF REVISION B OCTOBER 13, 2011 2 nQB3 VDD QB0 QB1 QB2 QB3 nOE_A N_SEL VDDA GND GND BW1 BW0 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER Table 1. Pin Descriptions Number 1, 2 3, 12, 18, 24, 30, 36 4 5 6, 9, 13, 19, 25, 31, 41, 48 7 8 10, 11 14, 15 16, 17 20, 21 22, 23 26, 27 28, 29 32, 33 34, 35 37 38, 39, 45 40 42 43, 44 46 47 Name XTAL_IN, XTAL_OUT VDD REF_CLK nREF_CLK GND VDDOL QLOCK QA, nQA QB0, nQB0 QB1, nQB1 QB2, nQB2 QB3, nQB3 QB4, nQB4 QB5, nQB5 QB6, nQB6 QB7, nQB7 nOE_A nOE_B2, nOE_B1, nOE_B0 N_SEL VDDA BW0, BW1 BYPASS REF_SEL Input Power Input Input Power Power Output Output Output Output Output Output Output Output Output Output Input Pulldown Pulldown Pullup/ Pulldown Type Description Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Core power supply pins. Non-inverting differential reference clock input. Differential output can accept the following differential input levels: LVPECL, LVDS, CML. Inverting differential reference clock input. Differential output can accept the following differential input levels: LVPECL, LVDS, CML. Power supply ground. Output supply pin for the PLL lock output (QLOCK). Supports 3.3V, 2.5V or 1.8V. PLL lock indication. See Table 3I for function. Supports 3.3V, 2.5V or 1.8V. Differential clock output pair. LVDS interface levels. Differential clock output pair. LVDS interface levels Differential clock output pair. LVDS interface levels Differential clock output pair. LVDS interface levels Differential clock output pair. LVDS interface levels Differential clock output pair. LVDS interface levels Differential clock output pair. LVDS interface levels Differential clock output pair. LVDS interface levels Differential clock output pair. LVDS interface levels Output enable input. See Table 3E for function. LVCMOS/LVTTL interface levels. Output enable inputs. See Tables 3F-3H for function. LVCMOS/LVTTL interface levels. Frequency select pin. See Table 3A for function. LVCMOS/LVTTL interface levels. Analog power supply. Pulldown Pulldown Pulldown PLL bandwidth control pins. See Table 3D for function. LVCMOS/LVTTL interface levels. PLL bypass mode select pin. See Table 3B for function. LVCMOS/LVTTL interface levels. Reference select input. See Table 3C for function. LVCMOS/LVTTL interface levels. Input Pulldown Input Power Input Input Input Pulldown NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. ICS814S208BKILF REVISION B OCTOBER 13, 2011 3 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER Table 2. Pin Characteristics Symbol CIN RPULLDOWN RPULLUP Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor QLOCK = HIGH, VDDOL = 3.3V ROUT Output Impedance QLOCK QLOCK = HIGH, VDDOL = 2.5V QLOCK = HIGH, VDDOL = 1.8V QLOCK = LOW, VDDOL = 3.3V, 2.5V, 1.8V Test Conditions Minimum Typical 2 51 51 26 32 44 22 Maximum Units pF kΩ kΩ Ω Ω Ω Ω Function Tables Table 3A. Output Divider N Function Table Inputs N_SEL 0 (default) 1 N ÷5 ÷4 Operation QB[0:7] Frequency with fREF = 30.72MHz 122.88MHz, (4 * fREF) 153.6MHz, (5 * fREF) NOTE: N_SEL is an asynchronous control. NOTE: With fXTAL= 30.72MHz and all control inputs in the default state, the ICS814S208I generates 30.72MHz at the QA output and 122.88MHz at the QBx outputs. Table 3B. PLL BYPASS Function Table Input BYPASS 0 (default) 1 Operation QA fOUT, QA = fVCO ÷ 20 fOUT, QA = fREF (PLL bypass) QB[0:7] fOUT, QBx = fREF * 20 ÷ N NOTE: BYPASS is an asynchronous control. NOTE: In PLL bypass mode, the frequency fREF is output at QA without frequency division. AC specifications do not apply in PLL bypass mode. Table 3C. PLL Reference Clock Select Function Table Input REF_SEL 0 (default) 1 Operation The crystal interface is selected as reference clock The REF_CLK input is selected as reference clock NOTE: REF_SEL is an asynchronous control. ICS814S208BKILF REVISION B OCTOBER 13, 2011 4 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER Table 3D. PLL Bandwidth Function Table Inputs BW1 0 (default) 0 (default) 1 1 BW0 0 (default) 1 0 (default) 1 Operation PLL Bandwidth 240kHz 520kHz 1MHz 2MHz NOTE: BW[1:0] is an asynchronous control. NOTE: With the lowest PLL bandwidth setting (BW[1:0] = 00, 240kHz), the PLL attenuates input reference jitter with spectral components above 240kHz. With the highest PLL bandwidth setting (BW[1:0] = 11, 2MHz), the PLL is not optimized for input reference jitter attenuation. Table 3E. nOE_A Output Enable Function Table Input nOEA 0 (default) 1 Operation QA, nQA outputs are enabled QA, nQA outputs are disabled (high-impedance) Table 3I. QLOCK Output Function Table Output QLOCK 0 1 PLL Status The PLL is locked to the input reference clock The PLL is not locked to the input reference clock NOTE: nOE_A is an asynchronous control. NOTE: QLOCK supports 3.3V, 2.5V or 1.8V according to the voltage supplied at VDDOL. See Table 4B. Table 3F. nOE_B0 Output Enable Function Table Input nOE_B0 0 (default) 1 Operation QB[0:3], nQB[0:3] outputs are enabled QB[0:3]. nQB[0:3] outputs are disabled (high-impedance) NOTE: nOE_B0 is an asynchronous control. Table 3G. nOE_B1 Output Enable Function Table Input nOE_B1 0 (default) 1 Operation QB[4:5], nQB[4:5] outputs are enabled QB[4:5], nQB[4:5] outputs are disabled (high-impedance) NOTE: nOE_B1 is an asynchronous control. Table 3H. nOE_B2 Output Enable Function Table Input nOE_B2 0 (default) 1 Operation QB[6:7], nQB[6:7] outputs are enabled QB[6:7], nQB[6:7] outputs are disabled (high-impedance) NOTE: nOE_B2 is an asynchronous control. ICS814S208BKILF REVISION B OCTOBER 13, 2011 5 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI XTAL_IN Other Inputs Outputs, VO (LVCMOS) Outputs, IO (LVDS) Continuous Current Surge Current Package Thermal Impedance, θJA Storage Temperature, TSTG Rating 4.6V 0V to VDD -0.5V to VDD + 0.5V -0.5V to VDD + 0.5V 10mA 15mA 30.5°C/W (0 mps) -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, VDDOL = 1.8V±0.2V, 2.5V±5% or 3.3V±5%, TA = -40°C to 85°C Symbol VDD VDDA Parameter Core Supply Voltage Analog Supply Voltage Test Conditions Minimum 3.135 VDD – 0.22 1.6 VDDOL QLOCK Output Supply Voltage 2.375 3.135 IDDA IDD Analog Supply Current Power Supply Current Typical 3.3V 3.3V 1.8 2.5 3.3 Maximum 3.465 VDD 2.0 2.625 3.465 22 355 Units V V V V V mA mA NOTE: For the Power Supply Voltage Sequence Information Application Note, see page 12. ICS814S208BKILF REVISION B OCTOBER 13, 2011 6 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V±5%, VDDOL = 1.8V±0.2V, 2.5V±5% or 3.3V±5%, TA = -40°C to 85°C Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage BW[1:0], BYPASS, nOE_A, nOE_B[2:0], REF_SEL, N_SEL BW[1:0], BYPASS, nOE_A, nOE_B[2:0], REF_SEL, N_SEL Test Conditions VDD = 3.3V VDD = 3.3V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDDOL = 3.465V, IOH = -8mA VOH QLOCK VDDOL = 2.625V, IOH = -8mA VDDOL = 2V, IOH = -8mA VOL Output Low Voltage QLOCK VDDOL = 3.465V or 2.625V, IOL = 8mA VDDOL = 2V, IOL = 8mA -10 2.6 1.8 1.5 0.5 0.4 Minimum 2.2 -0.3 Typical Maximum VDD + 0.3 0.8 150 Units V V µA µA V V V V V Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol IIH IIL VPP VCMR Parameter Input High Current REF_CLK, nREF_CLK REF_CLK Input Low Current nREF_CLK Peak-to-Peak Voltage Common Mode Input Voltage; NOTE 1 Test Conditions VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -10 -150 0.15 GND + 1.2 1.0 VDD Minimum Typical Maximum 150 Units µA µA µA V V NOTE 1: Common mode input voltage is defined as VIH. Table 4D. LVDS DC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C Symbol VOD ∆VOD VOS ∆VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 1.125 Test Conditions Minimum 247 Typical Maximum 454 50 1.375 50 Units mV mV V mV Table 5. Crystal Characteristics Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level; NOTE 1 NOTE 1: Using typical crystal parameter for ESR, CO, and CL in a 30.72MHz crystal. ICS814S208BKILF REVISION B OCTOBER 13, 2011 7 ©2011 Integrated Device Technology, Inc. Test Conditions Minimum Typical Fundamental Maximum Units 28.5 30.72 32 80 7 100 MHz Ω pF µW ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER AC Electrical Characteristics Table 6. AC Characteristics, VDD = 3.3V±5%, VDDOL = 1.8V±0.2V, 2.5V±5% or 3.3V±5%, TA = -40°C to 85°C Symbol fVCO fOUT fREF Parameter VCO Frequency Output Frequency QB[0:7], nQB[0:7] QA, nQA Reference Frequency Test Conditions BYPASS = 0 N_SEL = 0 N_SEL = 1 BYPASS = 0 BYPASS = 0 122.88MHz, Integration Range: 1kHz – 40MHz RMS Phase Jitter (Random); NOTE 1 122.88MHz, Integration Range: 12kHz – 20MHz 153.6MHz, Integration Range: 1kHz – 40MHz 153.6MHz, Integration Range: 12kHz – 20MHz 122.88MHz, Offset: 100Hz ΦN Single-Side Band Noise Power 122.88MHz, Offset: 1kHz 122.88MHz, Offset: 10kHz 122.88MHz, Offset: 100kHz QA, nQA tjit(per) Period Jitter, RMS QBx, nQBx QBx, nQBx TIE tPD tsk(o) tsk(b) t R / tF tLOCK odc Time Interval Error Propagation Delay; NOTE 2 Output Skew; NOTE 3, 4 Bank Skew; NOTE 4, 5 Output Rise/Fall Time PLL Lock Time Output Duty Cycle QA, nQA QBx, nQBx BYPASS = 0 BYPASS = 0 49 49 10% to 90% 75 at 122.88MHz Accumulated Period Jitter, 106 Samples REF_CLK, nREF_CLK to QA, nQA, BYPASS = 1, REF_SEL = 1 BYPASS = 0 550 Minimum 570 114 142.5 28.5 28.5 Typical 614.4 122.88 153.6 30.72 30.72 0.695 0.650 0.714 0.642 -91 -118 -130 -128 2.1 2.3 2.3 ±9 770 25 25 200 20 50 50 4.0 4.8 4.0 ±30 950 100 100 350 100 51 51 Maximum 640 128 160 32 32 0.96 0.89 0.93 0.89 Units MHz MHz MHz MHz MHz ps ps ps ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz ps ps ps ps ps ps ps ps ms % % tjit(Ø) NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized using Rohde & Schwarz SMA100A Signal Generator with fREF = 30.72MHz, unless noted otherwise. VDD and VDDA connected. BW[1:0] = 00. NOTE 1: Refer to the phase noise plots. NOTE 2: Measured from the differential input crossing point to the differential output crossing point. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. ICS814S208BKILF REVISION B OCTOBER 13, 2011 8 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER Typical Phase Noise at 122.88MHz 122.88MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.650ps (typical) Noise Power dBc Hz Offset Frequency (Hz) Typical Phase Noise at 153.6MHz 153.6MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.642ps (typical) Noise Power dBc Hz Offset Frequency (Hz) ICS814S208BKILF REVISION B OCTOBER 13, 2011 9 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER Parameter Measurement Information VDD SCOPE 3.3V±5% POWER SUPPLY + Float GND – VDD VDDA Qx nREF_CLK V PP Cross Points V CMR nQx REF_CLK GND 3.3V LVDS Output Load AC Test Circuit Differential Input Level nQBx QBx nQBy QBy nQA QA nQBy QBy t sk(b) t sk(o) Bank Skew Output Skew VOH VREF VOL Noise Power Phase Noise Plot 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Reference Point (Trigger Edge) Histogram Mean Period (First edge after trigger) f1 Offset Frequency f2 RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers Period Jitter, RMS RMS Phase Jitter ICS814S208BKILF REVISION B OCTOBER 13, 2011 10 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER Parameter Measurement Information, continued nQA, nQBx nQA, nQBx 90% 90% VOD QA, QBx t PW t PERIOD QA, QBx 10% tR tF 10% odc = t PW t PERIOD x 100% Output Rise and Fall Time Output Duty Cycle/Pulse Width/Period nREF_CLK REF_CLK nQA VDD ➤ out DC Input QA LVDS ➤ 100 VOD/∆ VOD out ➤ tPD Propagation Delay Differential Output Voltage Setup Propagation Delay Ideal clock edge positions VDD out ➤ DC Input LVDS out ➤ TIE0 ➤ TIE1 TIE2 TIEN VOS/∆ VOS Time TIE: Time Interval Error = min, mean and max of TIE0...N Offset Voltage Setup Time Interval Error ICS814S208BKILF REVISION B OCTOBER 13, 2011 11 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER Applications Information Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50Ω applications, R3 and R4 can be 100Ω. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels Power Supply Voltage Sequence Information No power sequence restrictions apply if VDD and VDDA are supplied by the same power plane and the recommended VDDA filter is used (see Figure 6). VDDOL may be applied at any time before or after VDD and VDDA are applied. If VDD and VDDA are not supplied by the same power plane, VDDA must be powered on before or at the same time VDD is applied. The VDDOL supply voltage may be applied at any time. ICS814S208BKILF REVISION B OCTOBER 13, 2011 12 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER 3.3V LVPECL Clock Input Interface The REF_CLK/nREF_CLK accepts LVPECL, LVDS, CML and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the REF_CLK/nREF_CLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 3.3V 3.3V 3.3V R1 50Ω Zo = 50Ω REF_CLK Zo = 50Ω nREF_CLK R1 100 Zo = 50Ω nREF_CLK R2 50Ω 3.3V 3.3V Zo = 50Ω REF_CLK CML LVPECL Input CML Built-In Pullup LVPECL Input Figure 2A. REF_CLK/nREF_CLK Input Driven by an IDT Open Collector CML Driver Figure 2B. REF_CLK/nREF_CLK Input Driven by a Built-In Pullup CML Driver 3.3V 3.3V 3.3V Zo = 50Ω REF_CLK Zo = 50Ω nREF_CLK Zo = 50Ω C2 R3 125 R4 125 3.3V 3.3V 3.3V R3 84 Zo = 50Ω C1 REF_CLK R4 84 3.3V LVPECL nREF_CLK R5 100 - 200 R6 100 - 200 R1 125 R2 125 LVPECL R1 84 R2 84 LVPECL Input LVPECL Input Figure 2C. REF_CLK/nREF_CLK Input Driven by a 3.3V LVPECL Driver Figure 2D. REF_CLK/nREF_CLK Input Driven by a 3.3V LVPECL Driver with AC Couple 3.3V 3.3V 3.3V Zo = 50Ω C1 REF_CLK R5 100 Zo = 50Ω C2 nREF_CLK R1 1k R2 1k R3 1k R4 1k LVDS LVPECL Input Figure 2E. REF_CLK/nREF_CLK Input Driven by a 3.3V LVDS Driver ICS814S208BKILF REVISION B OCTOBER 13, 2011 13 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 3A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and changing R2 to 50Ω. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 3B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. VCC XTAL_OUT R1 100 Ro Rs Zo = 50 ohms C1 XTAL_IN R2 100 .1uf Zo = Ro + Rs LVCMOS Driver Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface XTAL_OUT Zo = 50 ohms C2 XTAL_IN Zo = 50 ohms .1uf LVPECL Driver R1 50 R2 50 R3 50 Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface ICS814S208BKILF REVISION B OCTOBER 13, 2011 14 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. PIN SOLDER EXPOSED HEAT SLUG SOLDER PIN PIN PAD GROUND PLANE THERMAL VIA LAND PATTERN (GROUND PAD) PIN PAD Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ICS814S208BKILF REVISION B OCTOBER 13, 2011 15 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90Ω and 132Ω. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100Ω parallel resistor at the receiver and a 100Ω differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 5A can be used with either type of output structure. Figure 5B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. LVDS Driver ZO • Z T ZT LVDS Receiver Figure 5A. Standard Termination LVDS Driver Z O • ZT C ZT 2 LVDS ZT Receiver 2 Figure 5B. Optional Termination LVDS Termination Recommendations for Unused Input and Output Pins Inputs: REF_CLK/nREF_CLK Inputs For applications not requiring the use of the differential input, both REF_CLK and nREF_CLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from REF_CLK to ground. Outputs: LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. LVCMOS Output The unused LVCMOS output can be left floating. There should be no trace attached. Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ICS814S208BKILF REVISION B OCTOBER 13, 2011 16 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER Schematic Example Figure 6 shows an example of an ICS814S208I application schematic. In this example, the device is operated at a VDD = VDDOL = 3.3V. The 12pF parallel resonant 30.72MHz crystal is used. The load capacitance values C1 = 6.8pF and C2 = 6.8pF are recommended for frequency accuracy. Depending on the parasitics of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. For this device, the crystal load capacitors are required for proper operation. As with any high speed analog circuitry, the power supply pins are vulnerable to noise. To achieve optimum jitter performance, power supply isolation is required. The ICS814S208I provides separate power supplies to isolate from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uF capacitor in each power pin filter should be placed on the device side of the PCB and the other components can be placed on the opposite side. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. Logic Control Input Examples VDDA VDD R1 10 Set Logic Input to '1' RU1 1K VDD Set Logic Input to '0' RU2 Not Install VDD BW0 BW1 nOE_B0 BYPASS REF_SEL C3 0.1u C4 10u To Logic Input pins RD1 Not Install RD2 1K To Logic Input pins 48 47 46 45 44 43 42 41 40 39 38 37 N_SEL nOE_B1 nOE_B2 nOE_A QA + Zo_Dif f = 100 Ohm nQA VDD VDD nQB7 QB7 nQB6 QB6 GND VDD nQB5 QB5 nQB4 QB4 GND 36 35 34 33 32 31 30 29 28 27 26 25 R2 100 - C1 6.8pF X1 30.72MHz 12pF C2 6.8pF VDD R3 125 R4 125 GN D R E F _S EL BYPA SS nO E_B0 BW 1 BW 0 VD D A GN D N _S EL nO E_B1 nO E_B2 nO E _A VDD U1 XTAL_IN XTAL_OUT REF_CLK nREF_CLK VDDOL QLOCK QA nQA R5 1 2 3 4 5 6 7 8 9 10 11 12 XTAL_IN XTAL_OUT VDD REF_CLK nREF_CLK GND VDDOL QLOCK GND QA nQA VDD LVDS Termination VDD=3.3V VDDOL=3.3V Zo = 50 2.2K GN D QB0 nQ B0 QB1 nQ B1 VD D GN D QB2 nQ B2 QB3 nQ B3 VD D PA D QB7 R6 50 13 14 15 16 17 18 19 20 21 22 23 24 LVPECL Driv er R7 84 R8 84 VDD nQB7 3.3V 1 C6 0.1uF 3.3V 1 C9 0.1uF BLM18BB221SN1 2 Ferrite Bead C7 (U1:7) C8 10uF 0.1uF VDDOL 49 Zo = 50 LD1 Zo_Dif f = 100 Ohm + C5 0.1uF R9 50 - Alternate LVDS Termination BLM18BB221SN1 2 Ferrite Bead C10 (U1:3) (U1:12) (U1:18) (U1:24) C11 10uF 0.1uF C12 0.1uF C13 0.1uF C14 0.1uF (U1:30) (U1:36) C15 0.1uF C16 0.1uF VDD Figure 6. ICS814S208I Schematic Example ICS814S208BKILF REVISION B OCTOBER 13, 2011 17 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER Power Considerations This section provides information on power dissipation and junction temperature for the ICS814S208I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS14S208I is the sum of the core power plus the analog power plus the power dissipation in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. The maximum current at 85°C is as follows: IDD_MAX = 332mA IDDA_MAX = 20mA • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (332mA + 20mA) = 1219.68mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 30.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 1.220W * 30.5°C/W = 122.2°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance θJA for 48 Lead VFQFN, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 30.5°C/W 1 26.7°C/W 2.5 23.9°C/W ICS814S208BKILF REVISION B OCTOBER 13, 2011 18 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER Reliability Information Table 8. θJA vs. Air Flow Table for a 48-lead VFQFN θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 30.5°C/W 1 26.7°C/W 2.5 23.9°C/W Transistor Count The transistor count for ICS814S208I is: 9,137 ICS814S208BKILF REVISION B OCTOBER 13, 2011 19 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER Package Outline and Package Dimensions Package Outputline -K Suffix for 48 Lead VFQFN Bottom View w/Type A ID 2 1 CHAMFER 4 N N-1 Bottom View w/Type C ID 2 1 RADIUS 4 N N-1 There are 2 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) Table 9. PackageDimensions for 48 Lead VFQFN Symbol N A A1 A3 b D&E D1 & E1 D2 & E2 e R ZD & ZE L All Dimensions in Millimeters Minimum Nominal Maximum 48 0.8 0.9 0 0.02 0.05 0.2 Ref. 0.18 0.25 0.30 7.00 Basic 5.50 Basic 5.50 5.65 5.80 0.50 Basic 0.20~0.25 0.75 Basic 0.35 0.40 0.45 Reference Document: IDT Drawing #PSC-4203 ICS814S208BKILF REVISION B OCTOBER 13, 2011 20 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER Ordering Information Table 10. Ordering Information Table Part/Order Number 814S208BKILF 814S208BKILFT Marking ICS814S208BIL ICS814S208BIL Package Lead-Free, 48-lead VFQFN Lead-Free, 48-lead VFQFN Shipping Packaging Tray 1000 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS814S208BKILF REVISION B OCTOBER 13, 2011 21 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER Revision History Sheet Rev B Table T6 Page 8 16 Description of Change AC Characteristics Table - added Period JItter spec for QBx, nQBx outputs at 122.88MHz. Updated LVDS Termination application note. Date 10/13/11 ICS814S208BKILF REVISION B OCTOBER 13, 2011 22 ©2011 Integrated Device Technology, Inc. ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2011. All rights reserved.