830154AGI-08LFT

Over-Voltage Tolerant 1.5V, 1:4 Fanout Buffer ICS830154I-08 DATA SHEET General Description The ICS830154I-08 is an LVCMOS, over-voltage tolerant clock fanout buffer targeted for clock HiPerClockS™ generation in high-performance telecommunication, networking and computing applications. The device is optimized for low-skew clock distribution in low-voltage applications. The input over-voltage tolerance enables using this device in mixed-mode voltage applications. An output enable pin controls whether the outputs are in the active or high impedance state. Guaranteed output skew characteristics make the ICS830154I-08 ideal for those applications demanding well defined performance and repeatability. The ICS830154I-08 is packaged in a small 8-TSSOP and in an 8-SOIC package. Features • • • • • • • • • Low-skew 1:4 fanout buffer Supports 3.3V, 2.5V, 1.8V and 1.5V power supplies LVCMOS input and output levels 3.6V Over-voltage tolerance at the clock and control inputs Supports clock frequencies up to 160MHz LVCMOS compatible control input for output disable Output disabled to a high-impedance state -40°C to 85°C ambient operating temperature Available in lead-free RoHS 6 packages (8-TSSOP, 8-SOIC) ICS Block Diagram CLK_IN Pulldown Pin Assignments Q1 Q2 Q3 Q4 CLK_IN Q1 Q2 Q3 1 2 3 4 8 7 6 5 OE VDD GND Q4 ICS830154AMI-08 8-SOIC, 150 mil 3.9mm x 4.9mm x 1.375mm package body M-Package Top View ICS830154AGI-08 8-TSSOP 4.4mm x 3.0mm x 0.925mm package body G-Package Top View OE Pullup ICS830154AGI-08 REVISION A MARCH 29, 2010 1 ©2010 Integrated Device Technology, Inc. ICS830154I-08 Data Sheet OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER Table 1. Pin Descriptions Number 1 2 3 4 5 6 7 8 Name CLK_IN Q1 Q2 Q3 Q4 GND VDD OE Input Output Output Output Output Power Power Input Pullup Type Pulldown Description Single-ended clock input. LVCMOS interface levels. Single-ended clock output. LVCMOS interface levels. Single-ended clock output. LVCMOS interface levels. Single-ended clock output. LVCMOS interface levels. Single-ended clock output. LVCMOS interface levels. Power supply ground. Power supply pin. Output enable pin. See Table 3. LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol CIN Parameter Input Capacitance VDD = 3.465V CPD Power Dissipation Capacitance VDD = 2.375V VDD = 1.95V VDD = 1.6V RPULLUP Input Pullup Resistor Test Conditions Minimum Typical 4 14 13 13 12 51 51 VDD = 3.3V ± 5% ROUT Output Impedance VDD = 2.5V ± 5% VDD = 1.8V ± 0.15V VDD = 1.5 ± 0.1V 9 10 12 15 Maximum Units pF pF pF pF pF kΩ kΩ RPULLDOWN Input Pulldown Resistor Ω Ω Ω Ω Function Table Table 3. OE Configuration Table Input OE 0 1 (default) Operation Q[4:1] disabled (high-impedance) Q[4:1] enabled NOTE: OE is an asynchronous control. ICS830154AGI-08 REVISION A MARCH 29, 2010 2 ©2010 Integrated Device Technology, Inc. ICS830154I-08 Data Sheet OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, θJA 8 Lead TSSOP 8 Lead SOIC Storage Temperature, TSTG Rating 4.6V 3.6V -0.5V to VDD + 0.5V 121.5°C/W (0 mps) 103°C/W (0 mps) -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol VDD IDDQ Parameter Power Supply Voltage Quiescent Power Supply Current Inputs Open, Outputs Unloaded Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 1 Units V mA Table 4B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol VDD IDDQ Parameter Power Supply Voltage Quiescent Power Supply Current Inputs Open, Outputs Unloaded Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 1 Units V mA Table 4C. Power Supply DC Characteristics, VDD = 1.8V ± 0.15V, TA = -40°C to 85°C Symbol VDD IDDQ Parameter Power Supply Voltage Quiescent Power Supply Current Inputs Open, Outputs Unloaded Test Conditions Minimum 1.65 Typical 1.8 Maximum 1.95 1 Units V mA Table 4D. Power Supply DC Characteristics, VDD = 1.5V ± 0.1V, TA = -40°C to 85°C Symbol VDD IDDQ Parameter Power Supply Voltage Quiescent Power Supply Current Inputs Open, Outputs Unloaded Test Conditions Minimum 1.4 Typical 1.5 Maximum 1.6 1 Units V mA ICS830154AGI-08 REVISION A MARCH 29, 2010 3 ©2010 Integrated Device Technology, Inc. ICS830154I-08 Data Sheet OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER Table 4E. LVCMOS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage CLK_IN Input High Current OE CLK_IN IIL VOH VOL Input Low Current OE Output High Voltage Output Low Voltage Q[4:1] Q[4:1] VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V IOH = -12mA IOL = 12mA -5 -150 2.6 0.5 Test Conditions Minimum 0.65 * VDD -0.3 Typical Maximum 3.6 0.35 * VDD 150 5 Units V V µA µA µA µA V V Table 4F. LVCMOS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage CLK_IN Input High Current OE CLK_IN IIL VOH VOL Input Low Current OE Output High Voltage Output Low Voltage Q[4:1]] Q[4:1] VDD = VIN = 2.625V VDD = VIN = 2.625V VDD = 2.625V, VIN = 0V VDD = 2.625V, VIN = 0V IOH = -12mA IOL = 12mA -5 -150 1.8 0.5 Test Conditions Minimum 0.65 * VDD -0.3 Typical Maximum 3.6 0.35 * VDD 150 5 Units V V µA µA µA µA V V Table 4G. LVCMOS DC Characteristics, VDD = 1.8V ± 0.15V, TA = -40°C to 85°C Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage CLK_IN Input High Current OE CLK_IN IIL VOH VOL Input Low Current OE Output High Voltage Output Low Voltage Q[4:1] Q[4:1] VDD = 1.95V, VIN = 0V VDD = 1.95V, VIN = 0V IOH = -6mA IOL = 6mA -5 -150 VDD – 0.45 0.45 VDD = VIN = 1.95V Test Conditions Minimum 0.65 * VDD -0.3 Typical Maximum 3.6 0.35 * VDD 150 5 Units V V µA µA µA µA V V ICS830154AGI-08 REVISION A MARCH 29, 2010 4 ©2010 Integrated Device Technology, Inc. ICS830154I-08 Data Sheet OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER Table 4H. LVCMOS DC Characteristics, VDD = 1.5V ± 0.1V, TA = -40°C to 85°C Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage CLK_IN Input High Current OE CLK_IN IIL VOH VOL Input Low Current OE Output High Voltage Output Low Voltage Q[4:1] Q[4:1] VDD = VIN = 1.6V VDD = VIN = 1.6V VDD = 1.6V, VIN = 0V VDD = 1.6V, VIN = 0V IOH = -4mA IOL = 4mA -5 -150 0.75 * VDD 0.25 * VDD Test Conditions Minimum 0.65 * VDD -0.3 Typical Maximum 3.6 0.35 * VDD 150 5 Units V V µA µA µA µA V V AC Electrical Characteristics Table 5A. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol fOUT tpLH tpHL tPLZ, tPHZ tPZL, tPZH tsk(o) tsk(pp) tjit t R / tF odc Parameter Output Frequency Propagation Delay (low to high transition); NOTE 1 Propagation Delay (high to low transition); NOTE 1 Disable Time (active to high-impedance) Enable Time (high-impedance to disable) Output Skew; NOTE 2, 3 Part-to-Part Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time Output Duty Cycle 25MHz, Integration Range: 12kHz - 5MHz 10% to 90% 0.35 48 0.094 1.2 52 0.7 0.7 Test Conditions Minimum Typical Maximum 160 1.45 1.45 10 10 250 800 Units MHz ns ns ns ns ps ps ps ns % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized up to FOUT ≤ 150MHz. NOTE 1: Measured from the VDD/2 of the input to VDD/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2. ICS830154AGI-08 REVISION A MARCH 29, 2010 5 ©2010 Integrated Device Technology, Inc. ICS830154I-08 Data Sheet OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER Table 5B. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol fOUT tpLH tpHL tPLZ, tPHZ tPZL, tPZH tsk(o) tsk(pp) tjit t R / tF odc Parameter Output Frequency Propagation Delay (low to high transition); NOTE 1 Propagation Delay (high to low transition); NOTE 1 Disable Time (active to high-impedance) Enable Time (high-impedance to disable) Output Skew; NOTE 2, 3 Part-to-Part Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time Output Duty Cycle 25MHz, Integration Range: 12kHz - 5MHz 10% to 90% 0.35 48 0.076 1.2 52 0.8 0.8 Test Conditions Minimum Typical Maximum 160 1.7 1.7 10 10 250 800 Units MHz ns ns ns ns ps ps ps ns % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized up to FOUT ≤ 150MHz. NOTE 1: Measured from the VDD/2 of the input to VDD/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2. Table 5C. AC Characteristics, VDD = 1.8V ± 0.15V, TA = -40°C to 85°C Symbol fOUT tpLH tpHL tPLZ, tPHZ tPZL, tPZH tsk(o) tsk(pp) tjit t R / tF odc Parameter Output Frequency Propagation Delay (low to high transition); NOTE 1 Propagation Delay (high to low transition); NOTE 1 Disable Time (active to high-impedance) Enable Time (high-impedance to disable) Output Skew; NOTE 2, 3 Part-to-Part Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time Output Duty Cycle 25MHz, Integration Range: 12kHz - 5MHz 0.63V to 1.17V 0.12 47 0.193 0.6 53 1.1 1.1 Test Conditions Minimum Typical Maximum 160 2.1 2.1 10 10 250 800 Units MHz ns ns ns ns ps ps ps ns % For NOTES, see Table 5B above. ICS830154AGI-08 REVISION A MARCH 29, 2010 6 ©2010 Integrated Device Technology, Inc. ICS830154I-08 Data Sheet OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER Table 5D. AC Characteristics, VDD = 1.5V ± 0.1V, TA = -40°C to 85°C Symbol fOUT tpLH tpHL tPLZ, tPHZ tPZL, tPZH tsk(o) tsk(pp) tjit t R / tF odc Parameter Output Frequency Propagation Delay (low to high transition); NOTE 1 Propagation Delay (high to low transition); NOTE 1 Disable Time (active to high-impedance) Enable Time (high-impedance to disable) Output Skew; NOTE 2, 3 Part-to-Part Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time Output Duty Cycle 25MHz, Integration Range: 12kHz - 5MHz 0.525V to 0.975V 0.12 47 0.266 0.6 53 1.5 1.5 Test Conditions Minimum Typical Maximum 160 2.7 2.7 10 10 250 800 Units MHz ns ns ns ns ps ps ps ns % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized up to FOUT ≤ 150MHz. NOTE 1: Measured from the VDD/2 of the input to VDD/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2. ICS830154AGI-08 REVISION A MARCH 29, 2010 7 ©2010 Integrated Device Technology, Inc. ICS830154I-08 Data Sheet OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER Additive Phase Jitter (1.5V Output) The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase Jitter @ 25MHz 12kHz to 5MHz = 0.266ps (typical) SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. The source generator "IFR2042 10kHz – 56.4GHz Low Noise Signal Generator as external input to an Agilent 8133A 3GHz Pulse Generator". ICS830154AGI-08 REVISION A MARCH 29, 2010 8 ©2010 Integrated Device Technology, Inc. ICS830154I-08 Data Sheet OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER Parameter Measurement Information 1.65V±5% 1.25V±5% VDD SCOPE LVCMOS Qx VDD SCOPE LVCMOS Qx GND GND -1.65V±5% -1.25V±5% 3.3V Output Load AC Test Circuit 2.5V Output Load AC Test Circuit 0.9V±0.075V 0.75V±0.05V VDD SCOPE LVCMOS Qx VDD SCOPE LVCMOS Qx GND GND -0.9V±0.075V -0.75V±0.05V 1.8V Output Load AC Test Circuit 1.5V Output Load AC Test Circuit V Qx Par t 1 V Qx DD DD 2 2 Par t 2 V DD V Qy DD 2 t sk(o) Qy 2 t sk(pp) Output Skew Part-to-Part Skew ICS830154AGI-08 REVISION A MARCH 29, 2010 9 ©2010 Integrated Device Technology, Inc. ICS830154I-08 Data Sheet OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER Parameter Measurement Information, continued OE (High-level enabling) VDD VDD/2 VDD/2 0V Q1:Q4 V DD V DD 2 2 t PW t PERIOD tEN Output Qx (See Note) VDD/2 tDIS VOH VDD/2 odc = t PW t PERIOD x 100% Output Enable/Disable Time Output Duty Cycle/Pulse Width/Period 0.975V 0.975V 0.63V 1.17V 1.17V Q1:Q4 0.525V tR tF 0.525V Q1:Q4 0.63V tR tF 1.5V Output Rise/Fall Time 1.8V Output Rise/Fall Time VDD VDD 2 VDD VDD 2 tpHL 90% 90% CLK_IN 2 Q1:Q4 10% tR tF 10% Q1:Q4 2 tpLH 2.5V and 3.3V Output Rise/Fall Time Propagation Delay ICS830154AGI-08 REVISION A MARCH 29, 2010 10 ©2010 Integrated Device Technology, Inc. ICS830154I-08 Data Sheet OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER Applications Information Recommendations for Unused Output Pins Outputs: LVCMOS Outputs All unused LVCMOS outputs can be left floating. There should be no trace attached. ICS830154AGI-08 REVISION A MARCH 29, 2010 11 ©2010 Integrated Device Technology, Inc. ICS830154I-08 Data Sheet OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS830154I-08. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for theICS830154I-08 is the sum of the core power plus the power dissipation in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V *1mA = 3.465mW Total Static Power: = Power (core)MAX = 3.465mW Dynamic Power Dissipation at FOUT_MAX (160MHz) Total Power (160MHz) = [(CPD * N) * Frequency * (VDDO)2] = [(14pF *4) * 160MHz * (3.465V)2] = 107.6mW N = number of outputs Total Power = Static Power + Dynamic Power Dissipation = 3.465mW + 107.6mW = 111.065mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 121.5°C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.111W *121.5°C/W = 98.5°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6A. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 121.5°C/W 1 117.3°C/W 2.5 115.3°C/W Table 6B. Thermal Resistance θJA for 8 Lead SOIC, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS830154AGI-08 REVISION A MARCH 29, 2010 0 103°C/W 12 1 94°C/W 2.5 89°C/W ©2010 Integrated Device Technology, Inc. ICS830154I-08 Data Sheet OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER Reliability Information Table 7A. θJA vs. Air Flow Table for a 8 Lead TSSOP θJA vs. Air Flow Meter per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 121.5°C/W 1 117.3°C/W 2.5 115.3°C/W Table 7B. θJA vs. Air Flow Table for a 8 Lead SOIC θJA vs. Air Flow Meter per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 103°C/W 1 94°C/W 2.5 89°C/W Transistor Count The transistor count for ICS830154I-08 is: 191 ICS830154AGI-08 REVISION A MARCH 29, 2010 13 ©2010 Integrated Device Technology, Inc. ICS830154I-08 Data Sheet OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER Package Outline and Package Dimensions Package Outline - G Suffix for 8 Lead TSSOP Package Outline - M Suffix for 8 Lead SOIC Table 8A. Package Dimensions for 8Lead TSSOP All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 Table 8B. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 Basic H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-012 ICS830154AGI-08 REVISION A MARCH 29, 2010 14 ©2010 Integrated Device Technology, Inc. ICS830154I-08 Data Sheet OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER Ordering Information Table 9. Ordering Information Part/Order Number 830154AGI-08LF 830154AGI-08LFT 830154AMI-08LF 830154AMI-08LFT Marking AI08L AI08L 154AI08L 154AI08L Package Lead-Free, 8 Lead TSSOP Lead-Free, 8 Lead TSSOP Lead-Free, 8 Lead SOIC Lead-Free, 8 Lead SOIC Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS830154AGI-08 REVISION A MARCH 29, 2010 15 ©2010 Integrated Device Technology, Inc. ICS830154I-08 Data Sheet OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2010. All rights reserved.